this paper presents the complexity analysis of bit parallel multiplier in polynomial basis on FPGAs, both without and with carry logic. We directly present the Look-Up-Table (LUT) complexity and estimate the resource ...
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ISBN:
(纸本)9781424419609
this paper presents the complexity analysis of bit parallel multiplier in polynomial basis on FPGAs, both without and with carry logic. We directly present the Look-Up-Table (LUT) complexity and estimate the resource upper bound based on the existed gate-oriented architectures. Experimental results show that no FPGA synthesis tool reaches the estimated upper bound. Furthermore, the area optimization with fast carry logic can save additional 17% resources. the implementation results with manually mapped design on a Xilinx Virtex-4 device are reported.
Implementing convolutional neural networks for scene labelling is a current hot topic in the field of advanced driver assistance systems. the massive computational demands under hard real-time and energy constraints c...
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ISBN:
(纸本)9789090304281
Implementing convolutional neural networks for scene labelling is a current hot topic in the field of advanced driver assistance systems. the massive computational demands under hard real-time and energy constraints can only be tackled using specialized architectures. Also, cost-effectiveness is an important factor when targeting lower quantities. In this PhD thesis, a vector processor architecture optimized for FPGA devices is proposed. Amongst other hardware mechanisms, a novel complex operand addressing mode and an intelligent DMA are used to increase perfromance. Also, a C-compiler support for creating applications is introduced.
this paper introduces a new flow able to fit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. the flow is based on iterative refactoring and transformations of...
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ISBN:
(纸本)9781424410590
this paper introduces a new flow able to fit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. the flow is based on iterative refactoring and transformations of the application. From the resulting application, a VHDL code is generated. this code is finally used to simulate or synthesize the application. Significant experiments have validated the approach.
Physically unclonable functions are used for IP protection, hardware authentication and supply chain security. While many PUF constructions have been put forward in the past decade, only few of them are applicable to ...
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ISBN:
(纸本)9789090304281
Physically unclonable functions are used for IP protection, hardware authentication and supply chain security. While many PUF constructions have been put forward in the past decade, only few of them are applicable to FPGA platforms. Strict constraints on the placement and routing are the main disadvantages of the existing PUFs on FPGAs, because they place a high effort on the designer. In this paper we propose a new delay-based PUF construction called Monte Carlo PUF, that does not require low-level placement and routing control. this construction relies on the on-chip Monte Carlo method that is applied for measuring the delays of logic elements in order to extract a unique device fingerprint. the proposed construction allows a trade-off between the evaluation time and the error rate. the Monte Carlo PUF is implemented and evaluated on Xilinx Spartan-6 FPGAs.
Variable-latency, or speculative, addition is an effective technique to implement fast adders working on very long operands. Most approaches to speculative addition are either based on the assumption that operands hav...
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ISBN:
(纸本)9781467381239
Variable-latency, or speculative, addition is an effective technique to implement fast adders working on very long operands. Most approaches to speculative addition are either based on the assumption that operands have equiprobable independent bits, which is rarely the case in real applications due to sign-extension, or they can handle the case of signed numbers at the price of a considerable area overhead. Furthermore, many existing approaches require ad-hoc schemes preventing the reuse of standard adders typically available as optimized library components in many technologies, most notably field-programmable Gate Arrays. this paper introduces an innovative scheme for speculative addition that effectively addresses both problems, yielding fast and low-area circuits able to handle sign-extended numbers speculatively and only made of optimized carry-propagation adders based on fast carry circuitry as basic building blocks.
FPGAs are used in many long-life systems that serve mission-critical needs. the supply chain and life-cycle management of these devices have long relied on ensuring adequate controls are in place. In this paper, a tec...
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ISBN:
(纸本)9782839918442
FPGAs are used in many long-life systems that serve mission-critical needs. the supply chain and life-cycle management of these devices have long relied on ensuring adequate controls are in place. In this paper, a technique is presented that provides measurement vectors by determining both characteristics of the supply properties of the FPGA and characteristics of aging of the FPGA. Asynchronous ring oscillators are placed throughout the FPGA, and the measurement of these oscillators is compared to other chips both within a manufacturing lot and between other manufacturing lots. through these non-invasive measurements, the "health history" of the FPGA can be evaluated and utilized in supply chain decisions before and during system operation.
One of the most important topics of today is a packet processing in data centers with respect to the power consumption and efficient utilization of computational resources. the ARM architecture has proved to be an ene...
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ISBN:
(纸本)9782839918442
One of the most important topics of today is a packet processing in data centers with respect to the power consumption and efficient utilization of computational resources. the ARM architecture has proved to be an energy efficient computational system. Together with an integrated FPGA on a single die, it offers potentially a high performance with respect to the power consumption. DPDK - a set of libraries and drivers intended primarily for fast packet processing - is becoming to be a standard approach for packet processing, especially in data centers. In this paper, we exploit the potential of packet processing based on DPDK and FPGA SoC architectures. Especially, we aim at the potential of utilizing the ARM Cortex-A9 and Cortex-A53 CPUs.
Current trends show, it is increasingly difficult to manage the constraints of costs, power consumption, size and more than everything else, functional safety, with conventional architectures. this paper presents a ne...
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ISBN:
(纸本)9781424438914
Current trends show, it is increasingly difficult to manage the constraints of costs, power consumption, size and more than everything else, functional safety, with conventional architectures. this paper presents a new architecture to deal withthe current and upcoming requirements in safety critical applications. It proposes the use of diverse redundancy with digital and analog channels, to detect random hardware failures as well as systematic failures. that will increase the functional safety. By exploiting the ability of dynamic and partial hardware reconfiguration of FPGA and FPAA and by using the appropriate failure recovery scenario, the system availability can also be increased. Furthermore, the architecture offers the possibility to combine high accuracy with short response time.
As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architectur...
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ISBN:
(纸本)9781424419609
As the use of FPGAs increases, the importance of highly optimized processors for FPGAs will increase. In this paper we present the microarchitecture of a soft microprocessor core optimized for the Virtex-4 architecture. the core can operate at 357 MHz, which is significantly faster than Xilinx' Microblaze architecture on the same FPGA. At this frequency it is necessary to keep the logic complexity down and this paper shows how this can be done while retaining C, sufficient functionality for a high performance processor.
Many CPU design houses have added dedicated support for cryptography in recent processor generations, including Intel, IBM, and ARM. While adding accelerators and/or dedicated instructions boosts performance on crypto...
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ISBN:
(纸本)9789090304281
Many CPU design houses have added dedicated support for cryptography in recent processor generations, including Intel, IBM, and ARM. While adding accelerators and/or dedicated instructions boosts performance on cryptography, we are investigating a different approach that is not adding extra silicon area: We study to replace the hardened NEON SIMD unit of an ARM Cortex-A9 with an identical sized FPGA fabric, called an interlay. this will be used for implementing cryptographic instructions in soft-logic. We show that this approach can outperform the hardened NEON by up to 7.7 x on AES and provide functionality that is not available in the hardened ARM.
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