检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,087 篇 会议
31 篇 期刊文献
8 册 图书

馆藏范围

2,126 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,363 篇 工学
- 1,143 篇 计算机科学与技术...
- 757 篇 软件工程
- 452 篇 电气工程
- 226 篇 电子科学与技术（可...
- 90 篇 信息与通信工程
- 79 篇 控制科学与工程
- 41 篇 机械工程
- 38 篇 仪器科学与技术
- 32 篇 动力工程及工程热...
- 29 篇 建筑学
- 19 篇 土木工程
- 19 篇 生物工程
- 17 篇 核科学与技术
- 15 篇 光学工程
- 13 篇 生物医学工程（可授...
- 9 篇 材料科学与工程（可...
- 9 篇 安全科学与工程
- 8 篇 交通运输工程
- 6 篇 石油与天然气工程
181 篇 理学
- 104 篇 数学
- 43 篇 物理学
- 22 篇 生物学
- 20 篇 系统科学
- 13 篇 统计学（可授理学、...
- 8 篇 化学
53 篇 管理学
- 41 篇 管理科学与工程(可...
- 21 篇 工商管理
- 15 篇 图书情报与档案管...
17 篇 法学
- 15 篇 社会学
13 篇 医学
11 篇 经济学
- 11 篇 应用经济学
6 篇 军事学
5 篇 农学
3 篇 教育学

主题

947 篇 field programmab...
735 篇 field programmab...
322 篇 hardware
172 篇 computer archite...
146 篇 logic gates
130 篇 table lookup
115 篇 clocks
96 篇 throughput
94 篇 random access me...
85 篇 routing
82 篇 software
80 篇 acceleration
75 篇 delays
74 篇 optimization
67 篇 kernel
62 篇 logic
62 篇 switches
61 篇 registers
56 篇 algorithm design...
52 篇 parallel process...

机构

17 篇 univ toronto dep...
9 篇 imperial coll lo...
9 篇 ecole polytech f...
8 篇 department of co...
8 篇 tokyo inst techn...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
6 篇 univ tsukuba tsu...
6 篇 xilinx inc 2100 ...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 department of el...
5 篇 fudan univ state...

作者

31 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
13 篇 ienne paolo
12 篇 wayne luk
12 篇 wilton steven j....
12 篇 betz vaughn
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
11 篇 chow paul
10 篇 constantinides g...
9 篇 vaughn betz
9 篇 prasanna viktor ...
8 篇 kapre nachiket
8 篇 suhaib a. fahmy
8 篇 alonso gustavo
8 篇 hutchings brad
8 篇 paolo ienne
8 篇 habib mehrez
8 篇 amano hideharu

语言

2,111 篇 英文
9 篇 其他
5 篇 中文
1 篇 俄文

检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

共 2126 条记录，以下是11-20 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A Software-programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs 34

A Software-Programmable Neural Processing Unit for Graph Neu...

引用

34th international conference on field-programmable logic and applications (FPL)

作者： Zhang, Taikun Boutros, Andrew Gribok, Sergey Boateng, Kwadwo Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Intel Corp Programmable Solut Grp Santa Clara CA 95054 USA

ISBN: (纸本)9798331530082;9798331530075

Graph neural networks (GNNs) are a widely-used class of deep learning (DL) models for learning latent representations of graph-structured data for a variety of node/graph-level prediction tasks, some of which require real-time low latency inference. Most existing GNN accelerators rely on preprocessing input graphs on a host/embedded CPU to parallelize computations on different sub-graphs, making them unsuitable for real-time use cases. Others are extremely specialized streaming pipelines for only a specific type of GNN and therefore suffer from long FPGA bitstream compile times when the model is updated and cannot be used in applications that combine GNNs with other classes of DL models. In this work, we enhance the neural processing unit (NPU) FPGA overlay architecture, instruction set, and software stack to support a variety of GNN models. We achieve this without sacrificing the NPU flexibility;our enhanced NPU can be programmed purely through software to accelerate different GNNs or any of its originally supported DL workloads (e.g. MLPs, RNNs, GRUs, LSTMs). In addition, this flexibility enables our NPU software compiler to generate GNN kernels with different performance targets (throughput-optimized vs. latency-optimized) by exploiting different dimensions of compute parallelism on the same overlay architecture. Besides the flexibility benefits, our NPU implemented on an Intel Stratix 10 NX (14nm) FPGA can process 7.8x more graphs per second at a similar latency on average compared to a state-of-the-art model-specific FPGA accelerator targeting real-time applications on an AMD Ultrascale+ same-generation FPGA. It also achieves 5.8x higher throughput compared to an Nvidia RTX A6000 GPU (8nm) and 2.6x lower latency than a state-of-the-art accelerator that combines CPU-based graph preprocessing with AMD Versal (7nm) fabric and AI engine compute. Finally, we present a case study for using our enhanced NPU in real-time GNN-based multi-input multi-output (MIMO) antenn

关键词： Graph neural networks

来源：评论

学校读者我要写书评

暂无评论

eGPU: A 750 MHz Class Soft GPGPU for FPGA 33

eGPU: A 750 MHz Class Soft GPGPU for FPGA

引用

33rd international conference on field-programmable logic and applications (FPL)

作者： Langhammer, Martin Constantinides, George A. Intel Corp Programmable Solut Grp Santa Clara CA 95051 USA Imperial Coll London Elect & Elect Engn London England

ISBN: (纸本)9798350341515

this paper introduces the eGPU, a SIMT soft processor designed for FPGAs. Soft processors typically achieve modest operating frequencies, a fraction of the headline performance claimed by modern FPGA families, and obtain correspondingly modest performance results. We propose a GPGPU architecture structured specifically to take advantage of both the soft logic and embedded features of the FPGA. We also consider the physical location of the embedded memories and DSP Blocks relative to the location and number of soft logic elements in order to have a design with balanced resources. Our goal is to create a high performance soft processor able to implement complex portions of FPGA system designs, such as the linear solvers commonly used in wireless systems, through push-button compilation from software. the eGPU architecture is a streaming multiprocessor (SM) machine with 512 threads. Each SM contains 16 scalar processors (SP). Both IEEE754 FP32 and INT32 integer arithmetic are supported. We demonstrate a single SM eGPU in an Intel Agilex device, requiring 5600 ALMs and 24 DSP Blocks, which closes timing at over 770 MHz from a completely unconstrained compile. Multiple eGPUs can also be tightly packed together into a single Agilex FPGA logic region, with minimal speed penalty.

关键词： GPGPU FPGA

来源：评论

学校读者我要写书评

暂无评论

Angle Measurement Method Based on Cross-Orthogonal Hall Sensor 16

Angle Measurement Method Based on Cross-Orthogonal Hall Sens...

引用

16th IEEE international conference on Electronic Measurement and Instruments, ICEMI 2023

作者： Chen, Xiao He, Xiran Zhang, Ying Gao, Bo Sichuan University Department of Physics Chengdu China

ISBN: (纸本)9798350327144

Angle measurement sensors have gained widespread application in fields of automobiles, machinery, and other industries. the cross-orthogonal architecture based on Hall sensors is proposed to position angle. Meanwhile, A novel angle calibration algorithm effectively reduces the error caused by the offset voltage, the unequal amplitude and the additional harmonics. A special FPGA test has been designed to measure the angle of rotation of the artificial magnetic field and verify the proposed methods. the angle measurement results show an average measured error of ± 1.263°, which can meet the requirements of industrial and practical applications. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

field programmable Gate Array: An Extensive Review, Recent Trends, Challenges and applications 18

Field Programmable Gate Array: An Extensive Review, Recent T...

引用

18th INDIAcom;11th international conference on Computing for Sustainable Global Development, INDIACom 2024

作者： Badhoutiya, Arti Jaffer, Zainb Hussein, Heba Mohammed Juyal, Ashima Mittal, Manisha Anand, Rohit Gla University Department of Electrical Engineering Mathura India Al-Farahidi University Medical Technical College Iraq Al-Zahrawi University College Department of Dentistry Karbala Iraq Uttaranchal Institute of Technology Uttaranchal University Department of Ece Dehradun India Gtbit Department of Ece New Delhi India New Delhi India

ISBN: (纸本)9789380544519

A field programmable gate array (FPGA) is a type of programmable logic device that the consumer can modify after production to carry out a variety of tasks, from fundamental logic gate operations to AI systems and beyond. More than 70,000 documents pertaining to FPGA have been found in the two most prominent scientific databases, Scopus and Clarivate Web of Science. these articles demonstrate the wide variety of FPGA-based applications, from navigation systems on Mars rovers to a new mechanism that allows the kilograms redefinition's magnetic suspension system. this paper provides a comprehensive overview of field-programmable gate arrays (FPGAs), taking readers on a journey from the basics to sophisticated programming techniques. No matter how much or how little experience you have with FPGA programming, this study will be an invaluable resource for filling in the gaps in your knowledge. Readers will have a solid grounding in essential topics including FPGA architecture, hardware description languages, and synthesis. the present work addresses critical subjects such as FPGA architecture, hardware description languages, and synthesis, thereby providing readers with a robust foundation. Furthermore, it boldly ventures into the domain of advanced topics, including high-level synthesis and parallel processing, amplifying its appeal to seasoned FPGA enthusiasts. It is unequivocally evident that this work serves as an indispensable resource, equipping individuals from diverse backgrounds with the proficiency to fully exploit the remarkable potential of FPGAs across a myriad of applications and industries. this study also provides an overview of the recent trends and evolution of the related applications. © 2024 Bharati Vidyapeeth, New Delhi.

关键词： advancement component FPDGs performance programming

来源：评论

学校读者我要写书评

暂无评论

applications of Fuzzy Set Models in Optimizing Agricultural Production Structures in Smart Farms 1

引用

23rd international conference on Next Generation Wired/Wireless Networks and Systems (NEW2AN) / 16th conference on Internet of things and Smart Spaces (RuSMART)

作者： Ishnazarov, Akram Mamasoliyev, Sarvar Tashkent State Univ Econ Dept Math Methods Econ Tashkent Uzbekistan

ISBN: (数字)9783031609978

ISBN: (纸本)9783031609961;9783031609978

this article emphasizes the application of fuzzy logic in the field of agriculture. the use of fuzzy logic is not restricted to specific agricultural domains, but rather extends from soil analysis to the entire process of plant production, encompassing various areas within agriculture. To gain a better understanding of fuzzy logic in agriculture, a concise and comprehensive literature review has been conducted. Crop yield estimation fuzzy logic involves the incorporation of input parameters such as productivity, area, and labor expenses. through the application of fuzzy arithmetic to these parameters, a precise crop yield value is obtained. the fuzzy modeling employs optimal membership functions. the accuracy of the results is verified by comparing them with existing open-source literature.

关键词： fuzzy logic fuzzy inference system membership functions fuzzy mathematical programming problems graded membership

来源：评论

学校读者我要写书评

暂无评论

Integration of a Trojan Detection Tool with BFDS: Enhancing field-programmable Gate Array Security 24

Integration of a Trojan Detection Tool with BFDS: Enhancing ...

引用

4th international conference on Artificial Intelligence, Automation and Algorithms

作者： Zhang, Yanlong Xiao, Ke Wang, Shuo Zhou, Jing Beijing Microelect Technol Inst Beijing Peoples R China

ISBN: (纸本)9798400717840

field-programmable gate arrays (FPGAs) have garnered considerable interest and utilization, largely owing to their inherent flexibility and customizability. In this context, electronic design automation (EDA) technology serves as an instrumental facilitator for FPGA applications. Nevertheless, the emergence of hardware Trojans (HTs) represents a major vulnerability in FPGA security. To mitigate the risks associated with hardware Trojans, a formula has been devised to compute the controllability and observability of each signal within logic units in look-up table (LUT) netlists. Subsequently, a security verification methodology aimed at HT detection within these LUT netlists has been developed and incorporated into the EDA tool, BFDS. Detailed procedural steps for HT detection, including interactions with the graphical user interface, are elucidated. the efficacy of this embedded HT detection tool is substantiated through experimental validation. the results from these experiments confirm the capacity of the tool to successfully identify Trojans at the LUT-level netlist while seamlessly integrating into EDA toolchains, thereby enhancing the security of future FPGA design endeavors.

关键词： hardware Trojan detection electronic design automation tool graphical user interface

来源：评论

学校读者我要写书评

暂无评论

Order Analysis Algorithm Based on Time-Domain Stretching and Its logic Implementation 16

Order Analysis Algorithm Based on Time-Domain Stretching and...

引用

16th IEEE international conference on Electronic Measurement and Instruments, ICEMI 2023

作者： Wei, Yangbin Li, Hao Cao, Jiawei Luo, Guangkun Li, Xuyang Wang, Zhigang School of Automation Engineering University of Electronic Science and Technology of China Chengdu China

ISBN: (纸本)9798350327144

To address the spectrum aliasing caused by the non-uniform and non-stationary characteristics of rotating machinery vibration signals in the field of dynamic signal analysis, this paper proposes a time-domain stretching based order analysis algorithm. this algorithm stretches the vibration signal in the time domain, which facilitates the frequency domain compression caused by the signal stretching in the time domain to reduce the frequency domain aliasing caused by the spectrum broadening caused by the characteristics of the vibration signal. At the same time, in order to deal with the unequal interval sampling caused by the signal stretching in time domain, this paper integrates the resampling principle of cubic spline interpolation into the algorithm, which improves the accuracy of order analysis. In addition, the implementation of this algorithm in field programmable Gate Array (FPGA) is described in detail. At the same time, this paper also uses simulation experiments to test each module inside the algorithm, and analyzes the accuracy of important steps such as cubic spline interpolation, which verifies the feasibility of the actual system. © 2023 IEEE.

关键词： Frequency domain analysis

来源：评论

学校读者我要写书评

暂无评论

Architecture and Design Choices for an AI-enabled FPGA-based Cosmic Radiation Sensor 16

Architecture and Design Choices for an AI-enabled FPGA-based...

引用

16th international Symposium on Electronics and Telecommunications, ISETC 2024

作者： Popa, Stefan Kazak, Artur Dinu, Alexandru Ivanovici, Mihai Secrieru, Nicolae Carbune, Viorel Melnic, Vladimir Transilvania University of Brasov Electronics and Computers Dept. Brasov Romania Technical University of Moldova Center of Space Technologies Chisinau Moldova

ISBN: (纸本)9798350390865

field programmable Gate Array (FPGA) devices can be reconfigured after their manufacture to accelerate tasks such as Artificial Intelligence (AI) inference, provide lower response times and in some cases even lower power consumption compared to the software equivalent running on a modern microprocessor due to the capability of accessing their resources in parallel. Complex physics experiments and Space applications benefit greatly from FPGAs. We propose using a general-purpose, low-power, low-cost FPGA device in a nanosatellite as a cosmic radiation sensor. the AI-based hardware Cosmic Radiation Sensor (AICoRS) will be able to detect single event upsets (SEUs) and analyze the radiation patterns on the fly. the AICoRS system will be radiation tolerant to ensure correct operation in space conditions while acting as a SEU detector. We present the proposed architecture and the design choices we face, as well as a preliminary study of implementing the SEU detection element for evaluating the feasibility of using such a device for Space applications and for measuring cosmic radiation from the point of view of power consumption. © 2024 IEEE.

关键词： Space applications

来源：评论

学校读者我要写书评

暂无评论

Next-generation Digital Receiver Platforms for Cosmology/Radio Astronomy experiments 10

Next-generation Digital Receiver Platforms for Cosmology/Rad...

引用

10th IEEE international conference on Electronics, Computing and Communication Technologies (IEEE CONECCT)

作者： Srivani, K. S. Girish, B. S. Rao, Mayuri S. Singh, Saurabh Kamini, P. A. Madhavi, S. Keerthipriya, S. Dash, Adarsh Kumar Vishakha, S. P. Agrawal, Yash thiagaraj, Prabu Somashekar, R. Sethi, Shiv K. Shankar, Udaya N. Seetha, S. Raman Res Inst Elect Engn Grp Bengaluru India Raman Res Inst Astron & Astrophys Bengaluru India

ISBN: (纸本)9798350385939;9798350385922

Over the last decade, field-programmable Gate Array (FPGA) technology has made significant strides, notably with Advanced Micro Devices Inc. (AMD) pioneering Multi-processor Systems-on-Chip (MPSoC). the addition of RF-class analog technology has further advanced MPSoCs, resulting in Radio Frequency System-on-a-Chip (RFSoC). RFSoCs combine data converters with programmable logic, dedicated processors, and high-speed transceivers, making them ideal for large-N applications in radio astronomy/cosmology experiments. the Raman Research Institute has embarked upon building next-generation digital correlation spectrometers using RFSoC evaluation boards like AMD's ZCU111 and ZCU216, advancing towards a compact, custom-designed third generation RFSoC-based platform named "Cosmology and radio astronomy experiments with RFSoC Integrated Signal Processing" (CRISP). these technological advancements are pivotal for high precision cosmology experiments, detecting subtle signals from recombination and reionization epochs. the paper describes the digital correlation receivers based on evaluation platforms, signal processing firmware, and the architecture of CRISP leveraging Size, Weight, and Power (SWaP) attributes.

关键词： Correlation spectrometer FPGA RFSoC MPSoC signal processing Epoch Reionization Recombination programmable logic Processor

来源：评论

学校读者我要写书评

暂无评论

A Digital Oscilloscope Based Hardware Implementation Approach for Universal Memristor Emulators 16

A Digital Oscilloscope Based Hardware Implementation Approac...

引用

16th IEEE international conference on Electronic Measurement and Instruments, ICEMI 2023

作者： Xu, Bo Zhao, Jia Chen, Kai Wang, Yifan Yan, Yanjun Bai, Libing School of Automation Engineering University of Electronic Science and Technology of China Chengdu China School of Big Health & Intelligent Engineering Chengdu Medical College of China Chengdu China

ISBN: (纸本)9798350327144

Prior to nanoscale memristors are commercially viable, accurately verifying the characteristics of memristors in hardware is one of the effective approaches to rapidly expanding their engineering by applications. Nevertheless, the commonly used equivalent circuit based on commercial devices has issues: large errors, inefficiency, and compatibility. this paper proposes a general digital model for memristors based on Taylor expansion and introduces a polynomial order determination method. Numerical simulations confirm that the proposed model exhibits three typical characteristics of memristors. Afterwards, a reconfigurable memristor simulator is developed based on FPGA. Finally, the simulator is embedded in a digital oscilloscope, and an interface is designed to display the hysteresis loop of the memristor. In addition, by online modification of the polynomial coefficients, the existing memristors can be simulated in the designed platform and the phase trajectory can be displayed with high accuracy. © 2023 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共213页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：