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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

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Ric fast adder and its set-tolerant implementation in FPGAS

Ric fast adder and its set-tolerant implementation in FPGAS

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17th international conference on field programmable logic and applications

作者： Mesquita, Eduardo Franck, Helen Agostini, Luciano Guentzel, Jose Luis Univ Fed Pelotas Dept Informat GACI Pelotas RS Brazil

ISBN: (纸本)9781424410590

FPGA is currently a very important design technology to implement electronic systems due to its high logic density, its fast time-to-market and its low cost. But in order to provide high logic density FPGA devices are fabricated with nanometer CMOS technology that is becoming susceptible to radiation-induced soft errors. Among these errors, single-event transients (SETs) are those that are induced in the user's programmable logic. this paper presents a new fast adder, called RIC (Re-computing the Inverse Carry-in) and shows how this new adder architecture may be used to build SET-tolerant fast adders. Results considering FPGA-based implementation are presented.

关键词： field programmable gate arrays (FPGA)

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In-field Vulnerability Analysis of Hardware-Accelerated Computer Vision applications 25

In-Field Vulnerability Analysis of Hardware-Accelerated Comp...

引用

25th international conference on field programmable logic and applications

作者： Chadjiminas, I. Kyrkou, C. theocharides, T. Michael, M. K. Ttofis, C. Univ Cyprus KIOS Res Ctr Intelligent Syst & Networks Dept Elect & Comp Engn Nicosia Cyprus ACC Innovat Ltd Nicosia Cyprus

ISBN: (纸本)9781467381239

In this paper, we propose an FPGA-based emulation framework that can provide dynamic vulnerability analysis for hardware-accelerated computer vision applications. the framework can be integrated alongside the targeted application, to allow for run-time, in-field, dynamically adjusted vulnerability analysis in real-world conditions, taking into consideration the non-deterministic parameters of the computer vision algorithm computations. We evaluate the proposed framework in real-time using an FPGA platform, for an obstacle avoidance (OA) computer vision application and its disparity estimation kernel to study the impact of Single-Event Upsets (SEUs).

关键词： Approximate Computing FPGA Single Event Upsets Intermittent Faults Transient Faults Computer Vision Reliability and Vulnerability Analysis

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Hardware/software process migration and RTL simulation

Hardware/software process migration and RTL simulation

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17th international conference on field programmable logic and applications

作者： Blumer, Aric D. Patterson, Cameron D. Virginia Polytech Inst & State Univ Bradley Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)9781424410590

this paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of field programmable Gate Arrays (FPGAs). the feasibility of such a system is demonstrated using existing FPGAs by accelerating a cycle-based simulation of a Register Transfer Level (RTL) design description. through the use of a common instruction set, each simulation process may be run in a software Virtual Machine (VM) or in a hardware Real Machine (RM). the implementation provides data for an empirical model used to examine the behavior of unimplemented parts of the system.

关键词： field programmable gate arrays (FPGA)

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DPA RESISTANCE FOR LIGHT-WEIGHT IMPLEMENTATIONS OF CRYPTOGRAPHIC ALGORIthMS ON FPGAS

DPA RESISTANCE FOR LIGHT-WEIGHT IMPLEMENTATIONS OF CRYPTOGRA...

引用

19th international conference on field programmable logic and applications

作者： Velegalati, Rajesh Kaps, Jens-Peter George Mason Univ Volgenau Sch IT&E Fairfax VA 22030 USA

ISBN: (纸本)9781424438914

Recent advances in field programmable Gate Array (FPGA) technology are bound to make FPGAs a popular platform for battery powered devices. Many applications of such devices are mission critical and require the use of cryptographic algorithms to provide the desired security. However, Differential Power Analysis (DPA) attacks pose a sever threat against otherwise secure cryptographic implementations. Current techniques to defend against DPA attacks such as Dynamic Differential logic (DDL) lead to an increase in area consumption of factor five or more. In this paper we show that moderate security against DPA attacks can be achieved for FPGAs using DDL resulting in an area increase of not much more than a factor two over standard FPGA implementations. Our design flow requires only FPGA design tools and some scripts.

关键词： field programmable gate arrays (FPGA)

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Network Intrusion Detection Using Neural Networks on FPGA SoCs 29

Network Intrusion Detection Using Neural Networks on FPGA So...

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29th international conference on field-programmable logic and applications (FPL)

作者： Ioannou, Lenos Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9781728148847

Network security is increasing in importance as systems become more interconnected. Much research has been conducted on large appliances for network security, but these do not scale well to lightweight systems such as those used in the Internet of things (IoT). Meanwhile, the low power processors used in IoT devices do not have the required performance for detailed packet analysis. We present an approach for network intrusion detection using neural networks, implemented on FPGA SoC devices that can achieve the required performance on embedded systems. the design is flexible, allowing model updates in order to adapt to emerging attacks.

关键词： Artificial neural networks Feature extraction Security Training field programmable gate arrays Internet of things

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Find the Real Speed Limit: FPGA CAD for Chip-Specific Application Delay Measurement 27

Find the Real Speed Limit: FPGA CAD for Chip-Specific Applic...

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27th international conference on field programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Zhao, Shuze Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9789090304281

Process variation is increasing with each successive technology node, and it has reached the point where the worst-case timing modelling employed by current FPGA CAD tools is significantly underutilizing the available silicon. Previous studies have proposed exploiting FPGA reconfigurability to reduce this underutilization using techniques such as late binding and dynamic voltage scaling. Most of the proposed solutions require the ability to measure the target application's delay on each configured chip. To accurately measure the delay of an application on a certain chip, we must measure the delay of its speed limiting paths on this specific chip. In this paper, we present a variation-aware CAD tool that automatically generates calibration bitstreams to measure the delay of any input application. Our tool identifies the statistically critical paths of the circuit and optimally selects which paths to test such that it minimizes the chances of reporting an optimistic delay, under a constraint on the number of allowed calibration bitstreams. Experimental results across a suite of benchmarks show that with one calibration bitstream we achieve 16x lower probability of reporting an optimistic delay compared to a greedy approach. With three calibration bitstreams, we reduce the probability of optimism to two chips in a million, approximately 6,000x lower than a greedy approach.

关键词： Delays Table lookup Calibration Semiconductor device measurement Integrated circuit modeling Computational modeling field programmable gate arrays

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Placement Strategies for 2.5D FPGA Fabric Architectures 28

Placement Strategies for 2.5D FPGA Fabric Architectures

引用

28th international conference on field programmable logic and applications (FPL)

作者： Ravishankar, Chirag Gaitonde, Dinesh Bauer, Trevor Xilinx Inc 3100 Logic Dr Longmont CO 80503 USA Xilinx Inc 2100 Logic Dr San Jose CA USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs take advantage of 2.5D stacking technology to manufacture large capacity and high performance heterogenous devices at reasonable costs. EDA tools need to be aware of and exploit physical characteristics of such devices, for example the reduced connection count between SLRs, the infrequency of SLL channel occurence in the fabric, and the aspect ratios of individual SLRs. We implement a partition driven placer to explore various EDA options to take advantage of architectural features in 2.5D FPGAs. We improve the routability of designs by optimizing the placer for discrete SLL channels and reduced connection counts. We propose a cut schedule for the partitioner to orient the placement with awareness of the aspect ratio of SLRs to improve track demands within each SLR.

关键词： field programmable gate arrays Routing Stacking Wires Fabrics Complexity theory Heating systems

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A Self-Calibrating True Random Number Generator 29

A Self-Calibrating True Random Number Generator

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29th international conference on field-programmable logic and applications (FPL)

作者： Peetermans, Adriaan Grujic, Milos Rozic, Vladimir Verbauwhede, Ingrid Katholieke Univ Leuven Imec COSIC Kasteelpk Arenberg 10 B-3001 Leuven Belgium

ISBN: (纸本)9781728148847

True Random Number Generators (TRNGs) are essential in all security systems. Unfortunately, large design effort is required to ensure that a TRNG design on a fieldprogrammable Gate Array (FPGA) generates a sufficient entropy density at its output. this design effort relates to the fact that for each FPGA family a manual placement and routing procedure has to be executed. On top of this often comes the additional effort of finding a suitable location inside the target FPGA. this searching procedure has to be repeated for every device separately. In this demo, we show the working of a novel entropy source for the Coherent Sampling Ring Oscillator (COSO) based TRNG. this entropy source eliminates the need for any manual intervention during the implementation process. It generates two oscillating signals that can be matched with a precision of a few picoseconds. A controller regulates this entropy source based on some predefined bounds on the period length difference of the two oscillating signals.

关键词： field programmable gate arrays Generators Entropy Graphical user interfaces Monitoring Manuals Ring oscillators

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Hybrid FPGA debug approach 25

Hybrid FPGA debug approach

引用

25th international conference on field programmable logic and applications

作者： Panjkov, Zdravko Wasserbauer, Andreas Ostermann, Timm Hagelauer, Richard Intel Mobile Commun Danube Mobile Commun Engn Linz Austria Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria

ISBN: (纸本)9781467381239

In the modern verification environment an FPGA-based prototyping has become an important part of the whole verification flow. the ability to simulate real time application in more realistic speeds allows much higher coverage than traditional HDL logic simulators. the main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently there are two traditional solutions for this problem. the first solution is using embedded trace-buffers to record a subset of internal signals and the second solution captures a snapshot of the current FPGA state. Both of these techniques have certain benefits and shortcomings. In this paper, we present an idea of merging these two techniques into a new hybrid approach. Using this idea we created a hybrid circuit and during our experiments showed that it preserves all good sides from both traditional approaches.

关键词： Hybrid Circuit Device Component field programmable gate arrays debugger Snapshots PROBLEM SOLUTION international Data Encryption Algorithm real-time application program PROTOTYPE

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INCREASING STABILITY AND DISTINGUISHABILITY OF thE DIGITAL FINGERPRINT IN FPGAS thROUGH INPUT WORD ANALYSIS

INCREASING STABILITY AND DISTINGUISHABILITY OF THE DIGITAL F...

引用

19th international conference on field programmable logic and applications

作者： Patel, Hiren Kim, Yong McDonald, J. Todd Starman, LaVern USAF AF Res Lab 1940 Allbrook Dr Wright Patterson AFB OH 45433 USA Air Force Inst Technol Wright Patterson AFB OH 45433 USA

ISBN: (纸本)9781424438914

field programmable Gate Arrays (FPGAs) have become increasingly popular in circuit development due to their rapid development times and low costs. With their increased use, the need to protect their Intellectual Property (IP) becomes more urgent. the digital fingerprint accomplishes this by creating a unique identification (ID) for each FPGA. In this research, we propose methods to dramatically increase the stability and robustness of the digital fingerprint ID by the proper choice of input sequences. We also show that by properly choosing the input word, we can significantly increase the DF resistance to operating temperature changes.

关键词： field programmable gate arrays (FPGA)

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