It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. this paper presents a dynamic router for Xilinx FPGAs, des...
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ISBN:
(纸本)9781424419609
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. this paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinx's XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed withthe router and compared withthe Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.
this work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA impl...
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ISBN:
(纸本)9781424419609
this work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA implementation. the programmable aspect of the processor follows the ASIP (Application Specific Instruction set Processor) approach with a instruction set targeted to accelerating block matching motion estimation algorithms. Configurability relates to the ability to optimize the microarchitecture for the selected algorithm and performance requirements through varying the number and type of execution units at compile time.
the poor scalability of current mesh-based FPGA interconnection networks is impeding our attempts to build next-generation FPGA of larger logic capacity. A few alternative interconnection network architectures have be...
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ISBN:
(纸本)9781424419609
the poor scalability of current mesh-based FPGA interconnection networks is impeding our attempts to build next-generation FPGA of larger logic capacity. A few alternative interconnection network architectures have been proposed for future FPGAs, but they still have several design challenges that need to be addressed. In this paper we propose sFPGA, a scalable FPGA architecture, which is a hybrid between hierarchical interconnection and Network-on-Chip. the logic resources in sFPGA are organized into an array Of logic tiles. the tiles are connected by a hierarchical network of switches, which route data packets over the network. In addition, we have proposed a design flow for sFPGA which integrates current design flows seamlessly. By doing a case study in our emulation prototype, we have validated our sFPGA design flow.
Stream join is a fundamental and computationally expensive data mining operation for relating information from different data streams. this paper presents two FPGA-based architectures that accelerate stream join proce...
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ISBN:
(纸本)9789090304281
Stream join is a fundamental and computationally expensive data mining operation for relating information from different data streams. this paper presents two FPGA-based architectures that accelerate stream join processing. the proposed hardware-based systems were implemented on a multi-FPGA hybrid system with high memory bandwidth. the experimental evaluation shows that our proposed systems can outperform a software-based solution that runs on a high-end, 48-core multiprocessor platform by at least one order of magnitude. In addition, the proposed solutions outperform any other previously proposed hardware-based or software-based solutions for stream join processing. Finally, our proposed hardware-based architectures can be used as generic templates to map stream processing algorithms on reconfigurable logic, taking into consideration real-world challenges and restrictions.
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and was designed to emulate a distributed-...
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ISBN:
(纸本)9781424410590
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and was designed to emulate a distributed-memory message-passing architecture. the system consists of 7681008 MicroBlaze cores in 64-84 Virtex-II Pro 70 FPGAs on 16-21 BEE2 boards, surpassing the milestone of 1000 cores in a standard 42U rack. An architecture based on point-to-point channels and switches using a combination of custom and generic hardware provides the functionality. Virtual-cut-through dimensional routing on one of two hybrid topologies with virtual channels provides the connectivity. A control network with a tree topology provides management and debugging capabilities. A software infrastructure consisting of GCC, uClinux and UPC allows running off-the-shelf applications and scientific benchmarks. Initial performance is encouraging for emulation purposes. In this paper we report on the design and implementation of RAMP Blue and discuss our experiences and lessons learned.
We present an efficient FPGA architecture suitable for a medical 3D ultrasound beamformer. We tackle the delay calculation bottleneck, which is the heart and the most critical part of the beamformer, by proposing a co...
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ISBN:
(纸本)9782839918442
We present an efficient FPGA architecture suitable for a medical 3D ultrasound beamformer. We tackle the delay calculation bottleneck, which is the heart and the most critical part of the beamformer, by proposing a computationally efficient design that is able to perform volumetric real-time beamforming on a single-chip FPGA. the design has been demonstrated for a 32 x 32-channel receive probe, and we extrapolated the requirements of the architecture for 80 x 80 channels.
this paper presents a novel class of division algorithm that reduces the delay of calculus introducing more concurrency in computation. the algorithm is suitable for fixed-point operands and divides in a radix r = 2(k...
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ISBN:
(纸本)9781424438914
this paper presents a novel class of division algorithm that reduces the delay of calculus introducing more concurrency in computation. the algorithm is suitable for fixed-point operands and divides in a radix r = 2(k), producing k bits at each iteration. the proposed digit recurrence algorithm has two different architectures, a first one for general hardware implementation, and the second one optimized for configurable logic. Results show a speedup greater to three times respect to a classical non-restoring division implemented in Xilinx Devices. the dividers were also compared against Xilinx CoreGenerator circuits clearly outperforming latency and area
Reconfiaurable logic Devices are classified as the fine-grained or coarse-rained type on the basis of their basic logic cell architecture. In general, each architecture has its own merit;therefore, it is difficult to ...
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ISBN:
(纸本)9781424410590
Reconfiaurable logic Devices are classified as the fine-grained or coarse-rained type on the basis of their basic logic cell architecture. In general, each architecture has its own merit;therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In this paper, we propose a Variable Grain logic Cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and also develop technology mapping tool. Its key feature is the variable granularity being a trade-off between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. As a result, critical path delay, and number of configuration memory bits are reduced by 49.7%, and 48.5%, respectively, in the benchmark circuits.
this paper presents a comparison between two technologies for reconfigurable circuits: FPGA's and FPAA's. the comparison is based on a case study of the area of industrial control using simulations with both t...
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ISBN:
(纸本)9781424438914
this paper presents a comparison between two technologies for reconfigurable circuits: FPGA's and FPAA's. the comparison is based on a case study of the area of industrial control using simulations with both types of reconfigurable devices. Several design issues are discussed, including the ease of implementation, accuracy, capacity, consumption and size, among others. Based on the case study, we present qualitative directions to choose the most suitable reconfigurable device for similar applications.
Random number generators play an important role in the field of cryptography and security. It is often required that a random number generator consists of digital logic blocks only, so that it can be implemented on re...
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ISBN:
(纸本)9781424438914
Random number generators play an important role in the field of cryptography and security. It is often required that a random number generator consists of digital logic blocks only, so that it can be implemented on reconfigurable platforms. Since randomness cannot be proved by statistical tests there is a need for a provably secure hardware random number generator. In order to provide a proof of security, an experimental investigation of various physical effects on reconfigurable platforms is needed. In this paper we focus on the effect of narrow transitions suppression in the logic gates. the estimation of this effect may be crucial for the validity of the security proof of a RNG design. We explain our views on how experiments on FPGA should be performed and we give description of the measurement setup. We show that up to 98% of the transitions are suppressed in our experimental FPGA setup.
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