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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

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High Speed and Low Power DSP Architectures for Barker-13 Radar Pulse Compressor

High Speed and Low Power DSP Architectures for Barker-13 Rad...

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IEEE India conference (INDICON)

作者： K A Anoopkumar Bethi Pardhasaradhi G S Vandana Raja Rajeswari Pathipati Srihari Qualcomm India Private Limited New Delhi India ADAS Dept. Continental Automotive Components (India) Pvt Ltd Bangalore India Sri Shasha Prayathi Technologies Pvt. Ltd. Mangalore India ECE Dept. GVP College of Engineering for Women Vishakapatnam India ECE Dept. National Institute of Technology Surathkal Karnataka India

ISBN: (纸本)9781665452724

this paper proposes two novel efficient DSP architectures for the Barker-13 sequence for radar coded waveform design. Firstly, the traditional pulse compressor architectures are modified by using unfolded DSP techniques to achieve higher sampling rates for high-speed applications. Secondly, the reduction in hardware utilization and power consumption are addressed by the folding technique. Further, the proposed architectures are implemented on Artex-7 field programmable Gate Arrays (FPGA). the hardware implementation results demonstrates that the unfolded pulse compressor increased the speed by 3.25 times compared to traditional broadcasting filter realization. On the other hand, the folded architecture reduced the power usage by 15.2% in comparison to broadcast architecture. these pulse compressors can be deployed for high speed and low power radar/sonar applications.

关键词： Power demand Receivers logic gates Broadcasting Hardware Radar applications field programmable gate arrays

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Computation Offloading at field Level: Motivation and Break-Even Point Calculation 26

Computation Offloading at Field Level: Motivation and Break-...

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26th IEEE international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Gundall, Michael Huber, Christopher Schotten, Hans D. German Res Ctr Artificial Intelligence GmbH DFKI Kaiserslautern Germany Tech Univ Kaiserslautern Dept Elect & Comp Engn Kaiserslautern Germany

ISBN: (纸本)9781728129891

Smart manufacturing has the objective of creating highly flexible and resource optimized industrial plants. Furthermore, the improvement of product quality is another important target. these requirements implicate more complex control algorithms. Processing these algorithms may exceed the capabilities of resource constrained devices, such as programmable logic controllers (PLCs). In this case, the necessity for computation offloading is given. Due to the fact that industrial plants are currently designed for a life-cycle-time of more than ten years, in a realistic smart manufacturing scenario, these devices have to be considered. therefore, we investigate the impact of complex algorithms on conventional PLCs by simulating them with a load generator. In addition, we propose a realistic factory scenario including benchmarks for both wireline and wireless communication systems. thus, their round-trip time (RTT) is measured with and without additional load on the network. With the help of these investigations, break-even points for the application of computation offloading of two typical PLCs of Siemens S7 series can be calculated.

关键词： Computation offloading PLC smart manufacturing Industry 4.0 industrial communication wireless communications cloud computing

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the Development of Structured Tele Based Medicine Concept Using programmable System

The Development of Structured Tele Based Medicine Concept Us...

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Advance Computing and Innovative Technologies in Engineering (ICACITE), international conference on

作者： Myasar Mundher Adnan Rajesh Pant Yadaiah Nirsanametla Tabeen Fatima Dr Magesh Kumar Neelam Sanjeev Kumar The Islamic university Najaf Iraq Uttaranchal Institute of Management Uttaranchal University Uttarakhand India Centre of Research Impact and Outreach Chitkara University Rajpura Punjab India Department of CSE CMR Technical Campus Hyderabad Telangana India School of Business and Management Christ University Bangalore Department of Computer Science & Engineering SRM Institute of Science & Technology Vadapalani Chennai

ISBN: (数字)9798350360165

ISBN: (纸本)9798350360172

In the medical field, clinics and hospitals frequently use dispersed applications like telediagnosis. these apps must nevertheless provide information security in order to properly transit security measures like firewalls and proxies. the User Datagram Protocol (UDP) is often recommended for videoconferencing applications because of its low latency; nevertheless, security problems occur when UDP tries to pass through firewalls and proxies without a specified set of fixed ports. In order to overcome these obstacles, this study presents a revolutionary platform that uses Transmission Control Protocol (TCP) rather of UDP: VAGABOND, which stands for “Video Adaptation framework, across security gateways, based on transcription,” Adaptation Proxies (APs) that are designed to accommodate user preferences, device variations, and dynamic changes in network capacity comprise VAGABOND. this platform’s versatility at the user and network levels guarantees seamless operation in a range of scenarios. VAGABOND uses a binomial probability distribution to start making adaptation decisions. this distribution is formed from the retention of video packets inside a certain time period. VAGABOND gets beyond firewall and proxy constraints by using ordinary TCP ports (like 80 or 443) to provide videoconferencing data via TCP. But even though TCP is a dependable transport protocol, it can occasionally have latency and socket timeout problems. VAGABOND has clever adaptation techniques to deal with these problems and ensure smooth data transfer.

关键词： TCP Transport protocols Firewalls (computing) Telemedicine Sockets Information security logic gates

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Design of Restricted Coulomb Energy Neural Network Processor for Multi-modal Sensor Fusion 11th

Design of Restricted Coulomb Energy Neural Network Processor...

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11th international conference on Computer Science and its applications, CSA 2019 and 14th KIPS international conference on Ubiquitous Information Technologies and applications, CUTE 2019

作者： Cho, Jaechan Kim, Minwoo Jung, Yongchul Jung, Yunho School of Electronics and Information Engineering Korea Aerospace University Goyang-si Korea Republic of

ISBN: (纸本)9789811593420

this paper proposes a restricted coulomb energy neural network (RCE-NN) with an improved learning algorithm and presents the hardware architecture design and FPGA implementation results. the proposed learning algorithm divides each neuron region in the learning process and measures the reliability with different factors for each region. In addition, it applies a process of gradual radius reduction by a pre-defined reduction rate. In performance evaluations using two datasets, RCE-NN with the proposed learning algorithm showed high recognition accuracy with fewer neurons compared to existing RCE-NNs. the proposed RCE-NN processor was implemented in an Intel-Altera Cyclone IV FPGA with 26,702 logic elements, 13,096 registers and 131,072bits memory and operated at the clock frequency of 150 MHz. © 2021, Springer Nature Singapore Pte Ltd.

关键词： field programmable gate arrays (FPGA)

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Implementation of Real-Time Object Detection on FPGA

Implementation of Real-Time Object Detection on FPGA

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international conference on Trends in Electronics and Informatics (ICEI)

作者： Gayatri Rathod Parin Shah Ruchi Gajjar Manish I. Patel Nagendra Gajjar Electronics and Communication Engineering Department Institute of Technology Nirma University Ahmedabad Gujarat India

Object detection is a common and challenging problem in today's world. Also due to the rapid development of deep learning employing underlying deep models over the past ten years, many researchers have investigated and contributed to improving the performance of object identification and associated tasks such as object classification, localization, and segmentation. Inference time and detection accuracy are used to rate the effectiveness of any object detector. In terms of detection accuracy, it is observed that the two-stage detectors outperform the single-stage detector however, single-stage detectors outperform their rivals in terms of inference time. Additionally, You Only Look Once (YOLO) and its versions have improved detection accuracy, some-times surpassing two-stage detectors. In this study, we performed a co-design methodology for hardware and software (HW/SW) aimed at Central Processing Unit (CPU) + field programmable Gate Array (FPGA) based heterogeneous platform which is Xilinx FPGA Kria KV260. A CNN-based algorithm is first extended to the YOLOv4, v5L, and v5s framework before being implemented on the Kria KV260, an out-of-the-box platform for developing advanced vision applications. A reduced computation time is observed for the deployment of the Machine Learning model on Kria KV260.

关键词： Software algorithms Detectors Object detection logic gates Real-time systems Software Central Processing Unit

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Model Checking for an HDLC IP Core Transparency Error in an Aerospace Industrial Context 21

Model Checking for an HDLC IP Core Transparency Error in an ...

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4th international conference on Computer Science and Software Engineering, CSSE 2021

作者： Liu, Shiyu Li, Dongfang Xue, Jixing Yang, Guang Shen, W.E.I. Wang, Zhihao Beijing Institute of Computer Technology and Applications China

ISBN: (纸本)9781450390675

In recent years, the use of field-specific and customizable FPGA devices in the aerospace industry has become a standard practice because FPGA devices offer new trade-offs between flexibility, energy, and performance compared with general-purpose processors. the development of FPGA devices relying on IP core reuse technology has become the norm. IP cores that are reused are often regarded as safer, which makes the verification team neglect to verify. But in fact, limited by the level of verification technology during development, IP cores that have been reused for a long time may have some boundary errors that are difficult to find in simulation testing. In this article, we apply the model check to a commercial HDLC controller, which has been repeatedly used for nearly ten years on multiple spacecraft undertaking research by related aerospace industry departments. the model check found a logic error in the sending function of the IP core, and analyzed the timing path that triggered the error. this work demonstrates the efficiency of model checking in dealing with such boundary case errors. © 2021 ACM.

关键词： field programmable gate arrays (FPGA)

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SD Card Interface Using FPGA for Multimedia applications

SD Card Interface Using FPGA for Multimedia Applications

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international conference of Electronics, Communication and Aerospace Technology (ICECA)

作者： Srigitha S Nath S Navaneethan M S Sakthekannan M Udaya Krishnan B M Yogavignes Department of Electronics and Communication Engineering Saveetha Engineering College Chennai India

ISBN: (纸本)9781665482721

field programmable Gate Array (FPGA) is an application that is based on chips that can process audio, video, and image. For FPGA systems, onboard memory may be used; however, it cannot be readily expanded by putting in extra cards. Since microcontrollers can read and write Secure Digital (SD) cards, they are more useful. the primary goal is to develop a low-cost, non-volatile, flash-memory, detachable, portable, and user-friendly storage solution for field programmable Gate Array (FPGA) that can store vast quantities of data. Verilog enables complete access to the SD card's contents, eliminating the need for a microcontroller or general-purpose CPU on-chip. In this work, Spartan 6 and Artix-7 FPGA are utilized. For this, the proposed study utilizes a Strontium 4GB micro SDHC (class 6) card. the SD card stores files in the FAT32 format. the objective is to extract a BMP image file from an SD card. the proposed design has achieved the hardware resources in 916 look-up tables (LUT) and 464 flip-flops.

关键词： Strontium Protocols Microcontrollers Nonvolatile memory logic gates Hardware Table lookup

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Exploring Memory Access Techniques for Efficient FPGA based 3D CNN Accelerator Design

Exploring Memory Access Techniques for Efficient FPGA based ...

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IEEE international conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Fatima Hameed Khan Muhammad Adeel Pasha Shahid Masud Department of Electrical Engineering Lahore University of Management Sciences (LUMS) Lahore Pakistan

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Recent advancements in 3D Convolutional Neural Network (CNN) architectures have demonstrated superior performance across diverse computer vision tasks, albeit with a trade-off of intense computational and memory demands. thus, the tiling of incoming data becomes mandatory for 3D CNN acceleration in memory-constrained platforms such as field programmable Gate Arrays (FPGA). In this paper, different memory access techniques are explored to reduce the data traffic between on-chip and off-chip memories during the inference stage of a 3D CNN. the most suitable data traffic mode is identified by considering multiple parameters like latency, on-chip memory utilization and off-chip memory access. A parameterized and modular design approach for 3D CNNs has been implemented on an FPGA, where the input and weight data mapping modules are designed to minimize the on-chip memory requirements. these modules are parameterized for variable tiling sizes and different memory access modes while the main computation is performed on a systolic-array-based pipelined architecture. the experiments conducted on three widely adopted 3D networks, I3D, C3D, and R(2+1)D, have shown 16%, 28%, and 10% improvement in latency respectively. the proposed methodology also results in a lower energy dissipation profile.

关键词： three-dimensional displays Memory management Random access memory Parallel processing logic gates Hardware System-on-chip

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Text Classification for Embedded FPGA Devices using Character-Level CNN 7

Text Classification for Embedded FPGA Devices using Characte...

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7th international conference on Advanced Computing and Communication Systems, ICACCS 2021

作者： Saxena, Srijan Kumari, Sucheta Kumar, Sudhanshu Singh, Sonal Delhi Technological University Electronics and Communication Engineering New Delhi India

ISBN: (纸本)9781665405201

In the past few years, tremendous growth has been observed in the Internet of things (IoT) and mobile technologies. At the same time, deep learning technologies have also grown significantly. thus, it is essential to investigate the hardware acceleration and deployment of deep learning algorithms on edge devices. Two types of deep neural networks RNN and CNN are widely used for NLP (Natural Language Processing). Recent exploration of CNN based methods for NLP has proven that they are fast and effective. In this paper, we discuss multi-class text classification using 1D Temporal convolutional neural networks. We have explored the acceleration and deployment of our model on the Xilinx PYNQ (Python Productivity for ZYNQ) FPGA board. In this paper, we explored the features of character-level text classification which proves to be a perfect fit for edge applications owing to adaptivity to misspelled, infrequent words or informal text, lightweight models, and low latency. We have accelerated our text classification model using coarse pruning and quantization. the deployment exploits the strong relationship of a sequential processor with a PL (programmable logic) as an accelerator, to implement power efficient and low latency inference machine learning architecture. the model is evaluated on a dataset of reviews for several brands. A method of evaluation robustness of text classifications model, for informal language and misspellings, is also proposed. Compared to GPU, after proposed hardware acceleration a 50% drop in latency and a 1500% decrease in power has been observed on an FPGA. © 2021 IEEE.

关键词： field programmable gate arrays (FPGA)

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SpaceFibre IP Cores for the Next Generation of Radiation-Tolerant FPGAs 9

SpaceFibre IP Cores for the Next Generation of Radiation-Tol...

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9th international SpaceWire and SpaceFibre conference, ISC 2022

作者： Villafranca, Alberto Gonzalez Florit, Albert Ferrer Casas, Marti Farras Parkes, Steve STAR-Barcelona SL Sant Cugat Del Valles Barcelona Spain STAR-Dundee Dundee United Kingdom

ISBN: (纸本)9780995453029

SpaceFibre (ECSS-E-ST-50-11C) is a very high-performance, high-reliability and high-availability network technology specifically designed to meet the needs of space applications. It provides point-to-point and networked interconnections at Gigabit rates with Quality of Service (QoS) and Fault Detection, Isolation and Recovery (FDIR). SpaceFibre has been designed as a replacement of SpaceWire (ECSS-E-ST-50-12C)-it is backwards compatible with SpaceWire at the packet level-for next-generation space missions where very high throughput is required, providing up to 6.25 Gbit/s per lane, with multi-lane allowing to reach up to 16 times the speed of a single lane. NORBY and OPS-SAT technology demonstrators have already flown SpaceFibre, with more missions in both Europe and the USA currently designing or planning to use SpaceFibre. STAR-Dundee has developed a complete family of SpaceFibre IP cores fully compliant with the SpaceFibre standard. this family is composed of four different IPs: Single-Lane Interface, Multi-Lane Interface, Single-Lane Routing Switch and Multi-Lane Routing Switch. A new generation of radiation-tolerant FPGAs is emerging to cope with the ever-growing processing power required by newer missions. Microchip has released the PolarFire RTPF500, Xilinx the Versal XQRVC1902, and NanoXplore the BRAVE NG-Ultra. SpaceFibre operation requires serial transceivers, which are already inbuilt in modern FPGAs. the IPs have been adapted to take advantage of the specific transceivers and memory blocks offered by these new FPGAs. In this work we analyse in detail the performance of STAR-Dundee SpaceFibre IP cores on this new generation of FPGAs considering several performance metrics, e.g. maximum lane speed, resource usage, etc. We also compare the performance of the IPs with current state-of-the-art space-grade FPGAs, i.e. Microchip RTG4 and Xilinx Kintex UltraScale XQRKU060. this analysis can also be used as a representative benchmark to compare the performances o

关键词： field programmable gate arrays (FPGA)

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