Traditional design techniques for FPGAs are based on using hardware description languages, with functional and post-place-and-route simulation as a means to check design correctness and remove detected errors. With la...
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ISBN:
(纸本)9781424419609
Traditional design techniques for FPGAs are based on using hardware description languages, with functional and post-place-and-route simulation as a means to check design correctness and remove detected errors. With large complexity of things to be designed it is necessary to introduce new design approaches that will increase the level of abstraction while maintaining the necessary efficiency of a computation performed in hardware that we are used to today. this paper presents one such methodology that builds upon existing research in multithreading, object composability and encapsulation, partial runtime reconfiguration, and self adaptation. the methodology is based on currently available FPGA design tools. the efficiency of the methodology is evaluated on basic vector and matrix operations.
Configuration scrubbing is a technique used for repairing Single Event Upsets (SEUs) within the configuration memory of an FPGA. Scrubbing approaches have been developed using hardware external to the FPGA communicati...
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ISBN:
(纸本)9782839918442
Configuration scrubbing is a technique used for repairing Single Event Upsets (SEUs) within the configuration memory of an FPGA. Scrubbing approaches have been developed using hardware external to the FPGA communicating through a configuration port and using hardware within the FPGA by communicating with an internal configuration port (ICAP). More recent FPGAs such as the Xilinx Zynq 7-Series SoCs provide internal programmable processors that can configure the FPGA logic very rapidly using an internal Processor Configuration Access Port (PCAP). these SoC/FPGAs also provide automatic internal scrubbing through the use of high-speed readback and configuration error correction. this paper presents a novel form of FPGA configuration scrubbing for the Zynq-7000 SoC family by combining the highspeed PCAP configuration port with internal scrubbing. this novel scrubber corrects single-bit upsets in several microseconds and detects these upsets in 8 ms.
Understanding how FPGAs age and how to control that aging is crucial for ensuring the reliability and security of FPGAs in critical applications. Due to the proprietary nature of commercial FPGAs, it can be challengin...
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ISBN:
(纸本)9798331530082;9798331530075
Understanding how FPGAs age and how to control that aging is crucial for ensuring the reliability and security of FPGAs in critical applications. Due to the proprietary nature of commercial FPGAs, it can be challenging to validate aging models on real silicon, and most previous work has relied on circuit simulations to study the effects of FPGA aging. In this work, we leverage low-level placement and routing APIs provided by RapidWright to create a series of stressor and characterization circuits that allow us to measure the effects of aging on individual LUTs and routing resources in a 28nm FPGA. We demonstrate how these techniques allow fine-grained control of the relative aging of different FPGA resources, even to the point of aging individual paths within a single LUT. Several different aging experiments are demonstrated, and in a cumulative test, we show how different signal and LUT configurations can influence the aging rate by over 2x.
FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an appr...
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ISBN:
(数字)9781538685174
ISBN:
(纸本)9781538685174
FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an approach to manage FPGA resources with OS functionality, this paper introduces the concept of resource elastic virtualization which allows shrinking and growing of accelerators in the spatial domain withthe help of partial reconfiguration. Withthis, we can serve multiple applications simultaneously on the same FPGA and optimize the resource utilization and consequently the overall system performance. We demonstrate how an implementation of resource elasticity can be realized for OpenCL accelerators along with how it can achieve 23x better FPGA utilization and 49% better performance on average while simultaneously lowering waiting time for tasks.
As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. the current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-...
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ISBN:
(纸本)9781424438914
As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. the current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. this paper proposes the use of a Secure Reconfigurable Controller (SeReCon) for accounting of IP core usage, e.g. total runtime, no. of activations etc, in a PR system. this paper extends the reported SeReCon root-of-trust to support license enforcement within the PR flow and to facilitate confidentiality of the IP core during the PR system life-cycle. A prototype IP-aware SeReCon demonstrator, implemented on Virtex-5 and supporting reconfiguration of a PCIe accelerator with cryptographic IP cores is described.
We describe the hardware platform that will be used to run several demonstrator applications within the EU-funded hArtes project. hArtes' main goal is to support, with appropriate tools, the development of complex...
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ISBN:
(纸本)9781424419609
We describe the hardware platform that will be used to run several demonstrator applications within the EU-funded hArtes project. hArtes' main goal is to support, with appropriate tools, the development of complex applications on heterogeneous and reconfigurable systems. Our platform provides a number of heterogeneous computing sub-systems, such as DSPs, general-purpose CPUs and configurable elements (in the shape of FPGAs). the envisaged applications are mainly in the audio realm, so support for high-quality audio I/O is also present. FPGAs play a dual role: i) they support I/O functions for audio streaming, moving audio signals from/to main memory with full hardware support;ii) tightly coupled to traditional processors, they make up the reconfigurable processing core within the system. this paper describes the architecture and the first implementation of the platform.
this paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA...
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ISBN:
(纸本)9781424410590
this paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. the architecture that has been derived and implemented operated at 12.8Gbps and is scalable up to 20Gbps.
Key-value stores (KVS) become critical in many applications because of the data explosion recently. there is a strong demand to improve the throughput and reduce the latency for KVS. FPGA-based parallel architecture c...
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ISBN:
(纸本)9782839918442
Key-value stores (KVS) become critical in many applications because of the data explosion recently. there is a strong demand to improve the throughput and reduce the latency for KVS. FPGA-based parallel architecture can bring excellent performance and power efficiency. Cuckoo hashing has proven to be an efficient approach to implement KVS with good memory utilization and constant worst case access time. In this paper, an FPGA-based KVS implementation is proposed based on Cuckoo hashing, with a decoupled storage to achieve 81.7% memory utilization, and a pipeline scheme to achieve high performance. the latency of insert, search and delete operations is only 40 ns. And the throughput for search and delete can be 200 million requests per second (MRPS) which is 5x faster than [1]. Even when the load factor becomes 0.9, the throughput for insert can still achieve 147 MRPS.
FPGA CAD tools require wirelength predictions to make informed decisions through clustering, placement and routing stages towards power, area or delay based design goals. Unfortunately, there has been minimal work dev...
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ISBN:
(纸本)9781424410590
FPGA CAD tools require wirelength predictions to make informed decisions through clustering, placement and routing stages towards power, area or delay based design goals. Unfortunately, there has been minimal work devoted to estimating individual wirelengths early in the CAD flow. Rent's rule can be used to generate a wirelength distribution but cannot be used to predict lengths of individual wires. Hence, this paper explores "structural metrics" that have been found to possess strong predictive qualities in the ASIC domain. To our knowledge this is a first study in the application of these metrics in the FPGA CAD flow. Results show that the studied metrics capture characteristics of placement optimization carried out by VPR, and hence, are good indicators of post-placement wirelengths.
Recently, there has been an increased focus on integration of reconfigurable fabric with modern processors. However, existing soft-processors are optimized to leverage older FPGA fabrics, focus primarily on resource m...
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ISBN:
(纸本)9789090304281
Recently, there has been an increased focus on integration of reconfigurable fabric with modern processors. However, existing soft-processors are optimized to leverage older FPGA fabrics, focus primarily on resource minimization and have fixed-pipeline designs that limit the scope for tightly integrated hardware accelerators. In this work, we present Taiga: a RISC-V, 32-bit, soft-processor architecture supporting the RISC-V Multiply/Divide and Atomic operations extensions (RV32IMA) designed to support Linux-based shared-memory systems. the processor design is highly configurable and features a standardized interface for functional units allowing for ease of integration of new functional units. Despite a more complex pipeline, our design uses approximately 33% fewer slices while clocking 39% faster than a LEON3 based system built on a Xilinx Zynq X7CZ020.
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