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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

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A field programmable Process-In-Memory Architecture Based on RRAM Technology 5

A Field Programmable Process-In-Memory Architecture Based on...

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5th international conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Liang, Yuan Yin, Longxiang Xu, Ning Wuhan Univ Technol Sch Comp Sci & Technol Wuhan Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Wuhan Univ Technol Sch Informat Engn Wuhan Peoples R China

ISBN: (纸本)9781665423144

Conventional reconfigurable architectures, e.g., field-programmable Gate Array (FPGA), are confronted with the inflexibility of the on-chip local memory architecture and the scarce memory resource, which result in the inflexibility to deal with the current memory-thirsty data-intensive applications. Emerging nonvolatile devices, such as resistive random-access memory (RRAM), can operate in a logic-in-memory way, i.e., they can act as both a nonvolatile memory element and a switch, and thus, have the potential to provide higher flexibility and data processing ability. We propose a field-programmable logic-in-memory architecture based on RRAM technology, which is a two-dimensional tile array, where each tile is an RRAM-based crossbar array and can be remolded into three basic modes including logic, interconnect and memory. We further develop a specific adaptive algorithm for placement and routing, which can well exploit the logic-in-memory architecture characteristics. Comparing with traditional FPGAs, our architecture shows 1.9x lower power consumption, 2.8x lower delay, and 5.6x higher performance.

关键词： RRAM logic-in-memory reconfigurable P&R

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Hardware Implementation of Pseudo-Random Numbers on CPLD

Hardware Implementation of Pseudo-Random Numbers on CPLD

引用

international conference on Electronics, Computer and Computation (ICECCO)

作者： Adil Maidanov Sabyrzhan Atanov Bibigul Tailak L. N. Gumilyov Eurasian National University Nur-Sultan Kazakhstan

ISBN: (纸本)9781665409469

the article proposes a hardware solution for generating pseudo-random numbers. the VHDL development environment was chosen as a platform for implementation of CPLDs, because this programming environment satisfies all technological advancements in integrated circuits, where you can easily create digital designs and transfer them to circuits manually or automatically. the main purpose of the work is to present algorithms with execution on CPLDs that will allow creating a fast, efficient and inexpensive pseudo-random number generator. the resulting configurable generator can be used in a wide range of applications where the use of various pseudo-random sequences is required, for example, in implementation built-in self-testing for digital devices. the flowchart and an example of generation are given

关键词： Integrated circuits Flowcharts VHDL programmable logic devices Built-in self-test Hardware Generators

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1200V Series-Connected GAN-IGBT Hybrid Switch with Single Gate Driver

1200V Series-Connected GAN-IGBT Hybrid Switch with Single Ga...

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international conference on Electrical and Electronics Engineering, ELECO

作者： Ömer Faruk GÖKSU Mehmet Onur GÜLBAHÇE Serkan DÜŞMEZ Elektrik-Elektronik Mühendisliği Fatih Sultan Mehmet Vakıf Üniversitesi Elektrik Mühendisliği İstanbul Teknik Üniversitesi Huawei Technologies Duesseldorf GmbH Nuremberg Research Center

ISBN: (数字)9798331518035

ISBN: (纸本)9798331518042

GaN FETs offer higher switching speeds and lower gate drive losses compared to IGBTs. their low parasitic capacitance allows for achieving higher switching frequencies. Due to the limited Vds voltage of GaN FETs, they must be connected in series for high-voltage power conversion applications, necessitating voltage balancing. this study proposes a gate driving scheme and circuitry to control an 800V / 16A hybrid switch using a single gate driver while balancing voltage across the series-connected GaN FETs. As a result of using the hybrid configuration, conduction loss on GaN FETs has been reduced by 70.7%, and the cost of the switching unit has decreased significantly, making it an alternative low-switching loss and high power switching unit.

关键词： Switching frequency field effect transistors Switches logic gates Gate drivers Hybrid power systems Power conversion Voltage control Switching circuits Parasitic capacitance

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Boosting DNN Efficiency: Replacing FC Layers with Graph Embeddings for Hardware Acceleration

Boosting DNN Efficiency: Replacing FC Layers with Graph Embe...

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Digital Signal Processing and its applications (DSPA), international conference on

作者： Vasiliy S. Usatyuk Sergey I. Egorov Department of Computer Science South-West State University Kursk Russia

ISBN: (数字)9798331518752

ISBN: (纸本)9798331518769

Fully connected (FC) layers present a significant bottleneck in the throughput of Convolutional Neural Networks (CNNs) and Transformers when deployed on hardware accelerators such as FPGAs, ASICs, and analog AI chips. this paper proposes a novel approach to mitigate this limitation by replacing FC layers with sparse graph embedding techniques derived from Low-Density Parity-Check (LDPC) codes, enabling robust weight compression. Using VGG16 as a case study, we demonstrate that our method reduces the parameters in the FC layers from 123,642,856 to just 64,000-a 1,931-fold reduction-while maintaining high-precision classification performance. Following aggressive pruning (72% weight reduction), our LDPC-based embeddings, combined with 8-bit fixed-point quantization, achieve an accuracy of 70.21%, compared to 70.89% achieved by unpruned float32. On the Xilinx Alveo U50 platform, this translates to processing up to 1119 images per second with parallel computation of 64-dimensional embeddings. Moreover, by replacing the top FC layers with the proposed graph embedding method and leveraging fast analog feature extraction (via supervised or random projections), our approach demonstrates the potential to achieve peak performance on the Alveo U50 of 4.8 million images per second for float32 100-class classification and 39.86 million images per second for 10-class classification using 16-bit fixed-point representation. these findings underscore the capability of graph embeddings to significantly enhance DNN efficiency on data center and resource-constrained edge AI hardware platforms. We hypothesize that exploiting the inherent sparsity of graph embeddings, combined with the energy efficiency of analog computation for feature extraction, can yield substantial reductions in CNN, Transformer and Diffusion DNN inference power consumption, potentially surpassing GPU efficiency by three to four orders of magnitude. this paper presents preliminary results and outlines directions for

关键词： Accuracy Digital signal processing Transformers Feature extraction throughput Parity check codes Energy efficiency Convolutional neural networks Hardware acceleration field programmable gate arrays

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Efficient Table-Based Polynomial on FPGA 39

Efficient Table-Based Polynomial on FPGA

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39th IEEE international conference on Computer Design ICCD)

作者： Barbone, Marco Kwaadgras, Bas W. Oelfke, Uwe Luk, Wayne Gaydadjiev, Georgi Imperial Coll London Dept Comp London England Univ Groningen Bernoulli Inst Groningen Netherlands Inst Canc Res Joint Dept Phys London England Royal Marsden NHS Fdn Trust London England Maxeler Technol London England

ISBN: (纸本)9781665432191

field programmable Gate Arrays (FPGAs) are gaining popularity in the context of scientific computing due to the recent advances of High-Level Synthesis (HLS) tool-chains for customised hardware implementations combined with the increase in computing capabilities of modern FPGAs. As a result, developers are able to implement more complex scientific workloads which often require the evaluation of univariate numerical functions. In this study, we propose a methodology for table-based polynomial interpolation aiming at producing area-efficient implementations of such functions on FPGAs achieving the same accuracy and at similar performance as direct implementations. We also provide a rigorous error analysis to guarantee the correctness of the results. Our methodology covers the forecast of resource utilisation of the polynomial interpolator and, based on the characteristics of the function, guides the developer to the most area-efficient FPGA implementation. Our experiments show that in the case of a radiation spectrum of a Black Body application based on evaluating Planck's Law, it is possible to reduce resource utilisation by up to 90% when compared to direct implementations not using table-based methods. Moreover, when only the kernels are considered, our method uses up to two orders of magnitude fewer resources with no performance penalties. Based on previous more theoretical works, our study investigates practical applications of table-based methods in the context of high performance and scientific computing where it is used to implement common but more complex functions than the elementary functions widely studied in the related literature.

关键词： Interpolation Scientific computing Error analysis conferences logic gates Hardware Resource management

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Design of Processor Interface logics on field programmable Gate Array for Spacecraft On-Board Computer

Design of Processor Interface Logics on Field Programmable G...

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conference on Modeling of Systems Circuits and Devices (MOS-AK India)

作者： R. Anuvindh Rodney Augustine Francis Sayooj S. Ujit Bej R. Santha Bharathi S. Kanithan ECE Dept. MVJ College of Engineering Bengaluru India Control and Digital Electronics Group U R Rao Satellite Centre Bengaluru India

ISBN: (数字)9798350395556

ISBN: (纸本)9798350395563

the phrase “On Board Computer” refers to the computer of the spacecraft's avionic subsystem. the “On Board Software” is the software that implements the satellite's critical functions, such as failure detection, isolation, recovery, on-board time synchronization, attitude and orbit control, tele-command execution and distribution, telemetry gathering and formatting, and automatic thermal control. On-Board Computer uses standard interfaces like MIL-STD-1553B, SPI, UART, etc. to communicate with the rest of the spacecraft. the FPGA is used as a central arbiter for the processor, RAM, protocol chips, input-output interfaces and PROM/EEPROM. Each subsystem may use a different protocol, the FPGA should be able to accommodate the possible types. the Single Event Upset performance of the SRAM and EEPROM is enhanced by employing an error detection and correction algorithm, single error correction and double error detection. the addressable capability of generic 16-bit processor is enhanced to accommodate larger physical memory, with the help of a memory management unit. the individual modules of the project, such as Error Detection and Correction, Serial Peripheral Interface, Universal Asynchronous Receiver-Transmitter, Memory Management Unit and Wait-States logic, were designed and verified using Verilog Hardware Description Language on Xilinx Vivado platform.

关键词： Space vehicles Military standards Protocols Memory management Random access memory logic gates Software

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An identification of bioimpedance spectroscopy parameters by the least squares method 6th

An identification of bioimpedance spectroscopy parameters by...

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6th international conference on Advanced Engineering theory and applications, AETA 2019

作者： Ozana, Stepan Prauzek, Michal Konecny, Jaromir Kawala-Sterniuk, Aleksandra Department of Cybernetics and Biomedical Engineering VSB-Technical University of Ostrava Ostrava-Poruba Czech Republic Faculty of Electrical Engineering Automatic Control and Informatics Opole University of Technology Opole Poland

ISBN: (纸本)9783030530204

this contribution deals with identification of bioimpedance spectroscopy parameters for implementation on embedded platforms. the paper’s goal is to present method which is suitable for implementation in microcontrollers or field programmable gate arrays. the paper brings brief description of the state of the art and it reviews an equivalent electrical model and the least squares method as background of the work. In experimental part, the author presenting an experimental setup for data acquisition for electrical model and an identification approach including the implementation details of calculation of inverse matrix. In the result section the comparison between real and identified parameters is presenting and the results are evaluated in terms of accuracy. the proposed method can be considered as precise identification for the particular electrical model. the paper conclusion includes discussion about method accuracy and brief outline for future work. © Springer Nature Switzerland AG 2021.

关键词： field programmable gate arrays (FPGA)

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Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases 17th

Exploiting 3D Memory for Accelerated In-Network Processing o...

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17th international Symposium on Applied Reconfigurable Computing, ARC 2021

作者： Wirth, Johannes Hofmann, Jaco A. thostrup, Lasse Koch, Andreas Binnig, Carsten Embedded Systems and Applications Group TU Darmstadt Hochschulstr. 10 Darmstadt64289 Germany Data Management Lab TU Darmstadt Hochschulstr. 10 Darmstadt64289 Germany

ISBN: (纸本)9783030790240

the computing potential of programmable switches with multi-Tbit/s throughput is of increasing interest to the research community and industry alike. Such systems have already been employed in a wide spectrum of applications, including statistics gathering, in-network consensus protocols, or application data caching. Despite their high throughput, most architectures for programmable switches have practical limitations, e.g., with regard to stateful operations. FPGAs, on the other hand, can be used to flexibly realize switch architectures for far more complex processing operations. Recently, FPGAs have become available that feature 3D-memory, such as HBM stacks, that is tightly integrated with their logic element fabrics. In this paper, we examine the impact of exploiting such HBM to accelerate an inter-server join operation at the switch-level between the servers of a distributed database system. As the hash-join algorithm used for high performance needs to maintain a large state, it would overtax the capabilities of conventional software-programmable switches. the paper shows that across eight 10G Ethernet ports, the single HBM-FPGA in our prototype can not only keep up with the demands of over 60 Gbit/s of network throughput, but it also beats distributed-join implementations that do not exploit in-network processing. © 2021, Springer Nature Switzerland AG.

关键词： field programmable gate arrays (FPGA)

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Distributed Recommendation Inference on FPGA Clusters

Distributed Recommendation Inference on FPGA Clusters

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international conference on field programmable logic and applications

作者： Yu Zhu Zhenhao He Wenqi Jiang Kai Zeng Jingren Zhou Gustavo Alonso Systems Group ETH Zurich Alibaba Group

Deep neural networks are widely used in personalized recommendation systems. Such models involve two major components: the memory-bound embedding layer and the computation-bound fully-connected layers. Existing solutions are either slow on both stages or only optimize one of them. To implement recommendation inference efficiently in the context of a real deployment, we design and implement an FPGA cluster optimizing the performance of both stages. To remove the memory bottleneck, we take advantage of the High-Bandwidth Memory (HBM) available on the latest FPGAs for highly concurrent embedding table lookups. To match the required DNN computation throughput, we partition the workload across multiple FPGAs interconnected via a 100 Gbps TCP/IP network. Compared to an optimized CPU baseline (16 vCPU, AVX2-enabled) and a one-node FPGA implementation, our system (four-node version) achieves 28.95× and 7.68× speedup in terms of throughput respectively. the proposed system also guarantees a latency of tens of microseconds per single inference, significantly better than CPU and GPU-based systems which take at least milliseconds.

关键词： Deep learning Computational modeling TCPIP throughput Table lookup field programmable gate arrays

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SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs

SyncNN: Evaluating and Accelerating Spiking Neural Networks ...

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international conference on field programmable logic and applications

作者： Sathish Panchapakesan Zhenman Fang Jian Li School of Engineering Science Simon Fraser University Canada Futurewei Technologies Inc USA

In this paper, we propose a novel synchronous approach for rate encoding based Spiking Neural Networks (SNNs), which is more hardware friendly than conventional asynchronous approaches. We also design and implement the SyncNN framework to accelerate SNNs on Xilinx ARM-FPGA SoCs in a synchronous fashion. To improve the computation and memory access efficiency, we first quantize the network weights to 16-bit, 8-bit, and 4-bit fixed-point values with the SNN friendly quantization technique. For the encoded neurons that have dynamic and irregular access patterns, we design parameterized compute engines to accelerate their performance on the FPGA, where we explore various parallelization strategies and memory access optimizations. Our experimental results on multiple Xilinx ARM-FPGA SoC boards demonstrate that our SyncNN is scalable to run multiple networks, such as LeNet, Network in Network, and VGG, on various datasets such as MNIST, SVHN, and CIFAR-10. SyncNN not only achieves competitive accuracy (99.6%) but also achieves state-of-the-art performance (13,086 frames per second) for the MNIST dataset.

关键词： Quantization (signal) Neurons Memory management Hardware Encoding Computational efficiency field programmable gate arrays

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