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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

共 2124 条记录，以下是261-270 订阅

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CONFIGURING AREA AND PERFORMANCE: EMPIRICAL EVALUATION ON AN FPGA-BASED BIOCHEMICAL SIMULATOR

CONFIGURING AREA AND PERFORMANCE: EMPIRICAL EVALUATION ON AN...

引用

19th international conference on field programmable logic and applications

作者： Ooya, T. Yamada, H. Ishimori, T. Shibata, Y. Osana, Y. Oguri, K. Yoshimi, M. Nishikawa, Y. Funahashi, A. Hiroi, N. Amano, H. Nagasaki Univ Nagasaki Japan Seikei Univ Musashino Tokyo Japan Doshisha Univ Kyoto Japan Keio Univ Keio Japan

ISBN: (纸本)9781424438914

One of the obvious advantages of FPGA-based reconfigurable computing is customizability of a tradeoff point between performance and hardware costs. However, this tradeoff has rarely been discussed in a whole application level, which is the most important view for application users. this paper presents empirical evaluation of a hardware module sharing technique which can shift a tradeoff point of area and performance on an FPGA-based biochemical simulator. the biochemical simulation results are discussed in terms of hardware costs, simulation throughput, parallelism extracted in simulation hardware, and data transfer overheads.

关键词： field programmable gate arrays (FPGA)

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A TECHNIQUE FOR MINIMIZING POWER DURING FPGA PLACEMENT

A TECHNIQUE FOR MINIMIZING POWER DURING FPGA PLACEMENT

引用

18th international conference on field programmable and logic applications

作者： Vorwerk, Kristofer Raman, Madhu Dunoyer, Julien Hsu, Yaun-chung Kundu, Arun Kennings, Andrew Actel Corp Mountain View CA USA

ISBN: (纸本)9781424419609

this paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. the proposed method comprises a power-aware objective function for placement and is implemented in a commercial tool. In particular, a capacitance model based on multi-dimensional nonlinear regression is described, as well as a new capacitance model for global nets. the importance and advantages of these models are highlighted in terms of the overall attainable reduction in power in a real, commercially-available architecture and tool flow. the results are quantified across a range of industrial benchmarks targeting the Actel (R) IGLOO (TM) FPGA architecture. Power measurements show that, across a suite of 120 industrial designs, the technique described in this paper reduces dynamic power by 13% on average, with only a 1% degradation in timing performance.

关键词： field programmable gate arrays (FPGA)

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Accelerated Wire-Speed Packet Capture at 200 Gbps 28

Accelerated Wire-Speed Packet Capture at 200 Gbps

引用

28th international conference on field programmable logic and applications (FPL)

作者： Kekely, Lukas Spinler, Martin Friedl, Stepan Sikora, Jiri Korenek, Jan CESNET Ale Zikova 4 Prague 16000 Czech Republic

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We present our latest FPGA acceleration card NFB-200G2QL that is specifically designed to enable traffic processing at 200 Gbps. Unique high-speed DMA engines in the FPGA together with highly optimized Linux drivers enable data transfer through PCIe interfaces with minimal CPU overhead. Captured traffic can be independently distributed between individual cores of two physical CPUs (NUMA nodes) without utilization of QPI. As a result, wire-speed packet capture to the host memory from two fully saturated 100 Gbps Ethernet interfaces (QSFP28+ cages) is achieved and various network monitoring applications can utilize the power of the latest FPGAs and CPUs for data processing. this is especially useful when both directions of a single 100GbE link are monitored. the live demonstration shows how the packets are received from two 100 Gbps Ethernet links at wire-speed and captured to the host memory at 200 Gbps without a loss. the opposite direction of communication is also shown, i.e. how the packets are transmitted from the host memory and fully saturate the two 100GbE network interfaces. Achieved speeds are demonstrated by counters and gauges showing generated, received/transmitted and captured packets. We also show statistics of CPU load during the packet capture/transmission for different packet lengths.

关键词： field programmable gate arrays Ethernet throughput Data transfer Standards Acceleration Monitoring

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A Programming Model and Runtime System for Approximation-Aware Heterogeneous Computing 27

A Programming Model and Runtime System for Approximation-Awa...

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27th international conference on field programmable logic and applications (FPL)

作者： Parnassos, Ioannis Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Nikolaos Gkaras, Athanasios Kanellis, Konstantinos Antonopoulos, Christos D. Spyrou, Michalis Maroudas, Manolis Univ Thessaly Elect & Comp Engn Dept Volos Greece

ISBN: (纸本)9789090304281

Heterogeneous platforms that include diverse architectures such as multicore CPUs, FPGAs and GPUs are becoming very popular due to their superior performance and energy efficiency. Besides heterogeneity, a promising approach for minimizing energy consumption is through approximate computing which relaxes the requirement that all parts of a program are considered equally important to the output quality, thus, all should be executed at full accuracy. Our work extends a traditional OpenMP-like programming model and runtime system to support seamless execution on hybrid architectures with approximation semantics. Starting from a common application code, annotated with our programming model, the programmer can not only target heterogeneous architectures comprising CPU, FPGA and GPU components, but can also regulate the amount of approximation. We evaluate our framework on a number of large-scale applications and demonstrate that the combination of heterogeneous and approximate computing can provide a powerful dynamic interplay between performance and output quality.

关键词： field programmable gate arrays Kernel Runtime Graphics processing units Programming Histograms

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Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA 34

Techniques for Exploring Fine-Grained LUT and Routing Aging ...

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34th international conference on field-programmable logic and applications (FPL)

作者： Cook, Hayden Goeders, Jeffrey Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

ISBN: (纸本)9798331530082;9798331530075

Understanding how FPGAs age and how to control that aging is crucial for ensuring the reliability and security of FPGAs in critical applications. Due to the proprietary nature of commercial FPGAs, it can be challenging to validate aging models on real silicon, and most previous work has relied on circuit simulations to study the effects of FPGA aging. In this work, we leverage low-level placement and routing APIs provided by RapidWright to create a series of stressor and characterization circuits that allow us to measure the effects of aging on individual LUTs and routing resources in a 28nm FPGA. We demonstrate how these techniques allow fine-grained control of the relative aging of different FPGA resources, even to the point of aging individual paths within a single LUT. Several different aging experiments are demonstrated, and in a cumulative test, we show how different signal and LUT configurations can influence the aging rate by over 2x.

关键词： field programmable gate arrays (FPGA)

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IP PROTECTION IN PARTIALLY RECONFIGURABLE FPGAS

IP PROTECTION IN PARTIALLY RECONFIGURABLE FPGAS

引用

19th international conference on field programmable logic and applications

作者： Kepa, Krzysztof Morgan, Fearghal Kosciuszkiewicz, Krzysztof Natl Univ Ireland Dept Elect Engn Galway Ireland

ISBN: (纸本)9781424438914

As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. the current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. this paper proposes the use of a Secure Reconfigurable Controller (SeReCon) for accounting of IP core usage, e.g. total runtime, no. of activations etc, in a PR system. this paper extends the reported SeReCon root-of-trust to support license enforcement within the PR flow and to facilitate confidentiality of the IP core during the PR system life-cycle. A prototype IP-aware SeReCon demonstrator, implemented on Virtex-5 and supporting reconfiguration of a PCIe accelerator with cryptographic IP cores is described.

关键词： field programmable gate arrays (FPGA)

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Resource Elastic Virtualization for FPGAs using OpenCL 28

Resource Elastic Virtualization for FPGAs using OpenCL

引用

28th international conference on field programmable logic and applications (FPL)

作者： Vaishnav, Anuj Khoa Dang Pham Koch, Dirk Garside, James Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an approach to manage FPGA resources with OS functionality, this paper introduces the concept of resource elastic virtualization which allows shrinking and growing of accelerators in the spatial domain with the help of partial reconfiguration. With this, we can serve multiple applications simultaneously on the same FPGA and optimize the resource utilization and consequently the overall system performance. We demonstrate how an implementation of resource elasticity can be realized for OpenCL accelerators along with how it can achieve 23x better FPGA utilization and 49% better performance on average while simultaneously lowering waiting time for tasks.

关键词： field programmable gate arrays Task analysis Hardware Virtualization Resource management Elasticity Layout

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Designing a Virtual Runtime for FPGA Accelerators in the Cloud 26

Designing a Virtual Runtime for FPGA Accelerators in the Clo...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Asiatici, Mikhail George, Nithin Vipin, Kizheppau Fahmy, Suhaib A. Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Mahindra Ecole Cent Hyderabad Telangana India Univ Warwick Sch Engn Coventry CV4 7AL W Midlands England

ISBN: (纸本)9782839918442

FPGAs can provide high performance and energy efficiency to many applications;therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly limits the potential user base. Moreover, in a cloud setting, allocating a whole FPGA to a user is often wasteful and not cost effective due to low device utilization. To make FPGA application development easier, firstly, we propose a methodology that provides clean abstractions with high-level APIs and a simple execution model that supports both software and hardware execution. Secondly, to improve device utilization and share the FPGA among multiple users, we developed a lightweight runtime system that provides hardware-assisted memory virtualization and memory protection, enabling multiple applications to simultaneously execute on the device.

关键词： field programmable gate arrays (FPGA)

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USING 3D INTEGRATION TECHNOLOGY TO REALIZE MULTI-CONTEXT FPGAS

USING 3D INTEGRATION TECHNOLOGY TO REALIZE MULTI-CONTEXT FPG...

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19th international conference on field programmable logic and applications

作者： Cevrero, Alesandro Athanasopoulosi, Panagiotis Parandeh-Afshar, Hadi Skerlj, Maurizio Brisk, Philip Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Sch Engn CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781424438914

this paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. the DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes;the new configuration is loaded from the latch array into the FPGA in 60ns (5 cycles). the latency between reconfigurations, 8.42 mu s, is dominated by the time to read data from the DRAM into the latch array. We estimate that the DRAM can cache 289 FPGA contexts.

关键词： field programmable gate arrays (FPGA)

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SEPARABLE IMPLEMENTATION OF thE SECOND ORDER VOLTERRA FILTER (SOVF) IN XILINX VIRTEX-E FPGA

SEPARABLE IMPLEMENTATION OF THE SECOND ORDER VOLTERRA FILTER...

引用

18th international conference on field programmable and logic applications

作者： Al-Mistarihi, Mamoun F. Jordan Univ Sci & Technol Fac Engn Dept Elect Engn Irbid 22110 Jordan

ISBN: (纸本)9781424419609

Post-beamforming second order Volterra filter (SOVF) was previously introduced for decomposing the pulse echo ultrasonic radio-frequency (RF) signal into its linear and quadratic components. Using singular value decomposition (SVD), an optimal minimum-norm least squares algorithm for deriving the coefficients of the linear and quadratic kernels of the SOVF was developed and verified. the "Separable" implementation algorithm of a SOVF based on the eigenvalue decomposition (EVD) of the quadratic kernel was introduced and verified. In this paper, the "Separable" version of a Second Order Volterra filter is implemented in Xilinx Virtex-E FPGA. Parallel operation, efficient use of instructions per task, and data streaming capability of FPGA are identified. this implementation should allow for real-time implementation of quadratic filtering on commercial ultrasound scanners.

关键词： field programmable gate arrays (FPGA)

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