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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

共 2126 条记录，以下是271-280 订阅

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Tinsel: a manythread overlay for FPGA clusters 29

Tinsel: a manythread overlay for FPGA clusters

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Naylor, Matthew Moore, Simon W. thomas, David Univ Cambridge Cambridge England Imperial Coll London London England

ISBN: (纸本)9781728148847

Commodity FPGA boards with advanced networking facilities have great potential in the construction of high-performance compute clusters that scale. However, low-level design tools and long synthesis times are major barriers to productivity for application developers. In this paper, we explore the potential of a distributed soft-processor overlay, programmed in software at a high-level of abstraction, to deliver a useful level of performance for FPGA clusters. In particular, we demonstrate the use of hardware multhreading to achieve a fast, space-efficient, high-throughput overlay, and compare a 12-FPGA instance of it (12,288 RISC-V threads) against a conventional Xeon cluster on the problem of distributed graph processing.

关键词： Message systems field programmable gate arrays Random access memory Hardware Software Pipelines throughput

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Low-level Loop Analysis and Pipelining of applications mapped to Xilinx FPGAs 29

Low-level Loop Analysis and Pipelining of Applications mappe...

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Omidian, Hossein Lemieux, Guy G. F. Xilinx Inc San Jose CA 95124 USA Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9781728148847

In this paper we investigate using low-level loop analysis to identify common loop patterns in the netlist generated by the synthesis flow and use loop optimization techniques to increase Fmax of applications implemented on Xilinx FPGAs. Ordinarily, feed-forward paths in the netlist can be easily pipelined. the focus of this study is only sequential loops (with feedback cycles) that are more challenging to optimize. We show that, using low-level loop analysis, we can improve Fmax on average by 57% and achieve an average Fmax of 714MHz across seven industrial designs. Using aggressive loop combining, we also show that we can save 18% area on average while still improving the Fmax by 15% to 41% on four of the seven designs.

关键词： Low-level Loop Analysis FPGA Pipeline Loop Transformation

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Research and implementation of an automatic simulation tool 7

Research and implementation of an automatic simulation tool

引用

7th international conference on Dependable Systems and their applications, DSA 2020

作者： Tang, Liu Li, You Wang, Hongwei Zhao, Huan Ma, Luze Sun, Yuming Beijing Sunwise Information Technology Ltd. China

ISBN: (纸本)9780738124223

With the rapidly increasing of space missions, FPGA is more widely used for its ability of single chip approaching 10 million gates of logic and 10 million bits of memory. More and more challenges are posed to FPGA design and verification, with the characteristics of a tight schedule, a burdensome task, momentous responsibilities, etc. A reusable and robust environment for verification is needed to improve the efficiency and quality of verification. In this paper, we present a series of research works, including what kinds of simulation techniques should be used and which methodology should be addressed. By using the Universal Verification Methodology (UVM) template, the verification modeling is done by us, and verification code is generated with FPGA automatic simulation tool (SunwiseFAS). the performance of this tool on automatic constructing simulation environment is presented, too. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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ZytleBot: FPGA integrated development platform for ROS based autonomous mobile robot 29

ZytleBot: FPGA integrated development platform for ROS based...

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Nitta, Yasuhiro Tamura, So Takase, Hideki Kyoto Univ Grad Sch Informat Kyoto Japan

ISBN: (纸本)9781728148847

ZytleBot is an autonomous driving robot with an FPGA-integrated development platform that uses the Xilinx programmable system-on-chip (SoC). ZytleBot can run a course, turn right/left at intersections, avoid obstacles, detect traffic signals, and stop. All judgments and calculations necessary for driving are performed on the embedded system mounted on the robot. In ZytleBot, the main autonomous driving system uses the Robot Operating System (ROS) running on a CPU, and high-load processing is offloaded to the FPGA to enable real-time operation. the FPGA preprocesses road surface images acquired from the camera and detects traffic signals. We demonstrate the running of ZytleBot on a miniature course to win the FPT' 18 FPGA design competition(1). We also provide ZytleBot as a platform for the efficient development of FPGA-integrated ROS robots.

关键词： field programmable gate arrays Cameras Robot vision systems Hardware Software Mobile robots

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Characterizing Power Distribution Attacks in Multi-User FPGA Environments 29

Characterizing Power Distribution Attacks in Multi-User FPGA...

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Provelengios, George Holcomb, Daniel Tessier, Russell Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)9781728148847

Multi-tenant FPGAs that contain circuits from multiple users are emerging as a new usage model in cloud and embedded computing environments. Interactions between un-trusting tenant applications in an FPGA can enable new security exposures and the risk of side channel attacks or fault injection. In this work, we investigate the ability for aggressive power consumption of one application to disturb the power network to an extent that causes delay faults in a second application on the same FPGA. In particular, we identify the mechanisms by which the supply voltage is disturbed by the attack, and we characterize the magnitude of the disturbance as a function of time, power consumed by attacker, and position of the victim relative to the attacker. We highlight strategies that can be used to mitigate attacks, including low-cost monitoring circuits that can identify the source of an attack so that the attacker's use of the FPGA can be revoked.

关键词： field programmable gate arrays Voltage measurement Sensors Frequency measurement System-on-chip Cyclones Cloud computing

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FPGA Accelerated FPGA Placement 29

FPGA Accelerated FPGA Placement

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29th international conference on field-programmable logic and applications (FPL)

作者： Dhar, Shounak Singhal, Love Iyer, Mahesh A. Pan, David Z. Univ Texas Austin ECE Dept Austin TX 78712 USA Intel Corp San Jose CA USA

ISBN: (纸本)9781728148847

Placement is one of the runtime bottlenecks in an FPGA design implementation flow, in which global placement accounts for a major portion of the runtime. In this paper, we demonstrate FPGA acceleration of wirelength gradient computation, which is an important part of modern analytical placement tools. To the best of our knowledge, this is the first work on acceleration of analytical placement on FPGAs. Our implementation uses OpenCL and leverages the FPGA's ability to support deep pipelines. We achieve an average speedup of 3.03x for wirelength gradient computation only and 2x for the entire global placement flow over a 28-threaded CPU implementation. Our placement quality is comparable to previously published works. Additionally, we can finish global placement for a design with 1 million cells and 1 million nets in less than 1 minute.

关键词： field programmable gate arrays Pins Acceleration Adders Runtime Tools Measurement

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Demonstration of a Multimode SoC FPGA-based Acoustic Camera 29

Demonstration of a Multimode SoC FPGA-based Acoustic Camera

引用

29th international conference on field-programmable logic and applications (FPL)

作者： da Silva, Bruno Segers, Laurent Braeken, An Touhafi, Abdellah VUB Dept Ind Sci INDI Brussels Belgium VUB Dept Elect & Informat ETRO Brussels Belgium

ISBN: (纸本)9781728148847

the relatively low-cost of the Micro-Electromechanical Systems (MEMS) microphones together with recent advances in the MEMS technology facilitates the construction of large MEMS microphone arrays, which are used to collect the acoustic information from certain beamed directions by applying beamforming techniques. the use of beamforming techniques to steer the microphone array response is the principle used by acoustic cameras to graphically display the acoustic information in a heatmap form. Our demonstrator exploits the heterogeneous nature of System-on-Chip (SoC) FPGA systems by generating real-time acoustic images on the FPGA component while alleviating the Wireless Sensor Networks (WSN) bandwidth limitations by performing acoustic image processing locally on the hard-core processor. As a result, a real-time acoustic heatmap is generated, enabling the visualization of the sound sources characteristics.

关键词： Acoustics Wireless sensor networks Cameras Micromechanical devices field programmable gate arrays Microphone arrays

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Neural Network Overlay Using FPGA DSP Blocks 29

Neural Network Overlay Using FPGA DSP Blocks

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29th international conference on field-programmable logic and applications (FPL)

作者： Ioannou, Lenos Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9781728148847

With the increasing wider application of neural networks, there has been significant focus on accelerating this class of computations. Larger, more complex networks are being proposed in a variety of domains, requiring more powerful computation platforms. the inherent parallelism and regularity of neural network structures means custom architectures can be adopted for this purpose. FPGAs have been widely used to implement such accelerators because of their flexibility, achievable performance, efficiency, and abundant peripherals. While platforms that utilize multicore CPUs and GPUs are also competitive, FPGAs offer superior energy efficiency, and a wider space of optimisations to enhance performance and efficiency. FPGAs are also more suitable for performing such computations at the edge, where multicore CPUs and GPUs are are less likely to be used and energy efficiency is paramount.

关键词： Biological neural networks field programmable gate arrays Computer architecture Neurons Parallel processing Optimization

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A Deep Learning Framework to Predict Routability for FPGA Circuit Placement 29

A Deep Learning Framework to Predict Routability for FPGA Ci...

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Alhyari, A. Shamli, A. Abuwaimer, Z. Areibi, S. Grewal, G. Univ Guelph Sch Engn Guelph ON Canada Univ Guelph Sch Comp Sci Guelph ON Canada

ISBN: (纸本)9781728148847

the ability to accurately and efficiently estimate the routability of a circuit based on its placement is one of the most challenging and difficult tasks in the field programmable Gate Array (FPGA) flow. In this paper, we present a novel, deep-learning framework based on a Convolutional Neural Network model for predicting the routability of a placement. We also incorporate the deep-learning model into a state-of-the-art placement tool, and show how the model can be used to (1) avoid costly, but futile, place-and-route iterations, and (2) improve the placer's ability to produce routable placements for hard-to-route circuits using feedback based on routability estimates generated by the proposed model. the model is trained and evaluated using over 26K placement images derived from 372 benchmarks supplied by Xilinx Inc. Experimental results show that the proposed framework achieves a routability prediction accuracy of 97%, while exhibiting runtimes of only a few milliseconds.

关键词： Routing Integrated circuit modeling field programmable gate arrays Benchmark testing Heating systems Machine learning Predictive models

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FPGA Accelerated Deep Learning Radio Modulation Classification Using MATLAB System Objects & PYNQ 29

FPGA Accelerated Deep Learning Radio Modulation Classificati...

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29th international conference on field-programmable logic and applications (FPL)

作者： Maclellan, Andrew McLaughlin, Lewis Crockett, Louise Stewart, Robert W. Univ Strathclyde Dept Elect & Elect Engn Glasgow Lanark Scotland

ISBN: (纸本)9781728148847

Floating point Convolutional Neural Networks (CNNs) are computationally expensive and deeper networks can be impractical to deploy on FPGAs consuming a large number of resources and power, as well as having lengthy development times. Previous work has shown that CNNs can be quantised heavily using fixed point arithmetic to combat this without significant loss in classification accuracy. We aim to quantise an existing CNN architecture for radio modulation classification to 2-bit weights and activations, while retaining a level of accuracy close to the original paper, for deployment on a Zynq System on Chip (SoC). To improve the development time for hardware synthesisable CNNs, we make use of MATLAB System Objects and HDL Coder. the PYNQ framework is presented as a practical means for accessing the functionality of the CNN. Our preliminary results show a high classification accuracy even with 2-bit weights and activations.

关键词： field programmable gate arrays Modulation Matlab Hardware design languages Training Biological neural networks

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