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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

共 2124 条记录，以下是281-290 订阅

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High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences

High speed tablation system using an FPGA designed for distr...

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17th international conference on field programmable logic and applications

作者： Yamaguchi, Yoshiki Maruyama, Tsutomu Konishi, Fumikazu Konagaya, Akihiko Univ Tsukuba 1-1-1 Tenou Dai Tsukuba Ibaraki 3058573 Japan RIKEN Genom Sci Ctr Genom Sci Cent Kanagawa 2300045 Japan

ISBN: (纸本)9781424410590

A method is described for enumerating the frequencies of DNA subsequences on a system comprising a host computer and a field programmable gate array (FPGA) board with one FPGA. Frequencies of subsequences with lengths of up to K-0 K-1 K-2 (24 in the current implementation) are enumerated in three phases. In these three phases, subsequences with lengths of up to K-0, K (0) K-1, and K-0 K-1 K-2, respectively, are enumerated;these three phases are executed simultaneously on a pipelined circuit, resulting in high performance. the enumeration of frequent subsequences in databases, which are becoming larger and larger, will enable subsequences that are unique and/or repeatedly used in many parts of the sequences to be found.

关键词： field programmable gate arrays (FPGA)

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Static Hardware Task Placement on Multi-Context FPGA Using Hybrid Genetic Algorithm 25

Static Hardware Task Placement on Multi-Context FPGA Using H...

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25th international conference on field programmable logic and applications

作者： Liang, Hao Sinha, Sharad Warrier, Rakesh Zhang, Wei Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781467381239

field programmable Gate Arrays (FPGAs) are becoming pervasive in various kinds of computationally demanding applications. Working in a tightly coupled processor-coprocessor architecture, FPGAs are often anticipated to accelerate multiple fine-grained or coarse-grained tasks simultaneously. Single-context FPGAs are commonly used in such systems. With the recent development of emerging memory technologies, multicontext FPGAs that support dynamic reconfiguration with high-density non-volatile memories become feasible. Compared to single-context FPGAs, multi-context FPGAs are able to accelerate significantly more tasks with only moderate area and power overhead. However, the best way to utilize the computation capacity advantage of multi-context FPGAs for hardware task mapping remains an interesting and unexploited problem. In this paper, we first propose the framework of a processor-coprocessor architecture with multi-context FPGA as the coprocessor for multiple-task acceleration. Under the framework, a hybrid placement strategy based on genetic and greedy algorithms is proposed to efficiently place a set of tasks onto the multi-context FPGA to achieve the best logic capacity utilization. Experiments on real and synthetic benchmarks demonstrate the efficiency of the proposed algorithm compared with other general approaches.

关键词： field programmable gate arrays (FPGA)

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Voltage Drop-based Fault Attacks on FPGAs using Valid Bitstreams 27

Voltage Drop-based Fault Attacks on FPGAs using Valid Bitstr...

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27th international conference on field programmable logic and applications (FPL)

作者： Gnad, Dennis R. E. Oboril, Fabian Tahoori, Mehdi B. Karlsruhe Inst Technol Inst Comp Engn Karlsruhe Germany

ISBN: (纸本)9789090304281

Due to the widespread use of FPGAs in many critical application domains, their security is of high concern. In recent systems, such as FPGAs in the Cloud or in Systems-on-Chip (SoCs), users can gain access, even remotely, to the reconfigurable fabric to implement custom accelerators. this access can expose new security vulnerabilities in the entire system through malicious use of the FPGA fabric. In the past, attacks on the power supply level required local access to the hardware. In this paper, we reveal a security vulnerability in FPGAs that allows a valid configuration to generate severe voltage fluctuations, which crashes the FPGA within a few microseconds. Moreover, the extent of this crash is so severe, that manual power-cycling is required to be able to access and use the system again. this vulnerability has been systematically exploited in two different generations of FPGAs, and a SoC containing an FPGA. Because this vulnerability can lead to severe security attacks in systems using FPGA-based accelerators, we also analyze its underlying mechanism, and discuss possibilities for mitigation.

关键词： field programmable gate arrays Security Delays Clocks Latches Fabrics Computer crashes

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Dynamic Power Estimation Based on Switching Activity Propagation 27

Dynamic Power Estimation Based on Switching Activity Propaga...

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27th international conference on field programmable logic and applications (FPL)

作者： Nasser, Y. Prevotet, J. -C. Helard, M. Lorandel, J. INSA Rennes IETR Rennes France Univ Cergy Pontoise ENSEA CNRS ETIS Univ Paris SeineUMR 8051 Cergy Pontoise France

ISBN: (纸本)9789090304281

A new power estimation approach based on the decomposition of a digital system into basic operators is presented. this approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated to provide a global power estimation of a given system. A simple sum of the power dissipation contribution of each operator is enough to compute the total power consumption. this is performed by taking into account the switching activities relative to a given input pattern. Earlier, faster and more flexible power analysis for system designers are the advantages. this approach has been evaluated in a use-case application. the preliminary results indicate a promising speed-up of the design process and an error which is less than 8.0% compare to the classical power estimation tools.

关键词： Estimation Integrated circuit modeling field programmable gate arrays Switches Computational modeling Power demand Neural networks

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Customizing Low-Precision Deep Neural Networks For FPGAs 28

Customizing Low-Precision Deep Neural Networks For FPGAs

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28th international conference on field programmable logic and applications (FPL)

作者： Faraone, Julian Gambardella, Giulio Boland, David Fraser, Nicholas Blott, Michaela Leong, Philip H. W. Univ Sydney Sydney NSW Australia Xilinx Res Labs Dublin Ireland

ISBN: (纸本)9781538685174

In this paper, we argue that instead of solely focusing on developing efficient architectures to accelerate well-known low-precision CNNs, we should also seek to modify the network to suit the FPGA. We develop a fully automative toolflow which focuses on modifying the network through filter pruning, such that it efficiently utilizes the FPGA hardware whilst satisfying a predefined accuracy threshold. Although fewer weights are removed in comparison to traditional pruning techniques designed for software implementations, the overall model complexity and feature map storage is greatly reduced. We implement the AlexNet and TinyYolo networks on the large-scale ImageNet and PascalVOC datasets, to demonstrate up to roughly 2x speedup in frames per second and 2x reduction in resource requirements over the original network, with equal or improved accuracy.

关键词： field programmable gate arrays Hardware Quantization (signal) throughput Memory management Neural networks

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FPGA Accelerated FPGA Placement 29

FPGA Accelerated FPGA Placement

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29th international conference on field-programmable logic and applications (FPL)

作者： Dhar, Shounak Singhal, Love Iyer, Mahesh A. Pan, David Z. Univ Texas Austin ECE Dept Austin TX 78712 USA Intel Corp San Jose CA USA

ISBN: (纸本)9781728148847

Placement is one of the runtime bottlenecks in an FPGA design implementation flow, in which global placement accounts for a major portion of the runtime. In this paper, we demonstrate FPGA acceleration of wirelength gradient computation, which is an important part of modern analytical placement tools. To the best of our knowledge, this is the first work on acceleration of analytical placement on FPGAs. Our implementation uses OpenCL and leverages the FPGA's ability to support deep pipelines. We achieve an average speedup of 3.03x for wirelength gradient computation only and 2x for the entire global placement flow over a 28-threaded CPU implementation. Our placement quality is comparable to previously published works. Additionally, we can finish global placement for a design with 1 million cells and 1 million nets in less than 1 minute.

关键词： field programmable gate arrays Pins Acceleration Adders Runtime Tools Measurement

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A Systematic Approach to Design and Optimise Streaming applications on FPGA Using High-Level Synthesis 27

A Systematic Approach to Design and Optimise Streaming Appli...

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27th international conference on field programmable logic and applications (FPL)

作者： Hosseinabady, Mohammad Nunez-Yanez, Jose Luis Univ Bristol Dept Elect & Elect Engn Bristol Avon England

ISBN: (纸本)9789090304281

this paper proposes a systematic approach to help designers to optimise a given streaming application for FPGAs using High-Level Synthesis (HLS). the proposed technique specifically addresses the two main issues in a streaming application that are determining the exact amount of loop unrolling in the HLS code to increase the throughput and finding the optimum buffers' size to prevent deadlocks. To evaluate the proposed techniques two applications from the machine learning optimisation area are studied in the paper. these applications are Hessian-vector product and Conjugate Gradient (CG). the experimental results show up to 38x speed-up in throughput compared to the original streaming implementations provided by knowledgeable engineers using the dataflow, loop pipelining and FIFO channel related pragmas provided by the HLS tool. In addition, these applications show up to 2.98 GB/sec usage of memory bandwidth which is 93.1% of the total memory bandwidth available on the system. the source codes of the designs are available at https://***/Hosseinabady/csdfg-hls.

关键词： throughput Tools Systematics Optimization Bandwidth System recovery

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Demonstration of a Multimode SoC FPGA-based Acoustic Camera 29

Demonstration of a Multimode SoC FPGA-based Acoustic Camera

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29th international conference on field-programmable logic and applications (FPL)

作者： da Silva, Bruno Segers, Laurent Braeken, An Touhafi, Abdellah VUB Dept Ind Sci INDI Brussels Belgium VUB Dept Elect & Informat ETRO Brussels Belgium

ISBN: (纸本)9781728148847

the relatively low-cost of the Micro-Electromechanical Systems (MEMS) microphones together with recent advances in the MEMS technology facilitates the construction of large MEMS microphone arrays, which are used to collect the acoustic information from certain beamed directions by applying beamforming techniques. the use of beamforming techniques to steer the microphone array response is the principle used by acoustic cameras to graphically display the acoustic information in a heatmap form. Our demonstrator exploits the heterogeneous nature of System-on-Chip (SoC) FPGA systems by generating real-time acoustic images on the FPGA component while alleviating the Wireless Sensor Networks (WSN) bandwidth limitations by performing acoustic image processing locally on the hard-core processor. As a result, a real-time acoustic heatmap is generated, enabling the visualization of the sound sources characteristics.

关键词： Acoustics Wireless sensor networks Cameras Micromechanical devices field programmable gate arrays Microphone arrays

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NOVEL FPGA BASED HAAR CLASSIFIER FACE DETECTION ALGORIthM ACCELERATION

NOVEL FPGA BASED HAAR CLASSIFIER FACE DETECTION ALGORITHM AC...

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18th international conference on field programmable and logic applications

作者： Gao, Changjian Lu, Shih-Lien Broadcom Corp Wireless Connect 16340 W Bernardo Dr San Diego CA 92127 USA Intel Corp Microarchitecture Res Hillsboro OR 97124 USA

ISBN: (纸本)9781424419609

We present here a novel approach to use FPGA to accelerate the Haar-classifier based face detection algorithm. With highly pipelined microarchitecture and utilizing abundant parallel arithmetic units in the FPGA, we've achieved real-time performance of face detection having very high detection rate and low false positives. Moreover, our approach is flexible toward the resources available on the FPGA chip. this work also provides us an understanding toward using FPGA for implementing non-systolic based vision algorithm acceleration. Our implementation is realized on a HiTech Global PCIe card that contains a Xilinx XC5 VLX110T FPGA chip.

关键词： field programmable gate arrays (FPGA)

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A seamless DFT/FFT self-adaptive architecture for embedded radar applications 30

A seamless DFT/FFT self-adaptive architecture for embedded r...

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30th international conference on field-programmable logic and applications (FPL)

作者： Mazuet, Julien Narozny, Michel Dezan, Catherine Diguet, Jean-Philippe Thales LAS France Elancourt France UBO UBS Lab STICC CNRS Brest France

ISBN: (纸本)9781728199023

Radar is one of the domains where adaptability is paramount and algorithms must be adapted to system state. However, most systems include static implementations on FPGA or ASIC to process the massive amount of data from multiple sensors in parallel. the classic approach is to configure hardware logic through registers to switch radar modes, requiring to hardwire all configurations. In embedded systems, FPGA dynamic partial reconfiguration (DPR) is a promising solution to reuse scarce resources. In this paper, we use DPR for radar processing in order to switch between a classic discrete Fourier transform (DFT) sum and a fast Fourier transform (FFT) to enhance Doppler extraction. Our study explores the pros and cons of both methods. Based on these observations, we propose a new architecture and decision method that relies on Radar QoS for enabling an efficient self-adaptive solution. Finally, we provide a case study and a hardware-in-loop simulation with a reconfigurable radar implementation.

关键词： FPGA DPR radar QoS DFT

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