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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

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Accelerating Position-Aware Top-k ListNet for Ranking under Custom Precision Regimes 29

Accelerating Position-Aware Top-k ListNet for Ranking under ...

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29th international conference on field-programmable logic and applications (FPL)

作者： Li, Qiang Wang, Erwei Fleming, Shane T. thomas, David B. Cheung, Peter Y. K. Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (纸本)9781728148847

Document ranking is used to order query results by relevance with ranking models. ListNet is a well-know ranking approach for constructing and training learning to rank models. Compared with traditional learning approaches, ListNet delivers better accuracy, but is computationally too expensive to learn models with large datasets due to the large number of permutations involved in computing the gradients. this paper introduces a position-aware sampling approach, which takes the importance of ranking positions into account and shows better accuracy than previous sampling methods. We also propose an effective quantisation method based on FPGA devices for the ListNet algorithm, which organises the gradient values to several batches, and associates each batch with a different fractional precision. We implemented our approach on a Xilinx ultrascale+ board and applied it to the MQ 2008 benchmark dataset for ranking. the experiment results show a 4.42x speedup over an Nvidia GTX 1080T GPU implementation with 2% accuracy loss.

关键词： Training Computational modeling Computational complexity field programmable gate arrays Stochastic processes Optimization

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Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage 29

Becoming More Tolerant: Designing FPGAs for Variable Supply ...

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29th international conference on field-programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Shen, Linda L. Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781728148847

With the end of Dennard scaling, FPGA power consumption has become a major concern. While FPGAs are conventionally supplied by a fixed supply voltage (V-dd), recent industrial (SmartVID) and academic solutions (dynamic voltage scaling) have shown significant power savings by scaling the FPGA V-dd on a chip-specific or chip- and application-specific basis. However, FPGAs have historically been designed for fixed-V-dd operation, which raises the question of whether we can design FPGA circuitry that is better suited for voltage scaling. In this work, we show that conventional LUTs are more sensitive to voltage than routing, so we design different LUT circuits that are more tolerant to voltage scaling. Compared to a conventional LUT, our fastest proposed LUT reduces the average critical path delay by 14% and 47% at nominal (0.8 V) V-dd and at reduced (0.6 V) V-dd, respectively. this significant reduction in delay comes at a cost of only 8% FPGA tile area increase. Our proposed LUT designs result in lower energy-delay and energy-delay(2) products at nominal V-dd and below.

关键词： field programmable gate arrays Table lookup Delays Routing Multiplexing Transistors logic gates

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OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs 29

OpenFPGA: An Opensource Framework Enabling Rapid Prototyping...

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29th international conference on field-programmable logic and applications (FPL)

作者： Tang, Xifan Giacomin, Edouard Alacchi, Aurelien Chauviere, Baudouin Gaillardon, Pierre-Emmanuel Univ Utah Lab NanoIntegrated Syst LNIS Salt Lake City UT 84112 USA

ISBN: (纸本)9781728148847

Driven by the strong need in data processing applications, field programmable Gate Arrays (FPGAs) are playing an ever-increasing role as programmable accelerators in modern computing systems. To fully unlock processing capabilities for domain-specific applications, FPGA architectures have to be tailored for seamless cooperation with other computing resources. However, prototyping and bringing to production a customized FPGA is a costly and complex endeavor even for industrial vendors. In this paper, we introduce OpenFPGA, an open-source framework that enables rapid prototyping of customizable FPGA architectures through a semi-custom design approach. We propose an XML-to-Prototype design flow, where the Verilog netlists of a full FPGA fabric can be autogenerated using an extension of the XML language from the VTR framework and then fed into a back-end flow to generate production-ready layouts. OpenFPGA also includes a general-purpose Verilog-to-Bitstream generator for any FPGA described by the XML language. We demonstrate the capability of this automatic design flow with a Stratix IV-like FPGA architecture using a commercial 40nm technology node, and perform a detailed comparison to its academic and commercial counterparts. Compared to the current state-of-art academic results, our FPGA fabric reduces the area by 1.75x and the delay by 3x on average. In addition, OpenFPGA significantly reduces the gap between semi-custom-designed FPGAs and fully-optimized commercial products with a penalty of only 60% in area and 30% in delay, respectively.

关键词： field programmable gate arrays Computer architecture Hardware design languages XML Microprocessors Layout Libraries

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Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision applications 29

Quantifying the Benefits of Dynamic Partial Reconfiguration ...

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29th international conference on field-programmable logic and applications (FPL)

作者： Nguyen, Marie Tamburo, Robert Narasimhan, Srinivasa Hoe, James C. Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781728148847

Dynamic partial reconfiguration (DPR) allows parts of an FPGA to be reprogrammed at runtime (i.e., repurposed). though DPR has been supported by commercial devices and tools for more than a decade, it has been underutilized, perhaps, due to a shortage of demonstrated use-cases and quantified benefits over static FPGA mapping (without DPR). In this paper, we quantify the benefits of dynamic FPGA mapping (with DPR) over traditional static FPGA mapping for two vision applications deployed on systems with area/device cost, power or energy constraints (i.e., smart car and smart robot). In both applications, the FPGA needs to accelerate multiple tasks at 60 fps. However, all tasks are not required at the same time. In this work, instead of mapping all tasks statically on a large FPGA, the set of tasks needed at a given time is (1) repurposed on a smaller FPGA and (2) still meets the functional and performance requirements (i.e., 60 fps). In the two application examples, we show that dynamic mapping on smaller FPGAs reduces logic resource utilization by up to 3.2x, device cost by up to 10x, and power and energy consumption by up to 30% in comparison with static mapping on larger FPGAs. these benefits are crucial for applications deployed on systems where reducing area/device cost, power and energy is as important as meeting performance requirement.

关键词： field programmable gate arrays Task analysis Acceleration Runtime Dynamic scheduling Navigation Libraries

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An Embedded Digital Multi-channel Analyzer for Radiation Detection Based on FPGA 7th

An Embedded Digital Multi-channel Analyzer for Radiation Det...

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7th EAI international conference on Industrial Networks and Intelligent Systems, INISCOM 2021

作者： Trinh, Quang-Kien Trinh, Van-Ninh Le, thanh-Bang Dinh, Tien-Hung Cao, Van-Hiep Le Quy Don Technical University Hanoi Viet Nam Military Institute of Chemistry and Environment/High Command of Chemical Hanoi Viet Nam

ISBN: (纸本)9783030774233

In recent years, digital processing algorithms have been widely applied in spectrum processing applications. Besides, FPGA technology, thanks to its undeniable advantages in flexibility, high integration, and cost-effectiveness, is seriously considered as a practical platform for the realization of embedded digital signal processing (DSP) systems. this work conducts a study on the practical implementation of Digital Multi-channel Analyzer (DMCA) based on reconfigurable hardware (FPGA). We proposed a modular reconfigurable DMCA design that is ready to be integrated into portable radiation detecting equipment and is still capable to handle high-speed signal sampling as well as could be extended to further functions such as remote sensing and classifying. this module could be integrated into the real-time radiation monitoring system. the algorithms of pulse shaping filter, detecting peaks and spectrum histogram processing are optimized and implemented entirely using available FPGA logic resources. the design is experimentally verified in a system using Lanthanum Bromide Scintillation Radiation LaBr3(Ce) detector. the results are compared with commercial products (DSPEC of ORTEC), where isotopes 137Cs and 60Co gamma-ray spectra show that its performance partially is superior to the DSPEC in terms of full width at half maximum (FWHM), received and lost count rate, integral nonlinearity. this prototype system is highly promising for the multi-DMCA system in considering performance, cost, and form factors. Regarding resource utilization and performance, the whole design utilizes only 5% LEs, 24% memory resources of 10M50SAE144I7G FPGA from Intel and the DMCA core is capable to handle up to 97 MSPS sampling rates. © 2021, ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering.

关键词： field programmable gate arrays (FPGA)

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Area Optimized Hardware Architecture of Piccolo-80 Lightweight Block Cipher 5th

Area Optimized Hardware Architecture of Piccolo-80 Lightweig...

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5th international conference on Microelectronics, Computing and Communication Systems, MCCS 2020

作者： Mishra, Shubham Mishra, Zeesha Acharya, Bibhudendra Department of Electronics and Communication National Institute of Technology Raipur CG492010 India

ISBN: (纸本)9789811602740

Lightweight cryptography is a field of cryptography where implementation for resource constrained devices are in big demand. Piccolo is an ultra-lightweight block cipher having block size of 64-bit and key size of 80-bit and 128-bit. Compact implementations becomes more important when they can provide sufficient security without compromise in performance. In this paper an efficient architecture for Piccolo-80 cipher have been proposed. this cipher requires extreamely low area in hardware implementation, and hence it is useful in RFID applications. Piccolo with its proposed architecture has been implemented on various platforms of *** proposed work shows 112% improvement in terms of area and 17.65% better results in terms of efficiency. Different devices of Virtex and Spartan have been used to get the results. © 2021, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： field programmable gate arrays (FPGA)

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Finding a Needle in the Haystack of Hardened Interconnect Patterns 29

Finding a Needle in the Haystack of Hardened Interconnect Pa...

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29th international conference on field-programmable logic and applications (FPL)

作者： Nikolic, Stefan Zgheib, Grace Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Intel Corp San Jose CA USA

ISBN: (纸本)9781728148847

Circuits naturally exhibit recurring patterns of local interconnect. Hardening those patterns when designing field programmable Gate Array (FPGA) clusters can both eliminate slow programmable connections from the critical path and remove the need for transistors to implement them. While we may be able to manually design such clusters, based on intuition and observations, such an endeavour will always leave us in doubt whether we have used the potential of cheap and fast hardened connections to the fullest. On the other hand, since there are similar to 10(7) possible patterns of interconnect among only eight 5-input Look-Up Tables (LUTs), even without considering the possibilities for enforcing input sharing, performing an exhaustive exploration of the design space seems like a task as daunting as finding a needle in a haystack. Despite their enormous sizes, design spaces spanned by such cluster architectures are very well structured. In this paper, we leverage that structure to limit the search to only those points of the space that may perform better than any chosen reference. We demonstrate the usefulness of our techniques by narrowing the space spanned by five 5-LUT structures from hundreds of millions to a set of 261 structures that achieve >= 80% utilization on a set of standard benchmarks, while requiring only 12 external inputs. We believe that the exploration techniques presented here are an important step towards truly exploiting the potentials of hardening programmable connections.

关键词： Table lookup Orbits Delays Integrated circuit interconnections Kernel field programmable gate arrays Standards

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A Flexible Design Automation Tool for Accelerating Quantized Spectral CNNs 29

A Flexible Design Automation Tool for Accelerating Quantized...

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29th international conference on field-programmable logic and applications (FPL)

作者： Rajat, Rachit Zeng, Hanqing Prasanna, Viktor Univ Southern Calif Los Angeles CA 90007 USA

ISBN: (纸本)9781728148847

CNNs have proven to be extremely powerful in various computer vision applications. To alleviate the computation burden and improve hardware efficiency, low-complexity convolution algorithms (e.g., spectral convolution) and data quantization schemes have been implemented on FPGAs. However, to translate the reduced algorithm complexity into improved hardware performance, we need significant manual tuning of mapping parameters specific to the CNN model and the target FPGA device. We propose a flexible tool to automate the process of generating high throughput accelerators for quantized, spectral CNNs. the tool takes as input high level specification of the CNN model, the data quantization scheme and the target hardware architecture. It outputs synthesizable Verilog after fast exploration of the complete design space. Our tool is flexible in three dimensions: 1) data representation, 2) FPGA architecture, and 3) CNN models. To support arbitrary quantization bit width, we propose a resource-efficient multiplier design, which uses the fixed, high bit-width DSPs to implement various low bit-width complex multiplications needed in spectral CNNs. To support FPGAs with limited on-chip memory, we propose a systolic array-based architecture for spectral convolution, which exploits high computation parallelism in DSPs without stressing BRAM resources. To support CNNs with various layer parameters, we tile and permute data blocks to saturate the communication and computation capacity. Finally, we propose a fast design space exploration algorithm to complete the end-to-end Verilog generation. the whole design space exploration and verilog generation takes less than 1 second on an Intel Core i5 laptop. We perform evaluation on Stratix-10 and Stratix-V FPGAs, using AlexNet and VGG16. the generated accelerators achieve 2x to 4x higher throughput than state-of-the-art, for 8-bit and 16-bit data quantization.

关键词： Tools field programmable gate arrays Quantization (signal) Convolution Hardware throughput Computer architecture

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Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA 29

Hybrid Dot-Product Calculation for Convolutional Neural Netw...

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29th international conference on field-programmable logic and applications (FPL)

作者： Vestias, Mario Duarte, Rui Policarpo de Sousa, Jose T. Neto, Horacio Inst Politecn Lisboa INESC ID ISEL Lisbon Portugal Univ Lisbon INESC ID Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9781728148847

Convolutional Neural Networks (CNN) are quite useful in edge devices for security, surveillance, and many others. Running CNNs in embedded devices is a design challenge since these models require high computing power and large memory storage. Data quantization is an optimization technique applied to CNN to reduce the computing and memory requirements. the method reduces the number of bits used to represent weights and activations, which consequently reduces the size of operands and of the memory. the method is more effective if hybrid quantization is considered in which data in different layers may have different bit widths. this article proposes a new hardware module to calculate dot-products of CNNs with hybrid quantization. the module improves the implementation of CNNs in low density FPGAs, where the same module runs dot-products of different layers with different data quantizations. We show implementation results in ZYNQ7020 and compare with state-of-the-art works. Improvements in area and performance are achieved with the new proposed module.

关键词： Deep learning Convolutional Neural Network Embedded computing Hybrid quantization field-programmable Gate Array

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Hardware Accelerator for Dual Standard Deblocking Filter

Hardware Accelerator for Dual Standard Deblocking Filter

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international conference on VLSI Design

作者： P. Saravanan B. Syndia Priyadarshini P. Vignesh Kanna P. Vaishnavi PSG College of Technology Coimbatore India

Advanced Video Coding (AVC) also known as H.264 is a popular video coding standard which is used in many image processing applications. In order to fulfill the increasing demand for better video quality with less complex designs, High Efficiency Video Coding (HEVC) also known as H.265 came into picture. HEVC provides better quality with half the bit rate required for processing in comparison with AVC. In case of AVC, the design of deblocking filter is more complex due to the filtering decisions, whereas HEVC is less complex and also supports parallel processing. As there is a need for high throughput and less complex deblocking filter, a novel dual standard deblocking filter is proposed in this work which supports both AVC and HEVC. In particular, a novel filtering order which enables four edges to be processed simultaneously has been proposed for both AVC and HEVC. For AVC, the proposed design takes 18 clock cycles to process a 16 × 16 macroblock and for HEVC standard, the proposed design takes 12 clock cycles to process a 16 × 16 coding transform unit (CTU). In addition to this, the proposed design supports parallel processing concept in HEVC. the proposed design is synthesized using Xilinx ISE 14.7 and is mapped to xc5vlx30-1ff324 Virtex-5 field programmable gate array (FPGA). thus it helps in increasing the execution speed of the design and it is also noted that there is a reduction in number of clock cycles needed for processing when compared with the existing architectures. the physical implementation of the proposed architecture is also carried out using Semiconductor Lab (SCL) 180 nm process node.

关键词： Filtering Transforms Parallel processing Very large scale integration throughput Standards field programmable gate arrays

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