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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

共 2124 条记录，以下是291-300 订阅

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FPGA-based Design of a Self-checking TMR Voter 27

FPGA-based Design of a Self-checking TMR Voter

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27th international conference on field programmable logic and applications (FPL)

作者： Afzaal, Umar Lee, Jeong A. Chosun Univ Dept Comp Engn Gwangju South Korea

ISBN: (纸本)9789090304281

the most common error mitigation scheme used for hardening designs against radiation-induced upsets on FPGAs is Triple Modular Redundancy (TMR). In a TMR system, there are three copies of a module and voting circuits that mask errors by voting for the majority. there are several types of voting circuits which can be classified based on their insertion sites in the design, functionality or the type of data structure to be mitigated. these voters are mostly built from Look-up Tables (LUTs) but these voters just like the design that is hardened by applying TMR are also susceptible to radiation-induced effects. In this paper, we present the design of a self-checking LUT based 1-bit voter intended for those sites where a TMR system reduces to a duplex or a simplex system. Voters on these sites make a single point of failure and the proposed design avoids this situation by attaching multiple voter redundancies to the same output. the operation of the proposed voter has been verified through its hardware implementation and timing simulation.

关键词： Tunneling magnetoresistance Table lookup field programmable gate arrays Switches Redundancy Integrated circuit reliability

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Measure Twice and Cut Once: Robust Dynamic Voltage Scaling for FPGAs 26

Measure Twice and Cut Once: Robust Dynamic Voltage Scaling f...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Zhao, Shuze Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9782839918442

Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe V-dd depends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. this CT is used to scale V-dd while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.

关键词： field programmable gate arrays (FPGA)

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H2PIPE: High throughput CNN Inference on FPGAs with High-Bandwidth Memory 34

H2PIPE: High Throughput CNN Inference on FPGAs with High-Ban...

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34th international conference on field-programmable logic and applications (FPL)

作者： Doumet, Mario Stant, Marius Hall, Mathew Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Microsoft Corp Redmond WA 98052 USA Vector Inst Toronto ON Canada

ISBN: (纸本)9798331530082;9798331530075

Convolutional Neural Networks (CNNs) combine large amounts of parallelizable computation with frequent memory access. field programmable Gate Arrays (FPGAs) can achieve low latency and high throughput CNN inference by implementing dataflow accelerators that pipeline layer-specific hardware to implement an entire network. By implementing a different processing element for each CNN layer, these layer-pipelined accelerators can achieve high compute density, but having all layers processing in parallel requires high memory bandwidth. Traditionally this has been satisfied by storing all weights on chip, but this is infeasible for the largest CNNs, which are often those most in need of acceleration. In this work we augment a state-of-the-art dataflow accelerator (HPIPE) to leverage both High-Bandwidth Memory (HBM) and on-chip storage, enabling high performance layer-pipelined dataflow acceleration of large CNNs. Based on profiling results of HBM's latency and throughput against expected address patterns, we develop an algorithm to choose which weight buffers should be moved off chip and how deep the on-chip FIFOs to HBM should be to minimize compute unit stalling. We integrate the new hardware generation within the HPIPE domain-specific CNN compiler and demonstrate good bandwidth efficiency against theoretical limits. Compared to the best prior work we obtain speed-ups of at least 19.4x, 5.1x and 10.5x on ResNet-18, ResNet-50 and VGG-16 respectively.

关键词： field programmable gate arrays (FPGA)

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A Technology Mapper for Depth-Constrained FPGA logic Cells 25

A Technology Mapper for Depth-Constrained FPGA Logic Cells

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25th international conference on field programmable logic and applications

作者： Jiang, Zhenghong Zgheib, Grace Lin, Colin Yu Novo, David Huang, Zhihong Yang, Liqun Yang, Haigang Ienne, Paolo Chinese Acad Sci Inst Elect Syst Programmable Chip Res Dept Beijing Peoples R China Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781467381239

In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. these representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of field programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naively adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. the key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output;on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences;the result is a highly versatile mapper-thus enabling further research in these new architectures-with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).

关键词： field programmable gate arrays (FPGA)

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Improving external memory access for avalon systems on programmable chips

Improving external memory access for avalon systems on progr...

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17th international conference on field programmable logic and applications

作者： Eeckhaut, Hendrik Christiaens, Mark Faes, Phillipe Stroobandt, Dirk Univ Ghent ELIS Parallel Informat Syst B-9000 Ghent Belgium

ISBN: (纸本)9781424410590

In this paper we present a new hardware design pattern for improving memory transfers to external dynamic memory in Altera's SOPC-builder tool by reusing the standard DMA IP core for all bulk memory transfers without the need for a CPU. the presented approach doubles the data throughput without the need for extra system resources. In addition it is more effective for choosing optimal clock settings for the different components of the system on a programmable chip. the benefits and limitations of this new approach are illustrated with a real world example: a bitplane assembler for scalable wavelet based video. the new design is. times faster with the same clock settings as the original design and uses about 100 logic elements less. Applying our new approach also has a positive impact on energy consumption.

关键词： Clocks

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A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs 25

A portable open-source controller for safe Dynamic Partial R...

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25th international conference on field programmable logic and applications

作者： Di Carlo, Stefano Prinetto, Paolo Trotta, Pascal Andersson, Jan Politecn Torino Dip Automat & Informat Turin Italy Cobham Gaisler AB Gothenburg Sweden

ISBN: (纸本)9781467381239

thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based field programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of highly reliable systems. In this context, Dynamic Partial Reconfiguration (DPR) is far from being widely adopted due to the additional complexity introduced during the hardware design phase, and the dependability issues related to the FPGA reconfiguration process itself. this paper presents a portable open-source controller for safely enabling self dynamic and partial reconfiguration of systems implemented on Xilinx FPGAs. the controller embeds configurable error detection and correction circuitry that enables a safe DPR by monitoring for partial bitstreams data errors. Experiments highlight the high performances achieved and the limited hardware resources needed to implement it on different devices. the HDL source code has been made available through the popular open-source Cobham Gaisler GRLIB IP-cores library.(1)

关键词： hardware resource Reconfiguration field programmable gate arrays open source HIGH-PERFORMANCE Controllers error detection and correction dial pulse receiver

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Case for Fast FPGA Compilation using Partial Reconfiguration 28

Case for Fast FPGA Compilation using Partial Reconfiguration

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28th international conference on field programmable logic and applications (FPL)

作者： Park, Dongjoon Xiao, Yuanlong Magnezi, Nevo DeHon, Andre Univ Penn Dept Elect & Syst Engn Philadelphia PA 19104 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Despite the FPGA's advantages over other hardware platforms, long compilation time prevents FPGA engineers from efficiently exploring the design space and discourages new users who want to quickly iterate for debugging. To reduce compilation time, this work adopts a divide-and-conquer approach using Partial Reconfiguration with a Packet-Switched Fat-Tree network. Partially reconfigured leaves in the packet-switched network are independent from each other and can be compiled separately in parallel. Also, when a minor fix is required to a bitstream, only the corresponding leaves need to be incrementally compiled. Preliminary experimental evidence from our work-in-progress effort illustrates how a 30 minute full-chip compile time can be reduced to 7 minutes.

关键词： field programmable gate arrays Table lookup Overlay networks Runtime Tools Hardware Standards

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F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network 27

F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network

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27th international conference on field programmable logic and applications (FPL)

作者： Fan, Hongxiang Niu, Xinyu Liu, Qiang Luk, Wayne Tianjin Univ Sch Microelect Tianjin Peoples R China Imperial Coll London Dept Comp Sch Engn London England

ISBN: (纸本)9789090304281

In recent years, 3-dimension convolutional neural networks (3D CNNs) have been widely used for video analysis, 3-dimension geometric data and medical image diagnosis. While conventional CNNs are computationally intensive, 3D CNNs push the computational requirements into another level, since each computation depends on multiple image frames. this paper describes a novel hardware architecture for a 3D convolutional neural network, and design strategies to resolve memory usage and bandwidth limitations. the proposed architecture F-C3D is implemented on zc706 at 172MHz, showing 231 times speed up compared with software implementation on 1 GHz ARM CPU, 7.4 times speed up on 3.07 GHz Intel CPU and nearly 10 times lower power consumption than GPU.

关键词： three-dimensional displays Convolution Two dimensional displays Kernel Computer architecture Hardware field programmable gate arrays

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ENHANCING SECURITY OF RING OSCILLATOR-BASED TRNG IMPLEMENTED IN FPGA

ENHANCING SECURITY OF RING OSCILLATOR-BASED TRNG IMPLEMENTED...

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18th international conference on field programmable and logic applications

作者： Fischer, Viktor Bernard, Florent Bochard, Nathalie Varchola, Michal Univ St Etienne CNRS UMR 5516 Lab Hubert Curien 18 Rue Prof Lauras St Etienne France Tech Univ Kosice Dept Elect & Multimedia Commun Kosice Slovakia

ISBN: (纸本)9781424419609

Random number generators are one of basic cryptographic primitives used in cryptographic protocols. Most of true random number generators in field programmable Gate Arrays (FPGAs) employ the timing jitter from ring oscillator clocks as a source of randomness. the paper analyses the jitter generated in ring oscillators and it uses a simple physical model of jitter sources to show that the random jitter accumulates slower than the global and manipulable deterministic jitter. this fact, which can be used to attack generators, is not considered even in most recent designs considered to be secure. the paper proposes simple but efficient countermeasure against these attacks. the method is validated using the proposed behavioral VHDL model and it is shown to be efficient also in hardware.

关键词： field programmable gate arrays (FPGA)

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One Size Does Not Fit All: Implementation Trade-Offs for Iterative Stencil Computations on FPGAs 27

One Size Does Not Fit All: Implementation Trade-Offs for Ite...

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27th international conference on field programmable logic and applications (FPL)

作者： Deest, Gael Yuki, Tomofumi Rajopadhye, Sanjay Derrien, Steven Univ Rennes 1 IRISA Rennes France INRIA IRISA Rocquencourt France Colorado State Univ Ft Collins CO 80523 USA

ISBN: (纸本)9789090304281

Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. the best architecture depends on many factors such as the target platform, off-chip memory bandwidth, problem size, and performance requirements. We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. the optimal choice depends on problem sizes and performance goals.

关键词： field programmable gate arrays System-on-chip Pipeline processing Memory management Acceleration Bandwidth Hardware

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