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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"
2124 条 记 录,以下是291-300 订阅
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FPGA-based Design of a Self-checking TMR Voter  27
FPGA-based Design of a Self-checking TMR Voter
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27th international conference on field programmable logic and applications (FPL)
作者: Afzaal, Umar Lee, Jeong A. Chosun Univ Dept Comp Engn Gwangju South Korea
the most common error mitigation scheme used for hardening designs against radiation-induced upsets on FPGAs is Triple Modular Redundancy (TMR). In a TMR system, there are three copies of a module and voting circuits ... 详细信息
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Measure Twice and Cut Once: Robust Dynamic Voltage Scaling for FPGAs  26
Measure Twice and Cut Once: Robust Dynamic Voltage Scaling f...
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26th international conference on field-programmable logic and applications (FPL)
作者: Ahmed, Ibrahim Zhao, Shuze Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada
Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to ch... 详细信息
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H2PIPE: High throughput CNN Inference on FPGAs with High-Bandwidth Memory  34
H2PIPE: High Throughput CNN Inference on FPGAs with High-Ban...
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34th international conference on field-programmable logic and applications (FPL)
作者: Doumet, Mario Stant, Marius Hall, Mathew Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Microsoft Corp Redmond WA 98052 USA Vector Inst Toronto ON Canada
Convolutional Neural Networks (CNNs) combine large amounts of parallelizable computation with frequent memory access. field programmable Gate Arrays (FPGAs) can achieve low latency and high throughput CNN inference by... 详细信息
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A Technology Mapper for Depth-Constrained FPGA logic Cells  25
A Technology Mapper for Depth-Constrained FPGA Logic Cells
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25th international conference on field programmable logic and applications
作者: Jiang, Zhenghong Zgheib, Grace Lin, Colin Yu Novo, David Huang, Zhihong Yang, Liqun Yang, Haigang Ienne, Paolo Chinese Acad Sci Inst Elect Syst Programmable Chip Res Dept Beijing Peoples R China Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland
In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. these representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspir... 详细信息
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Improving external memory access for avalon systems on programmable chips
Improving external memory access for avalon systems on progr...
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17th international conference on field programmable logic and applications
作者: Eeckhaut, Hendrik Christiaens, Mark Faes, Phillipe Stroobandt, Dirk Univ Ghent ELIS Parallel Informat Syst B-9000 Ghent Belgium
In this paper we present a new hardware design pattern for improving memory transfers to external dynamic memory in Altera's SOPC-builder tool by reusing the standard DMA IP core for all bulk memory transfers with... 详细信息
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A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs  25
A portable open-source controller for safe Dynamic Partial R...
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25th international conference on field programmable logic and applications
作者: Di Carlo, Stefano Prinetto, Paolo Trotta, Pascal Andersson, Jan Politecn Torino Dip Automat & Informat Turin Italy Cobham Gaisler AB Gothenburg Sweden
thanks to their flexibility, increasing performances and low Non-Recurrent Engineering costs, SRAM-based field programmable Gate Array (FPGA) devices often represent the preferred platforms for the final deployment of... 详细信息
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Case for Fast FPGA Compilation using Partial Reconfiguration  28
Case for Fast FPGA Compilation using Partial Reconfiguration
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28th international conference on field programmable logic and applications (FPL)
作者: Park, Dongjoon Xiao, Yuanlong Magnezi, Nevo DeHon, Andre Univ Penn Dept Elect & Syst Engn Philadelphia PA 19104 USA
Despite the FPGA's advantages over other hardware platforms, long compilation time prevents FPGA engineers from efficiently exploring the design space and discourages new users who want to quickly iterate for debu... 详细信息
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F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network  27
F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network
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27th international conference on field programmable logic and applications (FPL)
作者: Fan, Hongxiang Niu, Xinyu Liu, Qiang Luk, Wayne Tianjin Univ Sch Microelect Tianjin Peoples R China Imperial Coll London Dept Comp Sch Engn London England
In recent years, 3-dimension convolutional neural networks (3D CNNs) have been widely used for video analysis, 3-dimension geometric data and medical image diagnosis. While conventional CNNs are computationally intens... 详细信息
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ENHANCING SECURITY OF RING OSCILLATOR-BASED TRNG IMPLEMENTED IN FPGA
ENHANCING SECURITY OF RING OSCILLATOR-BASED TRNG IMPLEMENTED...
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18th international conference on field programmable and logic applications
作者: Fischer, Viktor Bernard, Florent Bochard, Nathalie Varchola, Michal Univ St Etienne CNRS UMR 5516 Lab Hubert Curien 18 Rue Prof Lauras St Etienne France Tech Univ Kosice Dept Elect & Multimedia Commun Kosice Slovakia
Random number generators are one of basic cryptographic primitives used in cryptographic protocols. Most of true random number generators in field programmable Gate Arrays (FPGAs) employ the timing jitter from ring os... 详细信息
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One Size Does Not Fit All: Implementation Trade-Offs for Iterative Stencil Computations on FPGAs  27
One Size Does Not Fit All: Implementation Trade-Offs for Ite...
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27th international conference on field programmable logic and applications (FPL)
作者: Deest, Gael Yuki, Tomofumi Rajopadhye, Sanjay Derrien, Steven Univ Rennes 1 IRISA Rennes France INRIA IRISA Rocquencourt France Colorado State Univ Ft Collins CO 80523 USA
Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. the best architecture depends on many factors such as the target platform,... 详细信息
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