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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"
2124 条 记 录,以下是301-310 订阅
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A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2)  28
A Demonstration of FPGA-based You Only Look Once version2 (Y...
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28th international conference on field programmable logic and applications (FPL)
作者: Nakahara, Hiroki Shimoda, Masayuki Sato, Shimpei Tokyo Inst Technol Tokyo Japan
We implement the YOLO (You only look once) object detector on an FPGA, which is faster and has higher accuracy. It is based on the convolutional deep neural network (CNN), and it is a dominant part of both the perform... 详细信息
来源: 评论
HOW FAST IS AN FPGA IN IMAGE PROCESSING?
HOW FAST IS AN FPGA IN IMAGE PROCESSING?
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18th international conference on field programmable and logic applications
作者: Saegusa, Takashi Maruyama, Tsutomu Yamaguchi, Yoshiki Univ Tsukuba Tsukuba Ibaraki 3058573 Japan
In image processing, FPGAs have shown very high performance in spite of their low operational frequency. this high performance comes from (1) high parallelism in applications in image processing, (2) high ratio of 8 b... 详细信息
来源: 评论
Neural Network Overlay Using FPGA DSP Blocks  29
Neural Network Overlay Using FPGA DSP Blocks
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29th international conference on field-programmable logic and applications (FPL)
作者: Ioannou, Lenos Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England
With the increasing wider application of neural networks, there has been significant focus on accelerating this class of computations. Larger, more complex networks are being proposed in a variety of domains, requirin... 详细信息
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Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model  28
Deterministic Parallel Routing for FPGAs based on Galois Par...
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28th international conference on field programmable logic and applications (FPL)
作者: Moctar, Yehdhih Stojilovic, Mirjana Brisk, Philip IBM Res Austin TX 78758 USA Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Lausanne Switzerland Univ Calif Riverside Riverside CA 92521 USA
this paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel;and (2) routing one ... 详细信息
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A Demonstration of the GUINNESS: A GUI based Neural NEtwork SyntheSizer for an FPGA  27
A Demonstration of the GUINNESS: A GUI based Neural NEtwork ...
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27th international conference on field programmable logic and applications (FPL)
作者: Nakahara, H. Yonekawa, H. Fujii, T. Shimoda, M. Sato, S. Tokyo Inst Technol Tokyo Japan
the GUINNESS is a tool flow for the deep neural network toward FPGA implementation [3,4,5] based on the GUI (Graphical User Interface) including both the binarized deep neural network training on GPUs and the inferenc... 详细信息
来源: 评论
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement  29
A Deep Learning Framework to Predict Routability for FPGA Ci...
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29th international conference on field-programmable logic and applications (FPL)
作者: Alhyari, A. Shamli, A. Abuwaimer, Z. Areibi, S. Grewal, G. Univ Guelph Sch Engn Guelph ON Canada Univ Guelph Sch Comp Sci Guelph ON Canada
the ability to accurately and efficiently estimate the routability of a circuit based on its placement is one of the most challenging and difficult tasks in the field programmable Gate Array (FPGA) flow. In this paper... 详细信息
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Fault tolerance and reliability in field-programmable gate arrays
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IET COMPUTERS AND DIGITAL TECHNIQUES 2010年 第3期4卷 196-210页
作者: Stott, E. Sedcole, P. Cheung, P. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England
Reduced device-level reliability and increased within-die process variability will become serious issues for future field-programmable gate arrays (FPGAs), and will result in faults developing dynamically during the l... 详细信息
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A power estimation model for an FPGA-based softcore processor
A power estimation model for an FPGA-based softcore processo...
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17th international conference on field programmable logic and applications
作者: Zipf, Peter Hinkelmann, Heiko Deng, Lei Glesner, Manfred Blume, Holger Noll, Tobias G. Tech Univ Darmstadt Inst Microelect Syst Darmstadt Germany Rhein Westfal TH Aachen Elect Engn & Comp syst Aachen Germany
We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. this technique enables the estimation of... 详细信息
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Equivalence verification of FPGA and structured ASIC implementations
Equivalence verification of FPGA and structured ASIC impleme...
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17th international conference on field programmable logic and applications
作者: Pistorius, Joachim Hutton, Mike Schleicher, Jay Lotov, Mihail Julias, Enoch tharmalingam, Kumara Altera Corp San Jose CA 95134 USA
Structured ASICs have recently emerged as a mid-way between cell-based ASICs with high NRE costs and FPGAs with high unit costs. though the structured ASIC fabric attacks mask and other fixed cost it does not solve ve... 详细信息
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A Survey on FPGA Virtualization  28
A Survey on FPGA Virtualization
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28th international conference on field programmable logic and applications (FPL)
作者: Vaishnav, Anuj Khoa Dang Pham Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England
FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for eff... 详细信息
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