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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

共 2124 条记录，以下是301-310 订阅

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Configurable and Scalable Belief Propagation Accelerator for Computer Vision 26

Configurable and Scalable Belief Propagation Accelerator for...

引用

26th international conference on field-programmable logic and applications (FPL)

作者： Choi, Jungwook Rutenbar, Rob A. IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA Univ Illinois Dept Comp Sci 1304 W Springfield Ave Urbana IL 61801 USA

ISBN: (纸本)9782839918442

We demonstrate a novel FPGA-based accelerator architecture that can tackle a range of standard computer vision (CV) problems, with scalable performance and attractive speedups. the architecture relies on multiple pipelined processing elements (PEs) that can be configured to support various belief propagation (BP) settings for different CV tasks. Inside each PE, innovative implementation of Jump Flooding for efficient computation of BP solves the core configurability challenge. A novel block-parallel memory interface supports parallelization by distributing BP inference workloads across the PEs. Experimental results demonstrate that our accelerator achieves scalable performance with 11-41x speedup over standard sequential CPU implementations across a subset of well-known Middlebury and OpenGM benchmarks, with no compromise in quality of inference results. To the best of our knowledge, this is the first FPGA hardware implementation of BP capable of running a range of standard CV benchmarks with significant speedups.

关键词： Belief propagation computer vision Markov random field field programmable gate arrays

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ENHANCEMENTS TO FPGA DESIGN MEthODOLOGY USING STREAMING

ENHANCEMENTS TO FPGA DESIGN METHODOLOGY USING STREAMING

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19th international conference on field programmable logic and applications

作者： Plavec, Franjo Vranesic, Zvonko Brown, Stephen Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781424438914

Capacity of FPGAs has grown significantly, leading to increased complexity of designs targeting these chips. Traditional FPGA design methodology using HDLs is no longer sufficient and new methodologies are being sought. An attractive possibility is to use streaming languages. Streaming languages group data into streams, which are processed by computational nodes called kernels. they are suitable for implementation in FPGAs because they expose parallelism, which can be exploited by implementing the application in FPGA logic. Designers can express their designs in a streaming language and target FPGAs without needing a detailed understanding of digital logic design. In this paper we show how the Brook streaming language can be used to simplify design for FPGAs, while providing reasonable performance compared to other methodologies. We show that throughput of streaming applications can be increased through automatic kernel replication. Using our compiler, the FPGA designer can trade off FPGA area and performance by changing the amount of kernel replication. We describe the details of our compiler and present performance and area of a set of benchmarks. We found that throughput scales well with increased replication for most applications.

关键词： field programmable gate arrays (FPGA)

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Optimal Random Sampling Based Path Planning on FPGAs 26

Optimal Random Sampling Based Path Planning on FPGAs

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26th international conference on field-programmable logic and applications (FPL)

作者： Xiao, Size Postula, Adam Bergmann, Neil Univ Queensland Sch Informat Technol & Elect Engn Brisbane Qld 4072 Australia

ISBN: (纸本)9782839918442

Random sampling based path planning algorithms have shown their high efficiency in robotics, navigation and related fields. the Rapidly-Exploring Random Trees (RRT) is the typical method and works well in a variety of applications. Due to the sub-optimal issue of original RRT, the recent algorithm, known as RRT*, significantly improves the optimality of solution by adding the "cost review" procedure. However, the original RRT experiences the bottle neck of complicated iterations and it becomes worse in RRT*. this paper presents the developed hardware architecture for RRT*, which fully exploits the parallel potential of algorithm. Unlike the sequential execution in software, the "exploration" and "review" are identified as independent processes and executed in parallel. For the complicated operation of inserting vertexes, one pipelined Kd-tree constructor is designed to fast rebuild the tree when new vertex generated. Furthermore, to speed up the near neighbors and nearest neighbor searching, the vertexes are stored in separate Kd-trees so that the search processes can be carried out concurrently in each data tree. this work explores the possible and power-efficient RRT* hardware architecture on FPGAs compared to PC implementation.

关键词： field programmable gate arrays (FPGA)

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Static Hardware Task Placement on Multi-Context FPGA Using Hybrid Genetic Algorithm 25

Static Hardware Task Placement on Multi-Context FPGA Using H...

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25th international conference on field programmable logic and applications

作者： Liang, Hao Sinha, Sharad Warrier, Rakesh Zhang, Wei Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781467381239

field programmable Gate Arrays (FPGAs) are becoming pervasive in various kinds of computationally demanding applications. Working in a tightly coupled processor-coprocessor architecture, FPGAs are often anticipated to accelerate multiple fine-grained or coarse-grained tasks simultaneously. Single-context FPGAs are commonly used in such systems. With the recent development of emerging memory technologies, multicontext FPGAs that support dynamic reconfiguration with high-density non-volatile memories become feasible. Compared to single-context FPGAs, multi-context FPGAs are able to accelerate significantly more tasks with only moderate area and power overhead. However, the best way to utilize the computation capacity advantage of multi-context FPGAs for hardware task mapping remains an interesting and unexploited problem. In this paper, we first propose the framework of a processor-coprocessor architecture with multi-context FPGA as the coprocessor for multiple-task acceleration. Under the framework, a hybrid placement strategy based on genetic and greedy algorithms is proposed to efficiently place a set of tasks onto the multi-context FPGA to achieve the best logic capacity utilization. Experiments on real and synthetic benchmarks demonstrate the efficiency of the proposed algorithm compared with other general approaches.

关键词： field programmable gate arrays (FPGA)

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FPGA ACCELERATION OF QUASI-MONTE CARLO IN FINANCE

FPGA ACCELERATION OF QUASI-MONTE CARLO IN FINANCE

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18th international conference on field programmable and logic applications

作者： Woods, Nathan A. VanCourt, Tom XtremeData Inc Schaumburg IL 60173 USA Altera Corp Santa Cruz CA 95134 USA

ISBN: (纸本)9781424419609

Today, quasi-Monte Carlo (QMC) methods are widely used in finance to price derivative securities. the QMC approach is popular because for many types of derivatives it yields an estimate of the price, to a given accuracy, faster than other competitive approaches, like Monte Carlo (MC) methods. the calculation of the large number of underlying asset pathways consumes a significant portion of the overall run-time and energy of modem QMC derivative pricing simulations. therefore, we present an FPGA-based accelerator for the calculation of asset pathways suitable for use in the QMC pricing of several types of derivative securities. Although this implementation uses constructs (recursive algorithms and double-precision floating point) not normally associated with successful FPGA computing, we demonstrate performance in excess of 50x that of a 3 GHz multi-core processor.

关键词： field programmable gate arrays (FPGA)

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PERFORMANCE COMPARISON OF FPGA, GPU AND CPU IN IMAGE PROCESSING

PERFORMANCE COMPARISON OF FPGA, GPU AND CPU IN IMAGE PROCESS...

引用

19th international conference on field programmable logic and applications

作者： Asano, Shuichi Maruyama, Tsutomu Yamaguchi, Yoshiki Univ Tsukuba Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9781424438914

Many applications in image processing have high inherent parallelism. FPGAs have shown very high performance in spite of their low operational frequency by fully extracting the parallelism. In recent micro processors, it also becomes possible to utilize the parallelism using multi-cores which support improved SIMD instructions, though programmers have louse them explicitly to achieve high performance. Recent GPUs support a large number of cores, and have a potential for high performance in many applications. However, the cores are grouped, and data transfer between the groups is very limited. Programming tools for FPGA, SIMD instructions on CPU and a large number of cores on GPU have been developed, but it is still difficult to achieve high performance on these platforms. In this paper, we compare the performance of FPGA, GPU and CPU using three applications in image processing;two-dimensional filters, stereo-vision and k-means clustering, and make it clear which platform is faster under which conditions.

关键词： field programmable gate arrays (FPGA)

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SEPARABLE IMPLEMENTATION OF thE SECOND ORDER VOLTERRA FILTER (SOVF) IN XILINX VIRTEX-E FPGA

SEPARABLE IMPLEMENTATION OF THE SECOND ORDER VOLTERRA FILTER...

引用

18th international conference on field programmable and logic applications

作者： Al-Mistarihi, Mamoun F. Jordan Univ Sci & Technol Fac Engn Dept Elect Engn Irbid 22110 Jordan

ISBN: (纸本)9781424419609

Post-beamforming second order Volterra filter (SOVF) was previously introduced for decomposing the pulse echo ultrasonic radio-frequency (RF) signal into its linear and quadratic components. Using singular value decomposition (SVD), an optimal minimum-norm least squares algorithm for deriving the coefficients of the linear and quadratic kernels of the SOVF was developed and verified. the "Separable" implementation algorithm of a SOVF based on the eigenvalue decomposition (EVD) of the quadratic kernel was introduced and verified. In this paper, the "Separable" version of a Second Order Volterra filter is implemented in Xilinx Virtex-E FPGA. Parallel operation, efficient use of instructions per task, and data streaming capability of FPGA are identified. this implementation should allow for real-time implementation of quadratic filtering on commercial ultrasound scanners.

关键词： field programmable gate arrays (FPGA)

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USING 3D INTEGRATION TECHNOLOGY TO REALIZE MULTI-CONTEXT FPGAS

USING 3D INTEGRATION TECHNOLOGY TO REALIZE MULTI-CONTEXT FPG...

引用

19th international conference on field programmable logic and applications

作者： Cevrero, Alesandro Athanasopoulosi, Panagiotis Parandeh-Afshar, Hadi Skerlj, Maurizio Brisk, Philip Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Sch Engn CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781424438914

this paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. the DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes;the new configuration is loaded from the latch array into the FPGA in 60ns (5 cycles). the latency between reconfigurations, 8.42 mu s, is dominated by the time to read data from the DRAM into the latch array. We estimate that the DRAM can cache 289 FPGA contexts.

关键词： field programmable gate arrays (FPGA)

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AN FPGA-BASED IMPLEMENTATION OF thE MINRES ALGORIthM

AN FPGA-BASED IMPLEMENTATION OF THE MINRES ALGORITHM

引用

18th international conference on field programmable and logic applications

作者： Boland, David Constantinides, George A. Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (纸本)9781424419609

Due to continuous improvements in the resources available on FPGAs, it is becoming increasingly possible to accelerate floating point algorithms. the solution of a system of linear equations forms the basis of many problems in engineering and science, but its calculation is highly time consuming. the minimum residual algorithm (MINRES) is one method to solve this problem, and is highly effective provided the matrix exhibits certain characteristics. this paper examines an IEEE 754 single precision floating point implementation of the MINRES algorithm on an FPGA. It demonstrates that through parallelisation and heavy pipelining of all floating point components it is possible to achieve a sustained performance of up to 53 GFLOPS on the Virtex5-330T. this compares favourably to other hardware implementations of floating point matrix inversion algorithms, and corresponds to an improvement of nearly an order of magnitude compared to a software implementation.

关键词： field programmable gate arrays (FPGA)

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A NON-VOLATILE RUN-TIME FPGA USING thERMALLY ASSISTED SWITCHING MRAMS

A NON-VOLATILE RUN-TIME FPGA USING THERMALLY ASSISTED SWITCH...

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18th international conference on field programmable and logic applications

作者： Guillemenet, Yoann Torres, Lionel Sassatelli, Gilles Bruchon, Nicolas Hassoune, Ilham Univ Montpellier 2 CNRS LIRMM UMR F-34392 Montpellier 5 France

ISBN: (纸本)9781424419609

this paper describes the integration of a thermally assisted switching magnetic random access memory (TAS-MRAM) in FPGA design. the non-volatility of the latter is achieved through the use of magnetic tunneling junctions (MTJ) in the MRAM cell. A thermally assisted switching scheme is used to write data in the MTJ device, which helps to reduce power consumption during write operation in comparison to the writing scheme in classical MTJ device. Plus, the non-volatility of such a design should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM based FPGAs. A real time reconfigurable (RTR) micro-FPGA using TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

关键词： field programmable gate arrays (FPGA)

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