检索结果-内蒙古大学图书馆

28th international conference on field programmable logic and applications (FPL)

作者： Nakahara, Hiroki Shimoda, Masayuki Sato, Shimpei Tokyo Inst Technol Tokyo Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We implement the YOLO (You only look once) object detector on an FPGA, which is faster and has higher accuracy. It is based on the convolutional deep neural network (CNN), and it is a dominant part of both the performance and the area. It is widely used in the embedded systems, such as robotics, autonomous driving, security, and drones, all of which require high-performance and low-power consumption. A frame object detection problem consists of two problems: one is a regression problem to spatially separated bounding boxes, the second is the associated classification of the objects within realtime frame rate. We used the binary (1 bit) precision CNN for feature extraction and the half-precision (16 bit) precision CNN for both classification and localization. We implement a pipelined based architecture for the mixed-precision YOLOv2 on the Xilinx Inc. zcul02 board, which has the Xilinx Inc. Zynq Ultrascale+ MPSoC. the implemented object detector archived 35.71 frames per second (FPS), which is faster than the standard video speed (29.9 FPS). Compared with a CPU and a GPU, an FPGA based accelerator was superior in power performance efficiency. Our method is suitable for the frame object detector for an embedded vision system.

关键词： field programmable gate arrays Computer architecture Graphics processing units Detectors Feature extraction Training Neural networks

来源：评论

学校读者我要写书评

暂无评论

HOW FAST IS AN FPGA IN IMAGE PROCESSING?

HOW FAST IS AN FPGA IN IMAGE PROCESSING?

引用

18th international conference on field programmable and logic applications

作者： Saegusa, Takashi Maruyama, Tsutomu Yamaguchi, Yoshiki Univ Tsukuba Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9781424419609

In image processing, FPGAs have shown very high performance in spite of their low operational frequency. this high performance comes from (1) high parallelism in applications in image processing, (2) high ratio of 8 bit operations, and (3) a large number of internal memory banks on FPGAs which can be accessed in parallel. In the recent micro processors, it becomes possible to execute SIMD instructions on 128 bit data in one clock cycle. Furthermore, these processors support multi-cores and large cache memory which can hold all image data for each core. In this paper, we compare the performance of FPGAs with those processors using three applications in image processing;two-dimensional filters, stereo-vision and k-means clustering, and make it clear how fast is an FPGA in image processing, and how many hardware resources are required to achieve the performance.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Neural Network Overlay Using FPGA DSP Blocks 29

Neural Network Overlay Using FPGA DSP Blocks

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Ioannou, Lenos Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9781728148847

With the increasing wider application of neural networks, there has been significant focus on accelerating this class of computations. Larger, more complex networks are being proposed in a variety of domains, requiring more powerful computation platforms. the inherent parallelism and regularity of neural network structures means custom architectures can be adopted for this purpose. FPGAs have been widely used to implement such accelerators because of their flexibility, achievable performance, efficiency, and abundant peripherals. While platforms that utilize multicore CPUs and GPUs are also competitive, FPGAs offer superior energy efficiency, and a wider space of optimisations to enhance performance and efficiency. FPGAs are also more suitable for performing such computations at the edge, where multicore CPUs and GPUs are are less likely to be used and energy efficiency is paramount.

关键词： Biological neural networks field programmable gate arrays Computer architecture Neurons Parallel processing Optimization

来源：评论

学校读者我要写书评

暂无评论

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model 28

Deterministic Parallel Routing for FPGAs based on Galois Par...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Moctar, Yehdhih Stojilovic, Mirjana Brisk, Philip IBM Res Austin TX 78758 USA Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Lausanne Switzerland Univ Calif Riverside Riverside CA 92521 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

this paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel;and (2) routing one net at a time, while parallelizing the Maze Expansion step. Using eight threads running on eight cores, the two methods achieved speedups of 1.84 x and 3.67 x, respectively, compared to VPR's single threaded routability-driven router. Removing the determinism requirement increased these respective speedups to 2.67 x and 5.46 x, while sacrificing the guarantee of reproducible results.

关键词： Routing Nickel Instruction sets field programmable gate arrays Runtime Parallel processing Task analysis

来源：评论

学校读者我要写书评

暂无评论

A Demonstration of the GUINNESS: A GUI based Neural NEtwork SyntheSizer for an FPGA 27

A Demonstration of the GUINNESS: A GUI based Neural NEtwork ...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Nakahara, H. Yonekawa, H. Fujii, T. Shimoda, M. Sato, S. Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9789090304281

the GUINNESS is a tool flow for the deep neural network toward FPGA implementation [3,4,5] based on the GUI (Graphical User Interface) including both the binarized deep neural network training on GPUs and the inference on an FPGA. It generates the trained the Binarized deep neural network [2] on the desktop PC, then, it generates the bitstream by using standard the FPGA CAD tool flow. All the operation is done on the GUI, thus, the designer is not necessary to write any scripts to descript the neural network structure, training behaviour, only specify the values for hyper parameters. After finished the training, it automatically generates C++ codes to synthesis the bitstream using the Xilinx SDSoC system design tool flow. thus, our tool flow is suitable for the software programmers who are not familiar with the FPGA design.

关键词： Neural networks field programmable gate arrays Training Tools Graphical user interfaces Acceleration C++ languages

来源：评论

学校读者我要写书评

暂无评论

A Deep Learning Framework to Predict Routability for FPGA Circuit Placement 29

A Deep Learning Framework to Predict Routability for FPGA Ci...

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Alhyari, A. Shamli, A. Abuwaimer, Z. Areibi, S. Grewal, G. Univ Guelph Sch Engn Guelph ON Canada Univ Guelph Sch Comp Sci Guelph ON Canada

ISBN: (纸本)9781728148847

the ability to accurately and efficiently estimate the routability of a circuit based on its placement is one of the most challenging and difficult tasks in the field programmable Gate Array (FPGA) flow. In this paper, we present a novel, deep-learning framework based on a Convolutional Neural Network model for predicting the routability of a placement. We also incorporate the deep-learning model into a state-of-the-art placement tool, and show how the model can be used to (1) avoid costly, but futile, place-and-route iterations, and (2) improve the placer's ability to produce routable placements for hard-to-route circuits using feedback based on routability estimates generated by the proposed model. the model is trained and evaluated using over 26K placement images derived from 372 benchmarks supplied by Xilinx Inc. Experimental results show that the proposed framework achieves a routability prediction accuracy of 97%, while exhibiting runtimes of only a few milliseconds.

关键词： Routing Integrated circuit modeling field programmable gate arrays Benchmark testing Heating systems Machine learning Predictive models

来源：评论

学校读者我要写书评

暂无评论

Fault tolerance and reliability in field-programmable gate arrays

引用

IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第3期4卷 196-210页

作者： Stott, E. Sedcole, P. Cheung, P. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England

Reduced device-level reliability and increased within-die process variability will become serious issues for future field-programmable gate arrays (FPGAs), and will result in faults developing dynamically during the lifetime of the integrated circuit. Fortunately, FPGAs have the ability to reconfigure in the field and at runtime, thus providing opportunities to overcome such degradation-induced faults. this study provides a comprehensive survey of fault detection methods and fault-tolerance schemes specifically for FPGAs and in the context of device degradation, with the goal of laying a strong foundation for future research in this field. All methods and schemes are quantitatively compared and some particularly promising approaches are highlighted.

关键词： field programmable gate arrays INTEGRATED circuits INTEGRATED circuit fault tolerance SYSTEMS design FAULT-tolerant computing

来源：评论

学校读者我要写书评

暂无评论

A power estimation model for an FPGA-based softcore processor

A power estimation model for an FPGA-based softcore processo...

引用

17th international conference on field programmable logic and applications

作者： Zipf, Peter Hinkelmann, Heiko Deng, Lei Glesner, Manfred Blume, Holger Noll, Tobias G. Tech Univ Darmstadt Inst Microelect Syst Darmstadt Germany Rhein Westfal TH Aachen Elect Engn & Comp syst Aachen Germany

ISBN: (纸本)9781424410590

We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. this technique enables the estimation of the task specific power consumption of the modeled processor, in our case a LEON2, very early during a system design flow, based on the software which will run on it. the FLPA/ILPA model used during our work as well as the test scenarios and the measured results are described. Later, the function block separation and the power consumption modeling are discussed. Finally, the model is validated by benchmarking. the obtained model is promising in the sense that a) its estimations are close (4 % on average) to the measured data, and b) the model structure is similar to that of hardcore processors which is not a trivial result.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Equivalence verification of FPGA and structured ASIC implementations

Equivalence verification of FPGA and structured ASIC impleme...

引用

17th international conference on field programmable logic and applications

作者： Pistorius, Joachim Hutton, Mike Schleicher, Jay Lotov, Mihail Julias, Enoch tharmalingam, Kumara Altera Corp San Jose CA 95134 USA

ISBN: (纸本)9781424410590

Structured ASICs have recently emerged as a mid-way between cell-based ASICs with high NRE costs and FPGAs with high unit costs. though the structured ASIC fabric attacks mask and other fixed cost it does not solve verification, particularly physical verification issues with ASICs or logic errors missed by simulation which would require re-spins. these can be avoided by testing in-system with an FPGA and migrating the FPGA design to a closely coupled structured ASIC fabric. Here we describe a practical methodology for a fast, push-button, and thorough verification approach tying an FPGA prototype to a matching structured-ASIC implementation for cost-reduction. Our focus is the equivalence verification between the respective revisions of a design, including netlist, compiler settings, macro-block parameters, timing constraints, pin layout and resource count.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A Survey on FPGA Virtualization 28

A Survey on FPGA Virtualization

引用

28th international conference on field programmable logic and applications (FPL)

作者： Vaishnav, Anuj Khoa Dang Pham Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Consequently, FPGA virtualization methods and hardware infrastructures have frequently been proposed in both academia and industry for addressing multi-tenancy execution, multi-FPGA acceleration, flexibility, resource management and security. In this survey, we identify and classify the various techniques and approaches into three main categories: 1) Resource level, 2) Node level, and 3) Multi-node level. In addition, we identify current trends and developments and highlight important future directions for FPGA virtualization which require further work.

关键词： field programmable gate arrays Virtualization Computer architecture Software Hardware Fabrics Task analysis

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：