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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

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An FPGA Implementation of Real-time Object Detection with a thermal Camera 29

An FPGA Implementation of Real-time Object Detection with a ...

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29th international conference on field-programmable logic and applications (FPL)

作者： Shimoda, Masayuki Sada, Youki Kuramochi, Ryosuke Nakahara, Hiroki Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9781728148847

We demonstrate a sparse YOLOv2-based object detector with a thermal camera. A thermal camera outputs pixel values which represent heat (temperature), and the output is gray-scale images. Since the thermal cameras do not depend on whether there is the light or not unlike other visible range cameras, object detection using the thermal camera is reliable without ambient surrounding. this topic is of a broad interest in object surveillance[1] and action recognition[2]. However, since it is challenging to extract informative features from the thermal images, the implementation challenges of the object detector with high accuracy remain. In recent works, convolutional neural networks (CNNs) outperform conventional techniques, and a variety of object detectors based on the CNNs have been proposed. the representative networks are single-shot detectors that consist of a CNN and infer locations and classes simultaneously (e.g., SSD[3] and YOLOv2[4]). Although the primary advantage of the type is that it enables to train detection and classification simultaneously, the resulting increased computation time and area requirements can cause problems of implementation on an FPGA. Also, as for the proposed networks on RGB three channel images, one of the problems is false positive;the realization of more reliable object detector is required. To realize a real-time reliable object detector, we investigate an FPGA implementation of a sparse YOLOv2-based one whose inputs are four-channel images that consist of both the RGB and the thermal ones. In this demonstration, we show a performance comparison between an RGB-based detector and our proposed one on FPGAs.

关键词： Detectors field programmable gate arrays Cameras Object detection conferences Reliability Feature extraction

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Power Management in FPGAs using a Temperature Aware Place and Route Methodology 9

Power Management in FPGAs using a Temperature Aware Place an...

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9th IEEE international conference on Communication and Signal Processing, ICCSP 2020

作者： Gopikrishna, P.V. Kulkarni, G.H. KLS Gogte Institute of Technology Department of Electronics and Communication Engineering Belagavi India Jain College of Engineering Department of Electrical and Electronics Engineering Belagavi India

ISBN: (纸本)9781728149882

Due to increase in demand for low power electronic systems in recent years, significant research and development work is happening in the low power domain. this is especially true for field programmable Gate Arrays (FPGAs), which dissipate significantly more power than fixed-logic implementations. Power is a critical issue when FPGA applications are considered. In spite of the significant improvements in the recent past, power dissipation in FPGAs is significant. With the scaling down of CMOS process technology, factors like higher total interconnect capacitance per chip, higher operating frequencies, and increase in leakage will continue to increase the power density. All these factors will increase the operating temperature of the device which leads to the production of heat inside the chip. the final implementation is affected by the problems associated with the increase in heat produced. Some critical issues associated with temperature rise are the system reliability, the packaging of the chip and the life cycle of the final product. the dominance of the heat problem is one of the key design issues, which needs to be addressed. It is observed that in FPGAs the central portion of the device gets heated up due to the concentration of active Configurable logic Blocks (CLBs) at the centre. Effect of arranging the unused CLBs at different places across the FPGA and the thermal distribution is examined in the present work. this paper aims at minimizing the total power consumption and also to redistribute it across the entire FPGA. A temperature-aware placement and routing is considered, by placing the unused CLBs across different locations of the FPGA so as to obtain uniform temperature profile across the entire cross section of FPGA. Since temperature is dependent on the switching activity of the hardware resources of FPGA, the proposed methodology aims at redistributing the switching activity over the FPGA resources. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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Ultra-Low Power Rectangular field programmable Analogue Arrays For Biomedical applications 16

Ultra-Low Power Rectangular Field Programmable Analogue Arra...

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16th international System-on-Chip Design conference (ISOCC)

作者： Diab, Maha S. Mahmoud, Soliman Univ Sharjah Dept Elect & Comp Engn Sharjah U Arab Emirates

ISBN: (纸本)9781728124780

A field programmable analogue array (FPAA) for biomedical applications is introduced in this paper. the proposed FPAA is based on operational transconductance amplifier (OTA). the FPAA consists of configurable analogue blocks (CABs) arranged in three sections. Each section implements an OTA-C filter of reconfigurable order with variable gain, and bandwidth. Direct connections between CABs within a section, and between sections are present. the proposed reconfigurable FPAA permits different connections between its sections, providing a wide range of possible applications. Allowing the implementation of full biomedical systems, such as the analogue front-end (AFE) for biopotential signal acquisition. Reconfigurability and functionality of the proposed FPAA architecture is demonstrated through mapping of low power filters and AFE on FPAA. Simulations results for a 90 mu CMOS technology are given. the simulation results of filter and AFE on FPAA are compared to off-FPAA simulations.

关键词： biosignal FPAA OTA-C

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A High-Performance Data Processing Unit for Next Generation Satellite Transceivers 8

A High-Performance Data Processing Unit for Next Generation ...

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8th Annual IEEE international conference on Wireless for Space and Extreme Environments (WiSEE)

作者： Rust, Jochen Hao, Mingjie Karsthof, Ludwig Paul, Steffen Hashem, Elias Kulau, Ulf DSI Aerosp Technol GmbH Bremen Germany Univ Bremen Dept Commun Elect ITEMme Bremen Germany

ISBN: (数字)9781728164519

ISBN: (纸本)9781728164519

In this paper a novel High-Performance Data Processing Unit is presented that enables the design of flexible but high-performance wireless communication transceivers for space applications. Core of this platform is a Kintex Ultrascale FPGA which is available as a space-qualified and COTS device serving both, the deployment in traditional space and NewSpace applications, respectively. High modularity is achieved by using the cPCI-SS backplane standard that allows a seamless assembly, integration and testing, while offering a high re-usability in order to reduce the recurring costs. In addition, a mezzanine-connector-based interface allows the integration of application-specific extension boards, in particular RF-ICs. For evaluation, a State-of-the-Art signal processing chain for robust wireless communications is mapped onto our proposed High-Performance Data Processing Unit and the performance is analyzed. A comparison to other COTS and space-qualified FPGA devices highlights our approach to be a powerful solution for next generation high-performance transceivers, e.g. for 5G NTN.

关键词： Satellites Transceivers 5G mobile communication Wireless communication field programmable gate arrays Satellite broadcasting Aerospace electronics

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FPGA-Based modular multilevel converter (MMC) controller for efficient voltage balancing in real-time simulation

FPGA-Based modular multilevel converter (MMC) controller for...

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the 16th IET international conference on AC and DC Power Transmission (ACDC 2020)

作者： K. Xiong G. Wang J. Zhang G. He Shanghai Jiaotong University School of Electronic Information and Electrical Engineering Shanghai China

At present, the implementation of the capacitor voltage balancing controller is a great challenge for the real-time simulation of the MMC systems. In this paper, a field-programmable gate array (FPGA)-based MMC controller is presented. In order to break through the bottleneck of sort scheme in real-time simulation, an efficient sorting scheme is proposed. this scheme is integrated by bucket sort and oddeven sort. It can greatly reduce the comparison times and highly leverage the inherent parallelism in FPGA. A special storage scheme is proposed and can greatly reduce resource consumption of sub-module (SM) voltages and make the utilization of FPGA more efficient. this proposed MMC controller is implemented by high-level synthesis (HLS) and a set of optimization methods are proposed to reduce the timestep. the proposed controller offers a controller timestep of 50us on Xilinx VC709 and support for 640 SMs each bridge-arm and 6 bridge-arms in one MMC on a single board. the performance and accuracy are evaluated on a case study of a back-to-back MMC-HVDC system on ADPSS.

关键词： power convertors sorting power system simulation logic design HVDC power transmission field programmable gate arrays HVDC power convertors reconfigurable architectures

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Virtualizing FPGAs in the Cloud 20

Virtualizing FPGAs in the Cloud

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25th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Zha, Yue Li, Jing Univ Penn Philadelphia PA 19104 USA

ISBN: (纸本)9781450371025

field-programmable Gate Arrays (FPGAs) have been integrated into the cloud infrastructure to enhance its computing performance by supporting on-demand acceleration. However, system support for FPGAs in the context of the cloud environment is still in its infancy with two major limitations, i.e., the inefficient runtime management due to the tight coupling between compilation and resource allocation, and the high programming complexity when exploiting scale-out acceleration. the root cause is that FPGA resources are not virtualized. In this paper, we propose a full-stack solution, namely ViTAL, to address the aforementioned limitations by virtualizing FPGA resources. Specifically, ViTAL provides a homogeneous abstraction to decouple the compilation and resource allocation. applications are offline compiled onto the abstraction, while the resource allocation is dynamically determined at runtime. Enabled by a latency-insensitive communication interface, applications can be mapped flexibly onto either one FPGA or multiple FPGAs to maximize the resource utilization and the aggregated system throughput. Meanwhile, ViTAL creates an illusion of a single and large FPGA to users, thereby reducing the programming complexity and supporting scale-out acceleration. Moreover, ViTAL also provides virtualization support for peripheral components (e.g., on-board DRAM and Ethernet), as well as protection and isolation support to ensure a secure execution in the multi-user cloud environment. We evaluate ViTAL on a real system-an FPGA cluster composed of the latest Xilinx UltraScale+ FPGAs (XCVU37P). the results show that, compared with the existing management method, ViTAL enables fine-grained resource sharing and reduces the response time by 82% on average (improving Quality-of-Service) with a marginal virtualization overhead. Moreover, ViTAL also reduces the response time by 25% compared to AmorphOS (operating in high-throughput mode), a recently proposed FPGA virtualization method.

关键词： scale-out acceleration system abstraction compilation framework cloud computing field-programmable gate arrays

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Real-time Performance Evaluation of Single Phase 7 Level Z-Source Boost Inverter

Real-time Performance Evaluation of Single Phase 7 Level Z-S...

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international conference on Electrical Energy Systems (ICEES)

作者： Hanuman Prasad Kishor V. Bhadane Parveen Kumar Model Institute of Engineering and Technology Jammu India Amrutvahini College of Engineering Sangamner Maharashtra India

ISBN: (数字)9781728176123

ISBN: (纸本)9781728176130

Multilevel inverter has been familiarized as a popular topology for DC-AC power conversion. this paper illustrates the real-time performance evolution of seven level zsource diode clamp multilevel inverter. the field programmable gate array (FPGA) integrated real time simulators consists of multiprocessor and computer clusters are the main hardware platforms for real-time simulations. the real time (RI) lab software enables the parallel simulation of an electrical circuit on clusters of personal computer running at sampling time 10 μs. the integration of multilevel inverter and z-source energy conversion are used for DC-AC converter for high power applications with low total harmonics distortion. An impedance network has two passive elements such as two inductors and two capacitors connected between DC power source and multilevel inverter circuit. It provides a unique feature such as the boost the inverter output voltage and reduces the harmonic content in the output voltage as compared to the classic multilevel inverter. the real time results are verified the proposed system with a specified time step 10 μs and frequency is 10 KHz.

关键词： Computational modeling logic gates Multilevel inverters DC-AC power converters Real-time systems Integrated circuit modeling field programmable gate arrays

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Power Optimization of KNN Algorithm Based on FPGA

Power Optimization of KNN Algorithm Based on FPGA

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international conference on Engineering Technology and their applications (IICETA)

作者： Fadi T. Naser Sarah N. Hadi Ivan A. Hashim University of Technology Baghdad Iraq Al-Salam University College Baghdad Iraq

ISBN: (纸本)9781665494625

In modern field programmable Gate Array (FPGA) digital systems, power dissipation has become a critical concern to design digital systems. As size shrinks and density increases in chips, it will be a challenge to design high-performance and low-power digital systems. therefore, it is important to reduce the power dissipation in these systems by using power-optimization techniques. Most digital systems have different mathematical operations and machine learning algorithms in their architectures. this paper focuses on K-Nearest Neighbor (KNN) algorithm. A KNN algorithm takes more extended time, larger area and consumes more power than other basic computational algorithms. thus, recent digital systems require high speed and low-power KNN algorithm in order to improve its performance. In this work, dynamic-power consumption is targeted. Different designs of KNN algorithms, such as KNN design Based on Hard FPGA Blocks, Hybrid KNN Design, and KNN Algorithm Based on the VHDL Approach are suggested. A new power-optimization technique is suggested. the new VHDL technique shows the highest dynamic power saving, about (90%) than the other proposed designs.

关键词： VHDL Machine learning algorithms Digital systems Heuristic algorithms Switches logic gates Power dissipation

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Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling 29

Accelerating Bayesian Inference on Structured Graphs Using P...

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29th international conference on field-programmable logic and applications (FPL)

作者： Ko, Glenn G. Chai, Yuji Rutenbar, Rob A. Brooks, David Wei, Gu-Yeon Harvard Univ Cambridge MA 02138 USA Univ Pittsburgh Pittsburgh PA USA

ISBN: (纸本)9781728148847

Bayesian models and inference is a class of machine learning that is useful for solving problems where the amount of data is scarce and prior knowledge about the application allows you to draw better conclusions. However, Bayesian models often requires computing high-dimensional integrals and finding the posterior distribution can be intractable. One of the most commonly used approximate methods for Bayesian inference is Gibbs sampling, which is a Markov chain Monte Carlo (MCMC) technique to estimate target stationary distribution. the idea in Gibbs sampling is to generate posterior samples by iterating through each of the variables to sample from its conditional given all the other variables fixed. While Gibbs sampling is a popular method for probabilistic graphical models such as Markov Random field (MRF), the plain algorithm is slow as it goes through each of the variables sequentially. In this work, we describe a binary label MRF Gibbs sampling inference architecture and extend it to 64-label version capable of running multiple perceptual applications, such as sound source separation and stereo matching. the described accelerator employs a chromatic scheduling of variables to parallelize all the conditionally independent variables to 257 samplers, implemented on the FPGA portion of a CPU-FPGA SoC. For real-time streaming sound source separation task, we show the hybrid CPU-FPGA implementation is 230x faster than a commercial mobile processor, while maintaining a recommended latency under 50 ms. the 64-label version showed 137x and 679x speedups for binary label MRF Gibbs sampling inference and 64 labels, respectively.

关键词： bayesian inference markov chain monte carlo gibbs sampling hardware accelerator markov random field

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A Simple Heterogeneous Redundant Design Method for Finite State Machines on FPGAs 13th

A Simple Heterogeneous Redundant Design Method for Finite St...

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13th international conference on Complex, Intelligent, and Software Intensive Systems (CISIS)

作者： Itagawa, Takanori Kamasaka, Ryo Shibata, Yuichiro Nagasaki Univ 1-14 Bunkyo Machi Nagasaki 8528521 Japan

ISBN: (纸本)9783030223540;9783030223533

For FPGA applications in the application domains requiring a high degree of functional safety such as automotive and industrial infrastructure, simple homogeneous redundant logic design, where the same hardware modules are simply replicated, is not enough. In order to improve tolerance to common cause fault, heterogeneous redundant design, where different implementation approaches are taken for realizing the same logic functionality, is crucial. However, manual redundant design tends to place a burden on designers, reducing productivity of system development. To cope with this problem, this paper proposes a systematic heterogeneous redundant design approach for finite state machines on FPGAs, focusing on the diversity of state encoding methods. With this approach, designers can easily combine the state machines with different encoding to form heterogeneous redundancy, by inserting simple directives into RTL source code. In order to evaluate the effectiveness of the proposed approach, timing analysis of post-layout netlists is performed under an overclock situation as an example of common cause fault. the evaluation results demonstrate the proposed approach improves the error detection rate compared to conventional homogeneous redundant designs. It is also discussed how the choice of state encoding methods impacts the error detection rate.

关键词： field programmable gate arrays (FPGA)

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