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5th international Workshop on FPGAs for Software Programmers, FSP 2018, co-located with international conference on field programmable logic and applications, FPL 2018

作者： Heid, Kris Wenzel, Jakob Hochberger, Christian Computer Systems Group Technische Universität Darmstadt Merckstraße 25 Darmstadt64283 Germany

ISBN: (纸本)9783800747238

Today, a growing number of digital systems containing a software part is realized on field programmable Gate Arrays. this allows to use application specific multi-core architectures to run parts of the application in parallel. Automatic parallelization of embedded software is desired to make optimal use of these flexible multi-core architectures. In many programs, loops hold a majority of the total execution time and benefit from parallelization. In this contribution, we present a loop transformation tool that improves the parallelizability of typical legacy C code containing loops by a factor of two. Different than other approaches, we are using a pipeline-parallel execution model especially suited for distributed-memory systems. this execution model has widely different demands on beneficial loop transformation methods than other well known parallel execution models like widely applied in HPC. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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BOSON - Application-Specific Instruction Set Processor (ASIP) for Educational Purposes

BOSON - Application-Specific Instruction Set Processor (ASIP...

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international conference on Control, Automation, Robotics and Vision (ICARCV)

作者： Przemyslaw Mazurek Faculty of Electrical Engineering West Pomeranian University of Technology Szczecin Szczecin Poland

ISBN: (数字)9781728177090

ISBN: (纸本)9781728177106

this paper describes the Boson - Application-Specific Instruction Set Processor (ASIP), which is intended for educational purposes at the university. ASIP allows ISA (Instruction Set Architecture) optimization for a specific task, which is important for project optimization. Considered soft processor allows step-by-step learning of ASIP technology and microcontroller using the Logisim simulator, as well as a FPGA synthesis tool such as Quartus. Presented project shows the main ideas and design choices that were verified in the education process in the third semester of engineering studies “Information and Communication Technologies”.

关键词： field programmable gate arrays Clocks Tools Registers Hardware design languages Computer architecture logic gates

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Exact mapping of rewritten linear functions to configurable logic 5

Exact mapping of rewritten linear functions to configurable ...

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5th international Workshop on FPGAs for Software Programmers, FSP 2018, co-located with international conference on field programmable logic and applications, FPL 2018

作者： Greene, Jonathan W. Microsemi San JoseCA United States

ISBN: (纸本)9783800747238

We describe a method of mapping linear arithmetic functions to a targeted network of multipliers, adders, registers, muxes, and ROMs holding coefficients. the network may be fairly specific, or made more configurable by varying the primitives' control signals and adding routing muxes. Examples of possible functions include FIR and IIR filters, convolution, and FFTs. the method implicitly considers rewriting the function, such as by the associative and distributive properties of arithmetic, or methods such as Winograd filtering that benefit from combined computation of successive outputs. the method is intended to be used to implement IP for existing FPGA math blocks, evaluate new FPGA math block architectures, or potentially as a subroutine in high-level synthesis. Illustrative architectures using the PolarFireTM FPGA math block are presented, including: a symmetric FIR in which the math block operates at twice the speed of the fabric;a general (asymmetric) FIR that produces one sample per clock cycle with fewer multipliers than taps;and a folded symmetric FIR using fewer memory blocks than multipliers. the method is related to modulo scheduling and relies on a SAT or ILP solver. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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HyperLogLog Sketch Acceleration on FPGA

HyperLogLog Sketch Acceleration on FPGA

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international conference on field programmable logic and applications

作者： Amit Kulkarni Monica Chiosa thomas B. Preußer Kaan Kara David Sidler Gustavo Alonso Systems Group ETH Zürich Switzerland ETH Zurich Switzerland Microsoft Corporation Redmond WA USA

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Data sketches are a set of widely used approximated data summarizing techniques. their fundamental property is sub-linear memory complexity on the input cardinality, an important aspect when processing streams or data sets with a vast base domain such as URLs, IP addresses, user IDs, etc. Among the many data sketches available, HyperLogLog has become the reference for cardinality counting i.e., how many distinct data items there are in a data set. Although it does not count every data item but provides probabilistic guarantees on the result thereby reducing its memory footprint, and the result is often used to analyze data streams. In this paper, we explore how to implement HyperLogLog on an FPGA to benefit from the parallelism available and the ability to process data streams coming from high-speed networks. Our multi-pipelined high-cardinality HyperLogLog implementation delivers 1.8x higher throughput than the best-optimized multi-thread HyperLogLog running on a dual-socket Intel Xeon E5-2630 v3 system with a total of 16 cores and 32 hyper-threads.

关键词： field programmable gate arrays Estimation Data processing Hardware Acceleration throughput TCPIP

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ZUCL 2.0: Virtualised memory and communication for ZYNQ UltraScale+ FPGAS 6

ZUCL 2.0: Virtualised memory and communication for ZYNQ Ultr...

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6th international Workshop on FPGAs for Software Programmers, FSP 2019, co-located with international conference on field programmable logic and applications, FPL 2019

作者： Pham, Khoa Dang Paraskevas, Kyriakos Vaishnav, Anuj Attwood, Andrew Vesper, Malte Koch, Dirk Department of Computer Science University of Manchester Manchester United Kingdom Science and Technology Facilities Council United Kingdom

ISBN: (纸本)9783800750467

this paper introduces ZUCL 2.0, which extends abstraction services for FPGA applications on ARM-FPGA hybrids. the ZUCL 2.0 management services include 1) FPGA multi-tasking and context-switching based on dynamic reconfiguration and cooperative scheduling, 2) communication abstraction based on the ARM AMBA standard, and 3) memory isolation for privacy and security purposes. Moreover, FPGA applications deployed on ZUCL 2.0 and the ZUCL 2.0 kernel itself can be built and maintained independently. this is a crucial feature for higher design productivity and more flexible system updates. Prototypes were implemented for latest Xilinx UltraScale+ ZCU102, UltraZed and Ultra96 platforms to demonstrate the capabilities of ZUCL 2.0. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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Compact and programmable yet High-Performance SoC Architecture for Cryptographic Pairings

Compact and Programmable yet High-Performance SoC Architectu...

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international conference on field programmable logic and applications

作者： Milad Bahadori Kimmo Järvinen Department of Computer Science University of Helsinki Helsinki Finland University of Helsinki Helsinki Finland

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Cryptographic pairings are important primitives for many advanced cryptosystems. Efficient computation of pairings requires the use of several layers of algorithms as well as optimizations in different algorithm and implementation levels. this makes implementing cryptographic pairings a difficult task particularly in hardware. Many existing hardware implementations fix the parameters of the pairing to improve efficiency but this significantly limits the generality and practicality of the solution. In this paper, we present a compact and programmable yet high-performance architecture for programmable system-on-chip platforms designed for efficient computation of different cryptographic pairings. We demonstrate with real hardware that this architecture can compute optimal ate pairings on a Barreto-Naehrig curve with 126-bit security in 2.18ms in a Xilinx Zynq-7020 device and occupies only about 3200 slices, 36 DSPs, and 18 BRAMs. We also show that the architecture can support different types of pairings via microcode updates and can be implemented on other reprogrammable devices with very minor modifications.

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An Area Effective OFDM Transceiver System with Multi-Radix FFT/IFFT Algorithm for Wireless applications

An Area Effective OFDM Transceiver System with Multi-Radix F...

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international conference on Advanced Computing and Communication Systems (ICACCS)

作者： S. Dhanasekar P. Malin Bruntha T. Mary Neebha N. Arunkumar N. Senathipathi C. Priya Sri Eshwar College of Engineering Coimbatore India Karunya Institute of Technology and Sciences Coimbatore India P.A College of Engineering and Technology Pollachi India Karpagam College of Engineering and Technology Coimbatore India

An area effective Orthogonal Frequency Division Multiplexing (OFDM) transceiver design with Multi-radix FFT/IFFT algorithm is introduced for wireless applications. the Pseudo-Random Binary Sequence (PRBS) will be sent as input to OFDM Transmitter, which is passed on using orthogonal frequency. Inverse Fast Fourier Transform (IFFT) and Fast Fourier Transform (FFT) processors employ a significant role in OFDM transceiver design, which increases the area and power in the silicon area. the Multi-radix algorithms like Radix-2², Radix- 2³, Radix-2⁴ are used in the FFT/IFFT processors to decrease computational complexity. the FFT/IFFT algorithms use Urdhva Tiryakbhyam Vedic multipliers to decrease the undesired multiplication steps. To increase the speed of the multiplier, compressor adders will be introduced which reduces carry delay. the Vedic multiplier-based Multi-radix FFT/IFFT algorithms save hardware area in a silicon chip. the proposed OFDM transceiver design is implemented using Virtex-2 XC2V500-6 fg256 field programmable Gate Array (FPGA) device has achieved 41974-input Lookup Tables (LUTs), 2217 slices. It is operated with a maximum clock frequency of 155.35 MHz. the Multi-radix FFT/IFFT-based OFDM transceiver design reduces 84.4% slices, 68.1% 4-input LUTs and it occupies 62. 3K gates. the multi-carrier modulation technique used in the OFDM transceiver design enhances high-speed data transmission in wireless communication.

关键词： Wireless communication Program processors Frequency modulation OFDM logic gates Transceivers Silicon

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Resilient training of neural network classifiers with approximate computing techniques for hardware-optimised implementations

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第6期13卷 532-542页

作者： Torres, Vitor Ferreira Torres, Frank Sill Univ Fed Minas Gerais Grad Program Elect Engn Av Antonio Carlos 6627 BR-31270901 Belo Horizonte MG Brazil DFKI GmbH Cyber Phys Syst Bibliothekstr 5 D-28359 Bremen Germany

As Machine Learning applications increase the demand for optimised implementations in both embedded and high-end processing platforms, the industry and research community have been responding with different approaches to implement these solutions. this work presents approximations to arithmetic operations and mathematical functions that, associated with a customised adaptive artificial neural networks training method, based on RMSProp, provide reliable and efficient implementations of classifiers. the proposed solution does not rely on mixed operations with higher precision or complex rounding methods that are commonly applied. the intention of this work is not to find the optimal simplifications for specific deep learning problems but to present an optimised framework that can be used as reliably as one implemented with precise operations, standard training algorithms and the same network structures and hyper-parameters. By simplifying the 'half-precision' floating point format and approximating exponentiation and square root operations, the authors' work drastically reduces the field programmable gate array implementation complexity (e.g. -43 and -57% in two of the component resources). the reciprocal square root approximation is so simple it could be implemented only with combination logic. In a full software implementation for a mixed-precision platform, only two of the approximations compensate the processing overhead of precision conversions.

关键词： field programmable gate arrays learning (artificial intelligence) floating point arithmetic neural nets resilient training neural network classifiers approximate computing techniques hardware-optimised implementations high-end processing platforms research community arithmetic operations mathematical functions customised adaptive artificial neural networks training method mixed operations complex rounding methods optimal simplifications specific deep learning problems optimised framework precise operations standard training algorithms network structures half-precision floating point square root operations field programmable gate array implementation complexity reciprocal square root approximation software implementation mixed-precision platform precision conversions machine learning applications

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Particle computation: complexity, algorithms, and logic

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NATURAL COMPUTING 2019年第1期18卷 181-201页

作者： Becker, Aaron T. Demaine, Erik D. Fekete, Sandor P. Lonsford, Jarrett Morris-Wright, Rose Univ Houston Dept Elect & Comp Engn Houston TX USA MIT Comp Sci & Artificial Intelligence Lab 77 Massachusetts Ave Cambridge MA 02139 USA TU Braunschweig Dept Comp Sci Braunschweig ME Germany Brandeis Univ Dept Math Waltham MA 02254 USA

We investigate algorithmic control of a large swarm of mobile particles (such as robots, sensors, or building material) that move in a 2D workspace using a global input signal (such as gravity or a magnetic field). Upon activation of the field, each particle moves maximally in the same direction until forward progress is blocked by a stationary obstacle or another stationary particle. In an open workspace, this system model is of limited use because it has only two controllable degrees of freedom-all particles receive the same inputs and move uniformly. We show that adding a maze of obstacles to the environment can make the system drastically more complex but also more useful. We provide a wide range of results for a wide range of questions. these can be subdivided into external algorithmic problems, in which particle configurations serve as input for computations that are performed elsewhere, and internal logic problems, in which the particle configurations themselves are used for carrying out computations. For external algorithms, we give both negative and positive results. If we are given a set of stationary obstacles, we prove that it is NP-hard to decide whether a given initial configuration of unit-sized particles can be transformed into a desired target configuration. Moreover, we show that finding a control sequence of minimum length is PSPACE-complete. We also work on the inverse problem, providing constructive algorithms to design workspaces that efficiently implement arbitrary permutations between different configurations. For internal logic, we investigate how arbitrary computations can be implemented. We demonstrate how to encode dual-rail logic to build a universal logic gate that concurrently evaluates and, nand, nor, and or operations. Using many of these gates and appropriate interconnects, we can evaluate any logical expression. However, we establish that simulating the full range of complex interactions present in arbitrary digital circuits encoun

关键词： programmable matter Robot swarms Nano-particles Uniform inputs Parallel motion planning Complexity Array permutations NP-completeness PSPACE-completeness Efficient algorithms logic gates Universal computation

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Invited tutorial: OpenCL design flows for Intel and Xilinx FPGAS: Using common design patterns and dealing with vendor-specific differences 6

Invited tutorial: OpenCL design flows for Intel and Xilinx F...

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6th international Workshop on FPGAs for Software Programmers, FSP 2019, co-located with international conference on field programmable logic and applications, FPL 2019

作者： Kenter, Tobias Paderborn Center for Parallel Computing Department of Computer Science Paderborn University Warburger Str. 100 Paderborn33098 Germany

ISBN: (纸本)9783800750467

An increasing fraction of new results in the reconfigurable computing domain are obtained with the help of high level synthesis tools. Among the more popular tools are the OpenCL based Xilinx SDAccel and Intel FPGA SDK for OpenCL. Since they are building upon the same programming model and source language, one would hope for portability between different OpenCL based FPGA designs. However, the vast majority of published research is only optimized for one vendor tool and FPGA family. In this manuscript, we want to broaden that scope and provide practical guidance for both tool chains. We outline the common underlying design philosophy and goals of high level synthesis for FPGAs on an abstract level, before proceeding to an example-driven discussion of tool features and concepts. We present design patterns that work well for both tools and thus can promote portability of OpenCL based FPGA designs. We outline how tool differences that can be overcome for portability, or used for further optimized tool-specific designs. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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