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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

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doppioDB: A Hardware Accelerated Database 27

doppioDB: A Hardware Accelerated Database

引用

27th international conference on field programmable logic and applications (FPL)

作者： Sidler, David Owaida, Muhsen Istvan, Zsolt Kara, Kaan Alonso, Gustavo Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (纸本)9789090304281

Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings). With the increasing amount of user-generated data stored in relational databases, there is a growing need to analyze unstructured text data. At the same time more complex analytical operators are required to extract useful information from the vast amount of collected data. However, many analytical operators incur a significant compute complexity not suitable to database engines where multiple queries share the available resources. In this demonstration we show the benefit of using specialized hardware for such tasks and highlight the importance of a flexible, reusable mechanism for extending database engines with hardware-based operators. Our hybrid database engine, doppioDB, is deployed on an emerging Xeon+FPGA multicore architecture where the CPU and FPGA have cache-coherent access to the same memory, such that the hardware operators can directly access the database tables. the demonstration is illustrating the acceleration benefits of hardware operators, as well as doppioDB's flexibility in accommodating changing workloads.

关键词： Hardware Acceleration Databases field programmable gate arrays Engines Software

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A Partial Reconfiguration based Microphone Array Network Emulator 27

A Partial Reconfiguration based Microphone Array Network Emu...

引用

27th international conference on field programmable logic and applications (FPL)

作者： da Silva, Bruno Dominguez, Federico Braeken, An Touhafi, Abdellah Vrije Univ Brussel Dept Ind Sci INDI Brussels Belgium Escuela Super Politecn Litoral ESPOL Guayaquil Ecuador

ISBN: (纸本)9789090304281

Nowadays, microphone arrays are used in many applications for sound-source localization or acoustic enhancement. the current Micro-Electro-Mechanical Systems (MEMS) technology allows the development of networks of microphone arrays at a relatively low cost. Unfortunately, the evaluation of these networks requires controlled acoustic environments, such as anechoic chambers, to avoid possible distortions and acoustic artifacts. In this paper, we present a partial reconfigurable FPGA platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network's topology or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. In addition, our platform is also capable to converge to the ideal network with regards to power consumption, while still maintaining the desired level of sound-source localization accuracy. A graphical user interface provides a friendly control of the network and the parameters under test during the execution of the partial reconfiguration operations. Several experiments are presented to demonstrate some of the capabilities of our platform.

关键词： field programmable gate arrays Microphone arrays Acoustics Data integration Computer architecture Acoustic arrays

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REAPR: Reconfigurable Engine for Automata Processing 27

REAPR: Reconfigurable Engine for Automata Processing

引用

27th international conference on field programmable logic and applications (FPL)

作者： Xie, Ted Dang, Vinh Wadden, Jack Skadron, Kevin Stan, Mircea Univ Virginia Dept Elect & Comp Engn Charlottesville VA 22903 USA Univ Virginia Dept Comp Sci Charlottesville VA 22903 USA

ISBN: (纸本)9789090304281

Finite automata have proven their usefulness in high-profile domains ranging from network security to machine learning. While prior work focused on their applicability for purely regular expression workloads such as antivirus and network security rulesets, recent research has shown that automata can optimize the performance for algorithms in other areas such as machine learning and even particle physics. Unfortunately, their emulation on traditional CPU architectures is fundamentally slow and further bottlenecked by memory. In this paper, we present REAPR: Reconfigurable Engine for Automata PRocessing, a flexible framework that synthesizes RTL for automata processing applications as well as I/O to handle data transfer to and from the kernel. We show that even with memory and control flow overheads, FPGAs still enable extremely high-throughput computation of automata workloads compared to other architectures.

关键词： Automata field programmable gate arrays Engines Learning automata Benchmark testing Computer architecture

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An Efficient Reconfigurable Architecture by Characterizing Most Frequent logic Functions 25

An Efficient Reconfigurable Architecture by Characterizing M...

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25th international conference on field programmable logic and applications

作者： Ahmadpour, Iman Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Tehran Iran

ISBN: (纸本)9781467381239

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity or attain asymmetric low input functions. A heterogeneous LUT-HL architecture and a mapping scheme are also proposed to attain maximum logic resource usage. Experimental results on MCNC benchmarks demonstrate that the proposed architecture reduces area-delay product by 13% and 36% as compared to LUT4 and LUT6 based FPGAs, respectively. Considering the same area budget, our proposed architecture improves performance by 17% and 2% as compared to LUT4 and LUT6 based FPGAs.

关键词： logic functions Formal logic Reconfigurable architectures application specific integrated circuits input function BENCHMARKS Building construction LIPC gene ARCHITECTURE hectolitre

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Versatile Deployment of FPGA Accelerators in Disaggregated Data Centers: a Bioinformatics Case Study 27

Versatile Deployment of FPGA Accelerators in Disaggregated D...

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27th international conference on field programmable logic and applications (FPL)

作者： Alachiotis, Nikolaos theodoropoulos, Dimitris Pnevmatikatos, Dionisios Fdn Res & Technol Hellas Inst Comp Sci Iraklion 70013 Greece Tech Univ Crete Sch Elect & Comp Engn Khania 73100 Greece

ISBN: (纸本)9789090304281

Important design considerations for the cost-effective employment of hardware accelerators in next-generation data centers involve a) the type of candidate applications that a proposed solution can accelerate (generality), and b) the required development effort to successfully deploy the available accelerators for a given application (adoption overhead). To address the problem of generality, we present a versatile and dynamically reconfigurable hardware architecture that exhibits several accelerator slots and programmable interconnect to create application-specific accelerator datapaths. the proposed architecture fits in the model of disaggregated data centers, where compute, memory, and accelerators are broadly regarded as large pools of resources, and subsets of these resource pools are dynamically allocated on an as-needed basis to cooperatively boost performance of a broad range of applications. Initial results for a bioinformatics application that we employ as a case study and deals with the detection of positive selection in large-scale genomic datasets reveal a speedup of up to 6.4X when custom hardware accelerators are mapped to the proposed versatile accelerator architecture and compared with a parallel and highly optimized software implementation executed on a multi-core processor.

关键词： Hardware Acceleration Computer architecture field programmable gate arrays Genomics Bioinformatics

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Extracting INT8 Multipliers from INT18 Multipliers 29

Extracting INT8 Multipliers from INT18 Multipliers

引用

29th international conference on field-programmable logic and applications (FPL)

作者： Langhammer, Martin Pasca, Bogdan Baeckler, Gregg Gribok, Sergey Intel Santa Clara CA 95054 USA

ISBN: (纸本)9781728148847

With the advent of machine learning as perhaps the most high-profile application area for FPGAs, there is a compelling reason to improve the provision of smaller precision arithmetic on these devices. INT8 is commonly used for AI inferencing, and along with some additional soft logic for exponent handling, can be an effective solution for training as well. this paper describes techniques for efficiently extracting INT8 multipliers from commonly available INT18 multipliers found in many modern FPGAs. A small amount of soft logic - as little as 7 ALMs per INT8 multiplier is required to provide pre or post multiplier correction to calculate two INT8 multiplies from a single 18x18 multiplier. We present two configurations for both signed and unsigned representations where two multiplications share one input operand. In addition to the individual INT8 variants, we present full device cases of 22,400 INT8 multipliers organized as DOT32 product arrays, with the soft logic tightly bound to the INT18 based DSP Blocks. A majority of the soft logic and routing in the device is left untouched, and available for application development.

关键词： field programmable gate arrays logic gates Adders Artificial intelligence US Department of Transportation Routing Computer architecture

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BITSTREAM COMPRESSION thROUGH FRAME REMOVAL AND PARTIAL RECONFIGURATION

BITSTREAM COMPRESSION THROUGH FRAME REMOVAL AND PARTIAL RECO...

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19th international conference on field programmable logic and applications

作者： Sellers, Benjamin Heiner, Jonathan Wirthlin, Michael Kalb, Jeff Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA Sandia Natl Labs Wireless Event Sensing Applicat Albuquerque NM USA

ISBN: (纸本)9781424438914

As FPGA logic density continues to increase, new techniques are needed to store initial configuration data efficiently, maintain usability, and minimize cost. In this paper, a novel compression technique is presented for Xilinx Virtex partially reconfigurable FPGAs. this technique relies on constrained hardware design and layout combined with a few simple compression techniques. this technique uses partial reconfiguration to separate a hardware design into two separate regions: a static and partial region. A bitstream containing only the static region is then compressed by removing empty frames. this bitstream will be stored in non-volatile memory and used for initialization. the remaining logic is configured through partial reconfiguration over a communication network. By applying this technique, a high level of compression was achieved (almost 90% for the V4 LX25). this compression technique requires no extra decompression circuitry and compression levels improve as device size increases.

关键词： field programmable gate arrays (FPGA)

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FPGA implementation of a data-driven stochastic biochemical simulator with the next reaction method

FPGA implementation of a data-driven stochastic biochemical ...

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17th international conference on field programmable logic and applications

作者： Yoshimi, Masato Iwaoka, Yow Nishikawa, Yuri Kojima, Toshinori Osana, Yastmori Funahashi, Akira Hiroi, Noriko Shibata, Yuichiro Iwanaga, Naoki Kitano, Hiroaki Amano, Hideharu Keio Univ Yokohama Kanagawa 223 Japan JST ERATO SORST Kitano Symbiot Syst Project Tokyo Japan Nagasaki Univ Nagasaki Japan

ISBN: (纸本)9781424410590

this paper introduces a scalable FPGA implementation of a stochastic simulation algorithm (SSA) called the Next Reaction Method. there are some hardware approaches of SSAs that obtained high-throughput on reconfigurable devices such as FPGAs, but these works lacked in scalability. the design of this work can accommodate to the increasing size of target biochemical models, or to make use of increasing capacity of FPGAs. Interconnection network between arithmetic circuits and multiple simulation circuits aims to per-form a data-driven multi-threading simulation. Approximately 8 times speedup was obtained compared to an execution on Xeon 2.80GHz.

关键词： field programmable gate arrays (FPGA)

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Latency Insensitive Design Styles for FPGAs 28

Latency Insensitive Design Styles for FPGAs

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28th international conference on field programmable logic and applications (FPL)

作者： Abbas, Mustafa Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Long distance interconnect delays are not scaling well with process technology, thereby leading to long routes strongly impacting the critical path of large FPGA designs. this forces the designer to pipeline long connections, which necessitates time consuming logic redesign in traditional latency sensitive systems. Latency-insensitive design (LID) is an increasingly attractive alternative as the typical latency of long distance interconnect grows, since LID decouples the design of the interconnect from that of the computational modules. By doing so, LID simplifies timing closure, improves forward compatibility (migration of systems to future FPGAs) and makes automated system-level pipelining feasible. Modern FPGAs, such as Stratix 10 which includes pipelined interconnect, make it difficult to use traditional LID solutions without significant area and frequency overhead. We present two LID styles that are more suitable for FPGAs and compare them to traditional LID. Our best system gained 2x area efficiency and 18% speed efficiency over traditional LID. Additionally, our designs come at a minimal speed overhead of only 3% compared to that of a latency-sensitive design.

关键词： Registers field programmable gate arrays Pipeline processing Timing Relays Integrated circuit interconnections Clocks

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RECOBUS-BUILDER - A NOVEL TOOL AND TECHNIQUE TO BUILD STATICALLY AND DYNAMICALLY RECONFIGURABLE SYSTEMS FOR FPGAS

RECOBUS-BUILDER - A NOVEL TOOL AND TECHNIQUE TO BUILD STATIC...

引用

18th international conference on field programmable and logic applications

作者： Koch, Dirk Beckhoff, Christian Teich, Juergen Univ Erlangen Nurnberg Dept Comp Sci D-8520 Erlangen Germany

ISBN: (纸本)9781424419609

In this paper, we present the ReCoBus-Builder tool chain that simplifies the generation of dynamically reconfigurable systems to almost a push-button process. the generated systems provide one or more resource areas that will be used by different partially reconfigurable modules at runtime. It is possible to integrate multiple partially reconfigurable modules into the same resource area at the same time and these modules can communicate via a fixed bus infrastructure or dedicated point-to-point links with other parts of the system. this allows building encapsulated modules that will be integrated into the system by linking together bitstreams at runtime. We will demonstrate that bitstream linking can further be used to speed up the design process of static only systems by eliminating long synthesis runs or place and route steps, when only small portions of a design are exchanged.

关键词： field programmable gate arrays (FPGA)

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