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Research and implementation of an automatic simulation tool

Research and implementation of an automatic simulation tool

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international conference on Dependable Systems and their applications (DSA)

作者： Liu Tang You Li Hongwei Wang Huan Zhao Luze Ma Yuming Sun Beijing Sunwise Information Technology Ltd. China

ISBN: (数字)9780738124223

ISBN: (纸本)9781665419536

With the rapidly increasing of space missions, FPGA is more widely used for its ability of single chip approaching 10 million gates of logic and 10 million bits of memory. More and more challenges are posed to FPGA design and verification, with the characteristics of a tight schedule, a burdensome task, momentous responsibilities, etc. A reusable and robust environment for verification is needed to improve the efficiency and quality of verification. In this paper, we present a series of research works, including what kinds of simulation techniques should be used and which methodology should be addressed. By using the Universal Verification Methodology (UVM) template, the verification modeling is done by us, and verification code is generated with FPGA automatic simulation tool (SunwiseFAS). the performance of this tool on automatic constructing simulation environment is presented, too.

关键词： Schedules Space missions Tools logic gates Task analysis field programmable gate arrays

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FPGA based Hybrid Random Number Generators

FPGA based Hybrid Random Number Generators

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international conference of Electronics, Communication and Aerospace Technology (ICECA)

作者： G.R. MahendraBabu K.P. Sridhar Baskar Karpagam Academy of Higher Education Coimbatore

ISBN: (数字)9781728163871

ISBN: (纸本)9781728163888

In this digital era, Pseudo-random number generators (PRNGs) are widely used in several real-time applications. As many types of PRNG are available, the feedback shift register method remains as the popular one. Despite the hype, these methods are unable to produce reliable data due to the presence of repetitive patterns in the sequence. this research work overcomes the aforementioned challenges by developing a hybrid technique. Entropy concept is used to improve the PRNGs quality. Since, Hybrid PRNGs pass in the testing, they can be implemented in real-time applications.

关键词： field programmable gate arrays Generators Hybrid power systems Testing Power demand logic gates Linear feedback shift registers

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ZuCl: A ZynQ ultrascale+ framework for OpenCL HLS applications 5

ZuCl: A ZynQ ultrascale+ framework for OpenCL HLS applicatio...

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5th international Workshop on FPGAs for Software Programmers, FSP 2018, co-located with international conference on field programmable logic and applications, FPL 2018

作者： Pham, Khoa Dang Vaishnav, Anuj Vesper, Malte Koch, Dirk School of Computer Science University of Manchester Manchester United Kingdom

ISBN: (纸本)9783800747238

In this work, we are proposing the ZUCL framework for implementing and running OpenCL applications for the latest Xilinx ZYNQ UltraScale+ platform. ZUCL is a holistic framework addressing the FPGA OS infrastructure, high level synthesis (HLS) module implementation as well as the runtime management. ZUCL enables partial reconfiguration (PR) on this platform by providing an infrastructure featuring multiple adjacent PR regions having an identical resource layout. this allows users building their hardware modules once but instantiating them multiple times in the provided regions in a hot plug-and-play manner as well as implementing different sized modules that can share the reconfigurable resources. An automatic physical implementation backend based on templates allows implementing OpenCL kernels into hardware modules all the way from OpenCL descriptions to relocatable accelerator bitstreams in a fully software-centric design process. Finally, prototypes of generic device drivers for OpenCL kernels and a hardware task scheduler together with low-level configuration drivers have been developed to manage kernels at runtime. A demonstrator on a Xilinx ZCU102 evaluation board will show how multiple OpenCL kernels can be implemented and executed simultaneously with ease and flexibility by a ZYNQ UltraScale+ platform under direct control of the ARM SoC running Linux. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： High level synthesis

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the FogDevices platform - a comprehensive hardware solution for IoT applications 16th

The FogDevices platform - a comprehensive hardware solution ...

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16th international-Federation-of-Automatic-Control (IFAC) conference on programmable Devices and Embedded Systems PDES

作者： Brzoza-Woch, Robert Szydlo, Tomasz Windak, Mateusz Sendorek, Joanna AGH Univ Sci & Technol Dept Comp Sci Mickiewicza 30 PL-30059 Krakow Poland

this article presents the FogDevices hardware platform. It is a comprehensive set of concepts, approaches, and solutions for fast and effective IoT node hardware and software development. the proposed solution may contribute to more effective embedded IoT node software development by providing a unique tool for emulating environmental conditions. It is especially useful in development and testing of advanced data processing algorithms and operation logic for environmental conditions monitoring. By using the discussed approach, engineers can set up highly customized IoT hardware for operation in specific usage scenarios but without an excessive amount of work. the complete functional, electrical, and mechanical solution is presented along with multiple test results of its practical implementation. (C) 2019, IFAC (international Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Prototyping IoT Hardware Protocols Sensors Actuators Embedded systems Automation

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CRAM: Robust Medium Access Control for LPWAN using Cryptographic Frequency Hopping

CRAM: Robust Medium Access Control for LPWAN using Cryptogra...

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international conference on Distributed Computing in Sensor Systems (DCOSS)

作者： Absar-Ul-Haque Ahmar Emekcan Aras thien Duc Nguyen Sam Michiels Wouter Joosen Danny Hughes imec-DistriNet Computer Science KU Leuven Belgium

ISBN: (数字)9781728143514

ISBN: (纸本)9781728198040

Low power wide area networks (LPWANs) are being applied in many Internet of things applications around the globe. these technologies offer economic coverage of wide areas, while retaining low power operation. LoRaWAN is a key technology in this space, with a world-wide presence and millions of devices deployed in the field. Despite this early success, recent research has shown that LoRa performs poorly in dense deployments with a high degree of contention. Furthermore, LoRa is not robust against selective jamming attacks. In this paper, we propose CRAM: a cryptographic frequency hopping MAC protocol designed for the LoRa physical layer that reduces contention by fairly exploiting all available frequency space, while making it significantly more difficult to perform selective jamming. Our evaluation shows that CRAM significantly reduces contention, thereby dramatically increasing scalability and reliability in comparison to the standard LoRa protocol.

关键词： Media Access Protocol logic gates Standards Jamming Cryptography Physical layer

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field programmable gate array hardware accelerator of prime implicants generation for single-output boolean functions minimization 17

Field programmable gate array hardware accelerator of prime ...

引用

17th IEEE international conference on Emerging eLearning Technologies and applications, ICETA 2019

作者： Mados, B. Bilanova, Z. Chovancova, E. Adam, N. Technical University of Košice Department of Computers and Informatics Faculty of Electrical Engineering and Informatics Košice04200 Slovakia

ISBN: (纸本)9781728149677

the paper deals with the problematics of two-level single-output Boolean functions minimization which is important for many fields of science and technology including logic and control systems design, software engineering, artificial intelligence and others. In this work proposed solution, which is aimed to the production of prime implicants for particular Boolean functions, as the first step of Boolean functions minimization, is based on the use of designed hardware accelerator using field programmable Gate Array (FPGA) technology. As the part of this work, input and output binary vectors encoding is proposed along with the combinational logic module, described using VHDL. Module is implemented into Xilinx Kintex-7 FPGA KC705 Evaluation Kit evaluation board. Advantage of proposed hardware accelerator is in extremely small time complexity in comparison to the algorithms which are utilizing classical CPU based solutions. Another advantage is in constant time of prime implicants generation in case of the same number of input variables of Boolean function regardless of ON set cardinality. Disadvantage of the solution is that it is not possible to define don't care set and in space complexity which is rising quickly according to the number of input variables of Boolean function. © 2019 IEEE.

关键词： Boolean functions

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Hamamu: Specializing FPGAs for ML applications by Adding Hard Matrix Multiplier Blocks

Hamamu: Specializing FPGAs for ML Applications by Adding Har...

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international conference on Application Specific Systems (ASAP), Architectures and Processors

作者： Aman Arora Zhigang Wei Lizy K. John Department of Electrical and Computer Engineering The University of Texas Austin

ISBN: (数字)9781728171470

ISBN: (纸本)9781728172798

Designing efficient hardware for accelerating artificial intelligence (AI) and machine learning (ML) applications is a major challenge. Rapidly changing algorithms and neural network architectures make FPGA based designs an attractive solution. But the generic building blocks available in current FPGAs (logic Blocks (LBs), multipliers, DSP blocks) limit the acceleration that can be achieved. We propose Hamamu, a modification to the current FPGA architecture that makes FPGAs specialized for ML applications. Specifically, we propose adding hard matrix multiplier blocks (matmuls) into the FPGA fabric. these matmuls are implemented using systolic arrays of MACs (Multiply-And-Accumulate) and can be connected using programmable direct interconnect between neighboring matmuls to make larger systolic matrix multipliers. We explore various matmul sizes ($2\times 2\times 2$, $4\times 4\times 4$, $8\times 8\times 8$, $16\times 16\times 16$) and various strategies to place these blocks on the FPGA (Columnar, Surround, Hybrid). We find that providing $4\times 4\times 4$ hard matrix multiplier blocks in an FPGA speeds up neural networks from MLPerf benchmarks by up to $\sim 3.9x$, compared to a Stratix-10 like FPGA with equal number of MACs, same MAC architecture and high DSP:LB ratio. Although the flexibility of the FPGA will reduce for non-ML applications, an FPGA with hard matrix multipliers is a faster, and more area efficient hardware accelerator for ML applications, compared to current FPGAs.

关键词： field programmable gate arrays Random access memory Computer architecture Acceleration Machine learning Matrix converters Program processors

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FPGA virtualization deployment based on Docker container technology

FPGA virtualization deployment based on Docker container tec...

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international conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Xiangmeng Long Baohua Liu Feng Jiang Qingjie Zhang Xiaoli Zhi School of Computer Engineering and Science Shanghai University Shanghai China

FPGA (field programmable Gate Array) has special advantages in low latency, low power consumption and reconfigurable hardware as compared with CPU and GPU. It is deployed as heterogeneous accelerators on a large scale in cloud computing centers and research laboratories. Usually., developers operate directly on the physical machines and use the FPGA card exclusively. this leads to a bad utilization of FPGA resources. this paper proposes to virtualize and deploy FPGA resources as lightweight containers by using Docker and Kubernetes together. the Docker containers abstract FPGA resources and provide an isolated runtime environment for each application. the Kubernetes performs unified and automated scaling and scheduling of virtualized FPGA containers. thus, FPGA resources can be safely and effectively shared among multiple local and remote applications. Experiments show that the utilization of FPGA resources has been improved.

关键词： Runtime environment Cloud computing Power demand Laboratories Graphics processing units Containers logic gates

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A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs 28

A Demo of FPGA Aggressive Voltage Downscaling: Power and Rel...

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28th international conference on field programmable logic and applications (FPL)

作者： Salami, Behzad Unsal, Osman Cristal, Adrian BSC Barcelona Spain UPC Barcelona Spain

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the power consumption of digital circuits, e.g., field programmable Gate Arrays (FPGAs), is directly related to their operating supply voltages. On the other hand, usually, chip vendors introduce a conservative voltage guardband below the standard nominal level to ensure the correct functionality of the design in worst-case process and environmental scenarios. For instance, this voltage guardband is empirically measured to be 12%, 20%, and 16% of the nominal level in commercial CPUs [1], Graphics Processing Units (GPUs) [2], and Dynamic RAMs (DRAMs) [3], respectively. However, in many real-world applications, this guardband is extremely conservative and eliminating it can result in significant power savings without any overhead. Motivated by these studies, we aim to extend the undevolting technique to commercial FPGAs. Toward this goal, we will practically demonstrate the voltage guardband for a representative Xilinx FPGA, with a preliminary concentration on on-chip memories, or Block RAMs (BRAMs).

关键词： field programmable gate arrays Random access memory Voltage control Reliability Voltage measurement System-on-chip Circuit faults

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FLS-Based Collision Avoidance Cyber Physical System for Warehouse Robots using FPGA 6

FLS-Based Collision Avoidance Cyber Physical System for Ware...

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6th international conference on Dependable Systems and their applications, DSA 2019

作者： Ahmed, Hossam O. Kuwait Kuwait

ISBN: (纸本)9781728160573

the overperforming enormous number of Automated Guided Vehicles (AGV) that have been adopted in warehouses recently proved their capabilities of speeding up the parcel exchange process in comparing with human capabilities. In order to increase the overall performance of these AGVs, we introduced an Artificial Intelligence (AI) based processing unit for the purpose of enhancing the collaborative diagnostics and decision making in such applications by exchanging feedback data frames to the center hub. the proposed AI-based controller is based on a multi-core Fuzzy logic System (FLS) is to differentiate the level of collision probability in a Cyber Physical System (CPS) using asymmetric data bus width architecture. the proposed systolic FLS architecture in this paper has been designed using VHDL to be interfaced with a three TFmini Plus Lidar Sensors and three MaxSonar ultrasonic sensors using the Intel Altera OpenVINO FPGA board. the proposed systolic FLS processing unit achieved a processing computational speed of about 14.36 GOPS at maximum operating frequency of 270.86 MHz while consuming about 58.56 mW as a core dynamic thermal power dissipation and around 28.38 mW as a 1/0 thermal power dissipation. © 2020 IEEE.

关键词： field programmable gate arrays (FPGA)

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