检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,085 篇 会议
31 篇 期刊文献
4 册 图书

馆藏范围

2,120 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,363 篇 工学
- 1,143 篇 计算机科学与技术...
- 757 篇 软件工程
- 452 篇 电气工程
- 226 篇 电子科学与技术（可...
- 90 篇 信息与通信工程
- 79 篇 控制科学与工程
- 41 篇 机械工程
- 38 篇 仪器科学与技术
- 32 篇 动力工程及工程热...
- 29 篇 建筑学
- 19 篇 土木工程
- 19 篇 生物工程
- 17 篇 核科学与技术
- 15 篇 光学工程
- 13 篇 生物医学工程（可授...
- 9 篇 材料科学与工程（可...
- 9 篇 安全科学与工程
- 8 篇 交通运输工程
- 6 篇 石油与天然气工程
181 篇 理学
- 104 篇 数学
- 43 篇 物理学
- 22 篇 生物学
- 20 篇 系统科学
- 13 篇 统计学（可授理学、...
- 8 篇 化学
53 篇 管理学
- 41 篇 管理科学与工程(可...
- 21 篇 工商管理
- 15 篇 图书情报与档案管...
17 篇 法学
- 15 篇 社会学
13 篇 医学
11 篇 经济学
- 11 篇 应用经济学
6 篇 军事学
5 篇 农学
3 篇 教育学

主题

945 篇 field programmab...
735 篇 field programmab...
322 篇 hardware
172 篇 computer archite...
145 篇 logic gates
130 篇 table lookup
115 篇 clocks
96 篇 throughput
94 篇 random access me...
85 篇 routing
82 篇 software
80 篇 acceleration
75 篇 delays
73 篇 optimization
67 篇 kernel
62 篇 switches
61 篇 registers
61 篇 logic
56 篇 algorithm design...
52 篇 parallel process...

机构

17 篇 univ toronto dep...
9 篇 imperial coll lo...
9 篇 ecole polytech f...
8 篇 department of co...
8 篇 tokyo inst techn...
7 篇 univ british col...
7 篇 school of comput...
7 篇 brigham young un...
7 篇 imperial coll lo...
6 篇 univ tsukuba tsu...
6 篇 xilinx inc 2100 ...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 department of el...
5 篇 fudan univ state...

作者

31 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
13 篇 ienne paolo
12 篇 wayne luk
12 篇 wilton steven j....
12 篇 betz vaughn
11 篇 fahmy suhaib a.
11 篇 cheung peter y. ...
11 篇 chow paul
10 篇 constantinides g...
9 篇 vaughn betz
9 篇 prasanna viktor ...
8 篇 kapre nachiket
8 篇 suhaib a. fahmy
8 篇 alonso gustavo
8 篇 hutchings brad
8 篇 paolo ienne
8 篇 habib mehrez
8 篇 amano hideharu

语言

2,105 篇 英文
9 篇 其他
5 篇 中文
1 篇 俄文

检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

共 2120 条记录，以下是371-380 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A Tile-based Fused-Layer Approach to Accelerate DCNNs on Low-Density FPGAs 26

A Tile-based Fused-Layer Approach to Accelerate DCNNs on Low...

引用

26th IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Erdem, Ahmet Babic, Danijela Silvano, Cristina Politecn Milan Milan Italy

ISBN: (纸本)9781728109961

Accelerating Deep Convolutional Neural Networks on FPGAs is achieving a lot of interest across a wide range of applications such as image recognition and classification. Although memory requirement still represents a challenge for fast and efficient inference workloads, fused-accelerated layers have been recently proposed to mitigate memory bandwidth problems. In this scenario, we propose a tiled-based fused-layer approach to exploit temporal and spatial locality in mapping a DCNN to a specialized low-density FPGA. In our tile-based approach, we propose applying a fusing depth of two convolutional layers in order to fit into a low-density FPGA without affecting the performance, while reducing the memory bandwidth. We demonstrated the effectiveness of our two-fused layer approach to accelerate the VGG16 network on a Zynq-7020. We achieved an average speedup of 1.44x times, while saving up to 61% of memory transactions with respect to a baseline represented by tiled-only (not-fused) version. A tiled-based fully-fused version of VGG16 would not have been feasible to be mapped on a low-density Zynq-7020.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

A CNN Accelerator on FPGA with a Flexible Structure

A CNN Accelerator on FPGA with a Flexible Structure

引用

international conference on Computational Intelligence and applications (ICCIA)

作者： Dan Shan Guotao Cong Wei Lu Department of Electronic Engineering Dalian Neusoft University of Information Dalian P. R. China School of Control Science and Engineering Dalian University of Technology Dalian P. R. China

ISBN: (数字)9781728160429

ISBN: (纸本)9781728160436

Most of the existing convolutional neural networks (CNNs) are based on PC software, which cannot meet the real-time, low power and miniaturization requirements of the systems. In this paper, a CNN accelerator with flexible structure based on field-programmable Gate Array (FPGA) is proposed to achieve recognition of MNIST handwritten numeric characters. the system adopts deep pipeline processing and optimizes inter-layer and intra-layer parallelism from two levels of coarse and fine granularity. In view of the similarity of convolution structure, this design adopts structured circuit, which can easily expand the number of layers and neurons. the classification throughput and inter-layer data throughput capability can be improved by rationally organizing the internal memory resources of the FPGA. Compared with the general CPU, it achieves 3 times acceleration at 50MHz frequency, while the power consumption is only 2% of the CPU. Finally performance and power consumption are compared with other accelerators by VGG16.

关键词： Convolution Neurons field programmable gate arrays Parallel processing Kernel Computer architecture System-on-chip

来源：评论

学校读者我要写书评

暂无评论

Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems 28

Facilitating Easier Access to FPGAs in the Heterogeneous Clo...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Minhas, Umar Ibrahim Woods, Roger Karakonstantis, Georgios Queens Univ Belfast Belfast Antrim North Ireland

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

With FPGAs being increasingly integrated into existing software-based heterogeneous cloud environments, novel evaluation mechanisms are required to reveal the energy performance trade-offs of accelerators (FPGAs, GPUs, etc) in high-level heterogeneous programming environments. For FPGAs, this involves also a reconsideration of scheduling policies and reconfiguration methods with an aim of integrating software based approaches as well as performance optimizations for wider workload sizes. the approaches are evaluated using various reconfiguration methodologies for a number of applications.

关键词： Task analysis field programmable gate arrays Graphics processing units Cloud computing Optimization Computational modeling throughput

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Triple Event Upset Tolerant Area-Efficient FPGA-Based System for Space applications And Nuclear Plants

Work-in-Progress: Triple Event Upset Tolerant Area-Efficient...

引用

IEEE international Workshop on Factory Communication Systems (WFCS)

作者： Beatrice Shokry Dina G. Mahmoud Hassanein H. Amer Maha Shatta Gehad I. Alkady Ramez M. Daoud Ihab Adly Manar N. Shaker Tarek Refaat Electronics and Communications Engineering Department The American University in Cairo Cairo Egypt Electrical Eng. Dept. The British University in Egypt (BUE) Cairo Egypt Electronics and Communications Engineering Department Cairo University Cairo Egypt Engineering Department Cisco Systems Inc. Ottawa ON Canada

ISBN: (数字)9781728152974

ISBN: (纸本)9781728152981

this paper focuses on FPGA-based systems in the context of space applications and nuclear plants which are extremely harsh environments. In such environments, the probability of occurrence of Multiple Event Upsets (MEUs) is not negligible. Conventional fault-tolerant architectures (such as Triple Modular Redundancy) will NOT be able to handle Triple Event Upsets (TEUs) for example. A fault-tolerant architecture with only six identical modules is developed in this paper even though, intuitively, at least seven modules are required for a system to recover from a TEU. It is proven that the proposed architecture can fully recover from any sequence of Single, Double or Triple Event Upsets by using Dynamic Partial Reconfiguration. If a hard fault affects one of the modules, the architecture will lose some of its fault tolerance but may be able to continue operating correctly depending on the nature of the next fault.

关键词： FPGA Fault Tolerance TEUs hard fault space applications nuclear plants Triple Duplex Space applications Nuclear powerplants Fault tolerance hard breakdown field programmable gate arrays Upset Harsh environments triple modular redundancy

来源：评论

学校读者我要写书评

暂无评论

Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs 28

Enabling Low Impact, Rapid Debug for Highly Utilized FPGA De...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Hale, Robert Hutchings, Brad Brigham Young Univ Provo UT 84602 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Inserting soft logic analyzers into FPGA circuits is a common way to provide signal visibility at run-time, helping users locate bugs in their designs. However, this can become infeasible for highly (70-90+%) utilized designs, which leave few logic resources or block RAMs available for internal logic analyzers. this paper presents a fast, low-impact method of enabling signal visibility in these situations using LUT-based distributed memory. Trace-buffers are inserted post-PAR allowing users to quickly change the set of observed nets. Results from routing-based experiments are presented which demonstrate that, even in highly utilized designs, many design signals can be observed with this technique.

关键词： Tools field programmable gate arrays Probes Table lookup Debugging Routing

来源：评论

学校读者我要写书评

暂无评论

When FPGA-accelerator meets Stream Data Processing in the Edge 39

When FPGA-accelerator meets Stream Data Processing in the Ed...

引用

39th IEEE international conference on Distributed Computing Systems (ICDCS)

作者： Wu, Song Hu, Die Ibrahim, Shadi Jin, Hai Xiao, Jiang Chen, Fei Liu, Haikun Huazhong Univ Sci & Technol Sch Comp Sci & Technol Natl Engn Res Ctr Big Data Technol & Syst Serv Comp Technol & Syst LabCluster & Grid Comp Wuhan Peoples R China INRIA IMT Atlantique LS2N Nantes France

ISBN: (纸本)9781728125190

Today, stream data applications represent the killer applications for Edge computing: placing computation close to the data source facilitates real-time analysis. Previous efforts have focused on introducing light-weight distributed stream processing (DSP) systems and dividing the computation between Edge servers and the clouds. Unfortunately, given the limited computation power of Edge servers, current efforts may fail in practice to achieve the desired latency of stream data applications. In this vision paper, we argue that by introducing FPGAs in Edge servers and integrating them into DSP systems, we might be able to realize stream data processing in Edge infrastructures. We demonstrate that through the design, implementation, and evaluation of F-Storm, an FPGA-accelerated and general-purpose distributed stream processing system on Edge servers. F-Storm integrates PCIe-based FPGAs into Edge-based stream processing systems and provides accelerators as a service for stream data applications. We evaluate F-Storm using different representative stream data applications. Our experiments show that compared to Storm, F-Storm reduces the latency by 36% and 75% for matrix multiplication and grep application. It also obtains 1.4x and 2.1x improvement for these two applications, respectively. We expect this work to accelerate progress in this domain.

关键词： field programmable gate arrays Servers Big Data applications Task analysis Cloud computing Sparks

来源：评论

学校读者我要写书评

暂无评论

Multi-Fidelity Optimization for High-Level Synthesis Directives 28

Multi-Fidelity Optimization for High-Level Synthesis Directi...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Lo, Charles Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

High-Level Synthesis (HLS) tools enable rapid hardware development, but design expertise and effort are necessary to tune the high-level descriptions into optimized circuits. To improve designer productivity, automated design-space exploration techniques have been proposed. However, the optimization processes sample expensive CAD flows. In this paper, we adapt multi-fidelity optimization methods to incorporate low-fidelity estimates available in the FPGA CAD flow and speed up tuning of HLS parameters. We find that multi-fidelity optimization techniques can significantly reduce optimization time compared to previous approaches.

关键词： Optimization Solid modeling Clocks Tools Computational modeling field programmable gate arrays Hardware

来源：评论

学校读者我要写书评

暂无评论

CascadeC_NN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks 28

CascadeC<sub>NN</sub>: Pushing the Performance Limits of Qua...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Kouris, Alexandros Venieris, Stylianos I. Bouganis, Christos-Savvas Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

this work presents CascadeCNN, an automated toolflow that pushes the quantisation limits of any given CNN model, aiming to perform high-throughput inference. A two-stage architecture tailored for any given CNN-FPGA pair is generated, consisting of a low- and high-precision unit in a cascade. A confidence evaluation unit is employed to identify misclassified cases from the excessively low-precision unit and forward them to the high-precision unit for re-processing. Experiments demonstrate that the proposed toolflow can achieve a performance boost up to 55% for VGG-16 and 48% for AlexNet over the baseline design for the same resource budget and accuracy, without the need of retraining the model or accessing the training data.

关键词： Quantization (signal) Computational modeling field programmable gate arrays Hardware Task analysis Table lookup

来源：评论

学校读者我要写书评

暂无评论

An Application-Specific field-programmable Tree Ensemble Architecture 28

An Application-Specific Field-Programmable Tree Ensemble Arc...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Kuehn, Jan Manoli, Yiannos Univ Freiburg IMTEK Dept Microsyst Engn Freiburg Germany

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Supervised machine learning for data classification is increasingly implemented in hardware to be integrated close to the source of the data. the ability to update a trained machine learning model is the most important property any classification system must fulfill. this is often achieved by implementing the algorithm on reconfigurable hardware but some applications require speed, size, or power efficiency only application-specific integrated circuits (ASICs) can offer. Architectures that have proven to be very efficient on reconfigurable hardware are not always suited for custom ASIC designs. We therefore propose to integrate commonly used field-programmable technology in an application-specific architecture to allow updates of the trained model. this design pattern allows deep integration into full custom ASICs while leveraging all advantages of reconfigurable hardware.

关键词： Vegetation Integrated circuit modeling field programmable gate arrays Parallel architectures Hardware Decision trees

来源：评论

学校读者我要写书评

暂无评论

Towards Efficient Convolutional Neural Network for Domain-Specific applications on FPGA 28

Towards Efficient Convolutional Neural Network for Domain-Sp...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Zhao, Ruizhe Ng, Ho-Cheung Luk, Wayne Niu, Xinyu Imperial Coll London Dept Comp London England Corerain Technol Ltd Shenzhen Peoples R China

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGA becomes a popular technology for implementing Convolutional Neural Network (CNN) in recent years. Most CNN applications on FPGA are domain-specific, e.g., detecting objects from specific categories, in which commonly used CNN models pre-trained on general datasets may not be efficient enough. this paper presents TuRF, an end-to-end CNN acceleration framework to efficiently deploy domain-specific applications on FPGA by transfer learning that adapts pre-trained models to specific domains, replacing standard convolution layers with efficient convolution blocks, and applying layer fusion to enhance hardware design performance. We evaluate TuRF by deploying a pre-trained VGG-16 model for a domain-specific image recognition task onto a Stratix V FPGA. Results show that designs generated by TuRF achieve better performance than prior methods for the original VGG-16 and ResNet-50 models, while for the optimised VGG-16 model TuRF designs are more accurate and easier to process.

关键词： Convolution field programmable gate arrays Standards Hardware Acceleration Task analysis Kernel

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共212页 << < 34 35 36 37 38 39 40 41 42 43 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：