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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

共 2120 条记录，以下是381-390 订阅

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A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based TDC for Low Power and Low Resource Usage applications 5

A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based...

引用

5th international conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)

作者： Wu, Jinyuan Xu, Jingjing Fermilab Natl Accelerator Lab Batavia IL 60510 USA Purdue Univ 610 Purdue Mall W Lafayette IN 47907 USA

ISBN: (纸本)9781728123226

In common digital electronics design practice, combinatorial loop is less preferable, especially in the multi-bit cases. An exception of multi-bit feedback system that is allowed to be implemented in combinatorial loop is the Gray code sequence generator. the Gray code sequence generator runs by itself without being driven by an external clock. It steps through Gray code sequence significantly faster than the Gray code counter under the same silicon technology. In high energy physics experiments, it is necessary to find a low resource usage and low power TDC (Time-to-Digital-Converter) scheme for high channel count detectors. A Gray code oscillator based TDC is a good candidate for such a scheme. In this paper, we describe our work of design and implementation of a TDC based on combinatorial Gray code oscillator in a Xilinx Kintex-7 FPGA (field-programmable Gate Array). the implementation and test results are presented. the test result shows that the TDC using only 8 logic elements is able to reach a RMS precision of 160 ps for time difference measurements of a single pulse. the single pulse measurement precision can be further improved to 51 ps with the weighted average scheme using data from the same TDC channels captured by 4 consecutive system clock edges.

关键词： Time to Digital Converter Gray Code Oscillator FPGA applications

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Placement Strategies for 2.5D FPGA Fabric Architectures 28

Placement Strategies for 2.5D FPGA Fabric Architectures

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28th international conference on field programmable logic and applications (FPL)

作者： Ravishankar, Chirag Gaitonde, Dinesh Bauer, Trevor Xilinx Inc 3100 Logic Dr Longmont CO 80503 USA Xilinx Inc 2100 Logic Dr San Jose CA USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs take advantage of 2.5D stacking technology to manufacture large capacity and high performance heterogenous devices at reasonable costs. EDA tools need to be aware of and exploit physical characteristics of such devices, for example the reduced connection count between SLRs, the infrequency of SLL channel occurence in the fabric, and the aspect ratios of individual SLRs. We implement a partition driven placer to explore various EDA options to take advantage of architectural features in 2.5D FPGAs. We improve the routability of designs by optimizing the placer for discrete SLL channels and reduced connection counts. We propose a cut schedule for the partitioner to orient the placement with awareness of the aspect ratio of SLRs to improve track demands within each SLR.

关键词： field programmable gate arrays Routing Stacking Wires Fabrics Complexity theory Heating systems

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Multipumping-Enabled Multiported SRAM Based Efficient TCAM Design

Multipumping-Enabled Multiported SRAM Based Efficient TCAM D...

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Ashwin Santhosh Sonali Agrawal Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9781728192871

ISBN: (纸本)9781728192888

Memory which is used for searching applications, like Network routers, operating at a higher speed is called Ternary Content Addressable Memory (TCAM). the requirement of TCAM is gradually growing in the searching field applications. TCAM memories are usually built in ASIC (Application Specific Integrated Circuit) which offers searching operation at a higher speed in a predetermined time but is expensive in cost. TCAMs designed on FPGAs (field programmable Gate Array) experience high power consumption, larger use of FPGA resources, and suffer from the inefficiency of storage. TCAM using multipumping and multiported SRAM is designed for achieving an effectual use of FPGA resources, and a reduction in usage of power and area. In the present SRAM based TCAM designs, there is an exponential growth in memory usage due to the increase in the patterns of TCAM, which is reduced by cascading the multiple blocks of SRAM (BRAMs) in FPGA that makes growth linear. BRAMs of FPGAs have restrictions in depth, which restricts the effectual storage of TCAM bits. In this paper, a modified TCAM design is proposed which avoids this restriction by using shallow sub-blocking of BRAMs. the design proposed in this paper operates the multiported SRAM by using the dual-port BRAM and by clocking it internally at a higher frequency using multipumping technique which allows access of the BRAM subblocks in one cycle of the system clock. these modifications in the divisional traditional TCAM table results in an effectual design of TCAM memory. the proposed design is coded in Verilog and simulated using the Xilinx ISE tool and was implemented on a Virtex 7xc7vx485 FPGA device. the proposed design has better performance, in terms of 26% reduction in power and 7% reduction in area, as compared to existing SRAM based TCAM design.

关键词： Random access memory field programmable gate arrays Clocks logic gates Multiplexing Memory management Associative memory

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Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAs

Stealthy-Shutdown: Practical Remote Power Attacks in Multi -...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Yukui Luo Cheng Gongye Shaolei Ren Yunsi Fei Xiaolin Xu Northeastern University MA USA University of California Riverside CA USA

ISBN: (数字)9781728197104

ISBN: (纸本)9781728197111

With the deployment of artificial intelligent (AI) algorithms in a large variety of applications, there creates an increasing need for high-performance computing capabilities. As a result, different hardware platforms have been utilized for acceleration purposes. Among these hardware-based accelerators, the field-programmable gate arrays (FPGAs) have gained a lot of attention due to their re-programmable characteristics, which provide customized control logic and computing operators. For example, FPGAs have recently been adopted for on-demand cloud services by the leading cloud providers like Amazon and Microsoft, providing acceleration for various compute-intensive tasks. While the co-residency of multiple tenants on a cloud FPGA chip increases the efficiency of resource utilization, it also creates unique attack surfaces that are under-explored. In this paper, we exploit the vulnerability associated with the shared power distribution network on cloud FPGAs. We present a stealthy power attack that can be remotely launched by a malicious tenant, shutting down the entire chip and resulting in denial-of-service for other co-located benign tenants. Specifically, we propose stealthy-shutdown: a well-timed power attack that can be implemented in two steps: (1) an attacker monitors the realtime FPGA power-consumption detected by ring-oscillator-based voltage sensors, and (2) when capturing high power-consuming moments, i.e., the power consumption by other tenants is above a certain threshold, she/he injects a well-timed power load to shut down the FPGA system. Note that in the proposed attack strategy, the power load injected by the attacker only accounts for a small portion of the overall power consumption; therefore, such attack strategy remains stealthy to the cloud FPGA operator. We successfully implement and validate the proposed attack on three FPGA evaluation kits with running real-world applications. the proposed attack results in a stealthy-shutdown, demonstratin

关键词： Power demand Tools threshold voltage Sensors Acceleration Task analysis field programmable gate arrays

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A Smart Network Interface Approach for Distributed applications on Xilinx Zynq SoCs 28

A Smart Network Interface Approach for Distributed Applicati...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Shreejith, Shanker Cooke, Ryan A. Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Networked embedded systems have seen tremendous growth with many more complex critical and non-critical systems exchanging information over networks of various types. At each node, information is processed by the network stack before the application sees the data. Large portions of the stack are in software, resulting in significant and non-deterministic delays. While hybrid compute platforms like the Xilinx Zynq can accelerate processing tasks through offloading to programmable logic, the delays incurred due to connectivity can significantly impact overall application latency. In this paper, we present a smart network interface approach for the Xilinx Zynq platform based on datapath extensions within the otherwise standard Ethernet interface. We show that this approach improves computation offload latency by 24-27% and throughput by 37% for a complex computational kernel.

关键词： Ethernet Network interfaces Hardware Random access memory Software Registers Monitoring

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Feasibility and Design Trade-Offs of Neural Network Accelerators Implemented on Reconfigurable Hardware 6th

Feasibility and Design Trade-Offs of Neural Network Accelera...

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6th EAI international conference on Industrial Networks and Intelligent Systems, INISCOM 2020

作者： Trinh, Quang-Kien Duong, Quang-Manh Dao, thi-Nga Nguyen, Van-thanh Nguyen, Hong-Phong Le Quy Don Technical University Hanoi Viet Nam Posts and Telecommunications Institute of Technology Hanoi Viet Nam

ISBN: (纸本)9783030630829

In recent years, neural networks based algorithms have been widely applied in computer vision applications. FPGA technology emerges as a promising choice for hardware acceleration owing to high-performance and flexibility;energy-efficiency compared to CPU and GPU;fast development round. FPGA recently has gradually become a viable alternative to the GPU/CPU platform. this work conducts a study on the practical implementation of neural network accelerators based-on reconfigurable hardware (FPGA). this systematically analyzes utilization-accuracy-performance trade-offs in the hardware implementations of neural networks using FPGAs and discusses the feasibility of applying those designs in reality. We have developed a highly generic architecture for implementing a single neural network layer, which eventually permits further construct arbitrary networks. As a case study, we implemented a neural network accelerator on FPGA for MNIST and CIFAR-10 dataset. the major results indicate that the hardware design outperforms by at least 1500 times when the parallel coefficient p is 1 and maybe faster up to 20,000 times when that is 16 compared to the implementation on the software while the accuracy degradations in all cases are negligible, i.e., about 0.1% lower. Regarding resource utilization, modern FPGA undoubtedly can accommodate those designs, e.g., 2-layer design with p equals 4 for MNIST and CIFAR occupied 26% and 32% of LUT on Kintex-7 XC7K325T respectively. © 2020, ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering.

关键词： field programmable gate arrays (FPGA)

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Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECG applications in GF(p) 28

Revisiting FPGA Implementation of Montgomery Multiplier in R...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Roy, Debapriya Basu Mukhopadhyay, Debdeep Indian Inst Technol Kharagpur Dept Comp Sci & Engn Kharagpur W Bengal India

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

the fast implementations of ECC in GF(p) are generally implemented using specialized prime field, and henceforth, they are dependent on the structure of the prime. But, these implementations cannot be ported to generic curves which do not support such prime structures. Such generic curves are often used in various crypto-applications like pairing and post quantum secure supersingular isogeny based key exchange. In those cases, modular multiplication is executed through Montgomery multiplier which is slower compared to modular multiplication using specialized primes. this work aims to reduce the speed gap between Montgomery multiplication and modular multiplication in specialized prime field by presenting an efficient implementation of Montgomery multiplier on FPGA using the redundant number system.

关键词： Montgomery multiplier Redundant number system ECC

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FPGA Implementation of LDPC Encoder Architecture for Wireless Communication Standards

FPGA Implementation of LDPC Encoder Architecture for Wireles...

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international conference on Modern Circuits and Systems Technologies (MOCAST)

作者： Ruslan Goriushkin Pavel Nikishkin Aleksei Ovinnikov Evgeny Likhobabin Vladimir Vityazev Department of Telecommunications and foundations of radio engineering Ryazan State Radio Engineering University RSREU Ryazan Russia

ISBN: (数字)9781728166872

ISBN: (纸本)9781728166889

In this paper a pipeline architecture is proposed for FPGA implementation of a quasi-cyclic LDPC (QC-LDPC) encoder. the results are provided for implementation on a Xilinx ZYNQ-7 ZC706 Evaluation Board for code with rate 5/6 and block lengths from 576 to 2304. the design is parameterized and can be easily rebuilt to support various code rates and code lengths. the base matrices H and code parameters are taken from the IEEE 802.16e standard. the number of logic elements (LUT), clock speed, and throughput of the encoder are presented for different code lengths. the throughput of up to 16 Gbps for IEEE 802.16e codes has been achieved.

关键词： Parity check codes throughput field programmable gate arrays Encoding IEEE 802.16 Standard Clocks

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Design Space Exploration Scheme for Mapping Convolutional Neural Network on Zynq Zedboard

Design Space Exploration Scheme for Mapping Convolutional Ne...

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international conference on Electronics, Computers and Artificial Intelligence (ECAI)

作者： M. Sohaib Ul Hassan Umar S. Khan Sajid Gul Khawaja Department of Mechatronics Engineering National University of Sciences and Technology Islamabad Pakistan Department of Computer Engineering National University of Sciences and Technology Islamabad Pakistan

ISBN: (数字)9781728168432

ISBN: (纸本)9781728168449

Convolutional Neural Network (CNN) is an important machine learning algorithm. Due to its broad applications and classification accuracy it has become hot topic in recent times. CNNs are both computationally expensive and have extensive memory accesses which has rendered it inefficient on general purpose computers. GPU implementations have improved the performance of algorithm but high energy consumption of GPUs doesn't allow its usage in robotics and mobile embedded platforms. In this paper we study the mapping of Convolutional Neural Networks on field programmable gate arrays (FPGAs). We implement a VGG-16 style network which are the most admired CNN architectures in community. We Used Xilinx Zynq Zedboard for analytical modeling and mapping of CNN. For a complete network implementation, we achieved a peak performance of 1.3 GMACCs at 120 MHz frequency. Our implementation achieves a speed up of 4 times compared to software implementation on General Purpose Computer.

关键词： field programmable gate arrays Computer architecture Convolutional neural networks Convolution Software Random access memory Hardware

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Accelerated Wire-Speed Packet Capture at 200 Gbps 28

Accelerated Wire-Speed Packet Capture at 200 Gbps

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28th international conference on field programmable logic and applications (FPL)

作者： Kekely, Lukas Spinler, Martin Friedl, Stepan Sikora, Jiri Korenek, Jan CESNET Ale Zikova 4 Prague 16000 Czech Republic

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We present our latest FPGA acceleration card NFB-200G2QL that is specifically designed to enable traffic processing at 200 Gbps. Unique high-speed DMA engines in the FPGA together with highly optimized Linux drivers enable data transfer through PCIe interfaces with minimal CPU overhead. Captured traffic can be independently distributed between individual cores of two physical CPUs (NUMA nodes) without utilization of QPI. As a result, wire-speed packet capture to the host memory from two fully saturated 100 Gbps Ethernet interfaces (QSFP28+ cages) is achieved and various network monitoring applications can utilize the power of the latest FPGAs and CPUs for data processing. this is especially useful when both directions of a single 100GbE link are monitored. the live demonstration shows how the packets are received from two 100 Gbps Ethernet links at wire-speed and captured to the host memory at 200 Gbps without a loss. the opposite direction of communication is also shown, i.e. how the packets are transmitted from the host memory and fully saturate the two 100GbE network interfaces. Achieved speeds are demonstrated by counters and gauges showing generated, received/transmitted and captured packets. We also show statistics of CPU load during the packet capture/transmission for different packet lengths.

关键词： field programmable gate arrays Ethernet throughput Data transfer Standards Acceleration Monitoring

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