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检索条件"任意字段=16th International Conference on Field Programmable Logic and Applications"

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Resource Elastic Virtualization for FPGAs using OpenCL 28

Resource Elastic Virtualization for FPGAs using OpenCL

引用

28th international conference on field programmable logic and applications (FPL)

作者： Vaishnav, Anuj Khoa Dang Pham Koch, Dirk Garside, James Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an approach to manage FPGA resources with OS functionality, this paper introduces the concept of resource elastic virtualization which allows shrinking and growing of accelerators in the spatial domain with the help of partial reconfiguration. With this, we can serve multiple applications simultaneously on the same FPGA and optimize the resource utilization and consequently the overall system performance. We demonstrate how an implementation of resource elasticity can be realized for OpenCL accelerators along with how it can achieve 23x better FPGA utilization and 49% better performance on average while simultaneously lowering waiting time for tasks.

关键词： field programmable gate arrays Task analysis Hardware Virtualization Resource management Elasticity Layout

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A High Performance Implementation of Quasi Delay Insensitive Booleans Functions 26

A High Performance Implementation of Quasi Delay Insensitive...

引用

IEEE 26th international conference on Electronics, Electrical Engineering and Computing (INTERCON)

作者： Oliveira, Duarte L. Verducci, Orlando Batista, Gracieth C. Curtinhas, Tiago S. Technol Inst Aeronaut ITA Elect Engn Div ILEA Sao Jose Dos Campos SP Brazil Adventist Univ Ctr Sao Paulo Unasp Dept Comp Sci Sao Paulo Brazil

ISBN: (纸本)9781728136462

Digital circuit design demands critical requirements such as power consumption, robustness, performance, etc. when it is implemented in VLSI (Very Large Scale Integration). the asynchronous paradigm presents interesting features aiming to solve these requirements. An important class of asynchronous paradigm is the so-called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for those kinds of applications because they are robust to noise, to temperature variations, to wire and gate delays and to supply voltage variation, having also low electromagnetic emissions. QDI combinational circuits are designed as function blocks whose indicatability shows the robustness of the circuit communication with the environment. this paper presents two architectures based on basic gates and C elements as also an approach to the synthesis of the QDI function blocks. the two new architectures were prototyped in FPGAs (field programmable Gated Array) devices, applied in a set of benchmarks and compared with other architectures of the literature. Our proposal shows respectively a gain of up to 18.6%, 53.1%, 40.7% and 51.8% in latency, number of LUTs and power, dynamic and static, respectively.

关键词： asynchronous logic QDI circuits dual-rail code

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Customizing Low-Precision Deep Neural Networks For FPGAs 28

Customizing Low-Precision Deep Neural Networks For FPGAs

引用

28th international conference on field programmable logic and applications (FPL)

作者： Faraone, Julian Gambardella, Giulio Boland, David Fraser, Nicholas Blott, Michaela Leong, Philip H. W. Univ Sydney Sydney NSW Australia Xilinx Res Labs Dublin Ireland

ISBN: (纸本)9781538685174

In this paper, we argue that instead of solely focusing on developing efficient architectures to accelerate well-known low-precision CNNs, we should also seek to modify the network to suit the FPGA. We develop a fully automative toolflow which focuses on modifying the network through filter pruning, such that it efficiently utilizes the FPGA hardware whilst satisfying a predefined accuracy threshold. Although fewer weights are removed in comparison to traditional pruning techniques designed for software implementations, the overall model complexity and feature map storage is greatly reduced. We implement the AlexNet and TinyYolo networks on the large-scale ImageNet and PascalVOC datasets, to demonstrate up to roughly 2x speedup in frames per second and 2x reduction in resource requirements over the original network, with equal or improved accuracy.

关键词： field programmable gate arrays Hardware Quantization (signal) throughput Memory management Neural networks

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Case for Fast FPGA Compilation using Partial Reconfiguration 28

Case for Fast FPGA Compilation using Partial Reconfiguration

引用

28th international conference on field programmable logic and applications (FPL)

作者： Park, Dongjoon Xiao, Yuanlong Magnezi, Nevo DeHon, Andre Univ Penn Dept Elect & Syst Engn Philadelphia PA 19104 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Despite the FPGA's advantages over other hardware platforms, long compilation time prevents FPGA engineers from efficiently exploring the design space and discourages new users who want to quickly iterate for debugging. To reduce compilation time, this work adopts a divide-and-conquer approach using Partial Reconfiguration with a Packet-Switched Fat-Tree network. Partially reconfigured leaves in the packet-switched network are independent from each other and can be compiled separately in parallel. Also, when a minor fix is required to a bitstream, only the corresponding leaves need to be incrementally compiled. Preliminary experimental evidence from our work-in-progress effort illustrates how a 30 minute full-chip compile time can be reduced to 7 minutes.

关键词： field programmable gate arrays Table lookup Overlay networks Runtime Tools Hardware Standards

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A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2) 28

A Demonstration of FPGA-based You Only Look Once version2 (Y...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Nakahara, Hiroki Shimoda, Masayuki Sato, Shimpei Tokyo Inst Technol Tokyo Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We implement the YOLO (You only look once) object detector on an FPGA, which is faster and has higher accuracy. It is based on the convolutional deep neural network (CNN), and it is a dominant part of both the performance and the area. It is widely used in the embedded systems, such as robotics, autonomous driving, security, and drones, all of which require high-performance and low-power consumption. A frame object detection problem consists of two problems: one is a regression problem to spatially separated bounding boxes, the second is the associated classification of the objects within realtime frame rate. We used the binary (1 bit) precision CNN for feature extraction and the half-precision (16 bit) precision CNN for both classification and localization. We implement a pipelined based architecture for the mixed-precision YOLOv2 on the Xilinx Inc. zcul02 board, which has the Xilinx Inc. Zynq Ultrascale+ MPSoC. the implemented object detector archived 35.71 frames per second (FPS), which is faster than the standard video speed (29.9 FPS). Compared with a CPU and a GPU, an FPGA based accelerator was superior in power performance efficiency. Our method is suitable for the frame object detector for an embedded vision system.

关键词： field programmable gate arrays Computer architecture Graphics processing units Detectors Feature extraction Training Neural networks

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Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model 28

Deterministic Parallel Routing for FPGAs based on Galois Par...

引用

28th international conference on field programmable logic and applications (FPL)

作者： Moctar, Yehdhih Stojilovic, Mirjana Brisk, Philip IBM Res Austin TX 78758 USA Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Lausanne Switzerland Univ Calif Riverside Riverside CA 92521 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

this paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel;and (2) routing one net at a time, while parallelizing the Maze Expansion step. Using eight threads running on eight cores, the two methods achieved speedups of 1.84 x and 3.67 x, respectively, compared to VPR's single threaded routability-driven router. Removing the determinism requirement increased these respective speedups to 2.67 x and 5.46 x, while sacrificing the guarantee of reproducible results.

关键词： Routing Nickel Instruction sets field programmable gate arrays Runtime Parallel processing Task analysis

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A Survey on FPGA Virtualization 28

A Survey on FPGA Virtualization

引用

28th international conference on field programmable logic and applications (FPL)

作者： Vaishnav, Anuj Khoa Dang Pham Koch, Dirk Univ Manchester Sch Comp Sci Manchester Lancs England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Consequently, FPGA virtualization methods and hardware infrastructures have frequently been proposed in both academia and industry for addressing multi-tenancy execution, multi-FPGA acceleration, flexibility, resource management and security. In this survey, we identify and classify the various techniques and approaches into three main categories: 1) Resource level, 2) Node level, and 3) Multi-node level. In addition, we identify current trends and developments and highlight important future directions for FPGA virtualization which require further work.

关键词： field programmable gate arrays Virtualization Computer architecture Software Hardware Fabrics Task analysis

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Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP applications

Low-Cost Approximate Constant Coefficient Hybrid Binary-Unar...

引用

Annual IEEE Symposium on field-programmable Custom Computing Machines (FCCM)

作者： S. Rasoul Faraji Pierre Abillama Kia Bazargan Department of ECE University of Minnesota Twin Cities Minneapolis MN USA

ISBN: (数字)9781728158037

ISBN: (纸本)9781728158044

Multipliers are used in virtually all Digital Signal Processing (DSP) applications, such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. the proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx logicORE IP CCMs and table-based KCM CCMs on average. We evaluate the proposed multipliers on 2-D discrete cosine transform and fast Fourier transform algorithms as two common DSP modules. Post-routing FPGA results show that the proposed multipliers can improve the {area × delay cost, and energy consumption per sample} of 8-bit fixed-point 2-D discrete cosine transform on average by {33%, 36%}. the improvement for 128-point 16-bit fixed-point fast Fourier transform on these metrics is {45%, 54%}. Moreover, the throughput of the proposed 2-D discrete cosine transform and 128-point fast Fourier transform architectures are on average 1.04× and 1.76× of the throughput of the binary architectures implemented using Xilinx logicORE IP CCMs, respectively.

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BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing 28

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay f...

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28th international conference on field programmable logic and applications (FPL)

作者： Umuroglu, Yaman Rasnayake, Lahiru Sjalander, Magnus Xilinx Res Labs Dublin Ireland Norwegian Univ Sci & Technol NTNU Dept Comp Sci Trondheim Norway NTNU Trondheim Norway

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Matrix-matrix multiplication is a key computational kernel for numerous applications in science and engineering, with ample parallelism and data locality that lends itself well to high-performance implementations. Many matrix multiplication dependent applications can use reduced-precision integer or fixedpoint representations to increase their performance and energy efficiency while still offering adequate quality of results. However, precision requirements may vary between different application phases or depend on input data, rendering constant-precision solutions ineffective. We present BISMO, a vectorized bit serial matrix multiplication overlay for reconfigurable computing. BISMO utilizes the excellent binary-operation performance of FPGAs to offer a matrix multiplication performance that scales with required precision and parallelism. We characterize the resource usage and performance of BISMO across a range of parameters to build a hardware cost model, and demonstrate a peak performance of 6.5 TOPS on the Xilinx PYNQ-Z1 board.

关键词： Hardware Mathematical model Synchronization Software Table lookup field programmable gate arrays

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Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs 28

Embracing Diversity: Enhanced DSP Blocks for Low-Precision D...

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28th international conference on field programmable logic and applications (FPL)

作者： Boutros, Andrew Yazdanshenas, Sadegh Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada Vector Inst Toronto ON Canada

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Use of reduced precisions in Deep Learning (DL) inference tasks has recently been shown to significantly improve accelerator performance and greatly reduce both model memory footprint and the required external memory bandwidth. With appropriate network retuning, reduced precision networks can achieve accuracy close or equal to that of full-precision floating-point models. Given the wide spectrum of precisions used in DL inference, FPGAs' ability to create custom bit-width datapaths gives them an advantage over other acceleration platforms in this domain. However, the embedded DSP blocks in the latest Intel and Xilinx FPGAs do not natively support precisions below 18-bit and thus can not efficiently pack low-precision multiplications, leaving the DSP blocks under-utilized. In this work, we present an enhanced DSP block that can efficiently pack 2x as many 9-bit and 4x as many 4-bit multiplications compared to the baseline Arria-10-like DSP block at the cost of 12% block area overhead which leads to only 0.6% total FPGA core area increase. We quantify the performance gains of using this enhanced DSP block in two state-of-the-art convolutional neural network accelerators on three different models: AlexNet, VGG-16, and ResNet-50. On average, the new DSP block enhanced the computational performance of the 8-bit and 4-bit accelerators by 1.32x and 1.6 x and at the same time reduced the utilized chip area by 15% and 30% respectively.

关键词： field programmable gate arrays Compressors Memory management Degradation Computational modeling

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