A prototype system that executes a set of periodic real-time tasks utilising dynamic hardware reconfiguration is presented. the proposed scheduling technique, merge server distribute load (MSDL), is not only able to g...
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A prototype system that executes a set of periodic real-time tasks utilising dynamic hardware reconfiguration is presented. the proposed scheduling technique, merge server distribute load (MSDL), is not only able to give an offline guarantee for the feasibility of the task set, but also minimises the number of device configurations. After describing this technique, the schedulability analysis is extended to cover different runtime system overheads, including the device reconfiguration time. then, a light-weight runtime system that performs the online part of the MSDL scheduling technique is detailed. the runtime system is implemented entirely in hardware. Finally, the corresponding synthesis tool flow is outlined and the overhead posed by the runtime system is reported.
this tutorial explores the use of the System on a programmable Chip as an ideal platform for rapid development of embedded solutions. Many sophisticated tools exist that facilitate rapid development of embedded system...
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ISBN:
(纸本)9781424403127
this tutorial explores the use of the System on a programmable Chip as an ideal platform for rapid development of embedded solutions. Many sophisticated tools exist that facilitate rapid development of embedded systems on a chip. As an example, we discuss a suite of three tightly-coupled embedded systems development tools from Altera, including: (1) hardware system generation and integration, (2) embedded software development, and (3) automatic hardware acceleration of ANSIASO-spec C functions.
In this paper we examine the feasibility of a new approach to FPGA design bitstream compression which aims to optimise placement and routing in order to minimise the distribution of configuration data in the device. W...
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ISBN:
(纸本)9781424403127
In this paper we examine the feasibility of a new approach to FPGA design bitstream compression which aims to optimise placement and routing in order to minimise the distribution of configuration data in the device. We present results from a variety of experiments which demonstrate how achievable compression ratio varies withthe design size and applied constraints. the approach proves promissing for certain designs where compression ratios up to 5 were achieved without compromising design timing.
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealththat must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper we describe a technique that automates...
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ISBN:
(纸本)9781424403127
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealththat must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper we describe a technique that automates the generation of IP core interfaces allowing these to be used as C functions transparently from within C source codes using a reconfigurable computing compiler. We also show how this same tool can be used to support run-time reconfiguration on FPGAs by generating a common wrapper that interfaces to multiple cores.
Dynamically reconfigurable FPGA-based systems offer a new kind of flexibility such as on-demand computing, self-adaption and self-optimization capabilities by restructuring the hardware at run-time. Using partial dyna...
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ISBN:
(纸本)9781424403127
Dynamically reconfigurable FPGA-based systems offer a new kind of flexibility such as on-demand computing, self-adaption and self-optimization capabilities by restructuring the hardware at run-time. Using partial dynamic reconfiguration allows the main system to run uninterrupted during the reconfiguration process in addition to the reduced time for the reconfiguration process. However, existing FPCFA-based platforms are hampered by physical restrictions limiting the practicability of partial reconfiguration. this led us to the concept of the Erlangen Slot Machine architecture in order to eliminate the physical and technical constraints.
We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared withthe linear congestion meth...
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ISBN:
(纸本)9781424403127
We introduce a new congestion driven placement algorithm for FPGAs in which the overlapping effect of bounding boxes is taken into consideration. Experimental results show that compared withthe linear congestion method [1] used in the state-of-the-art FPGA place and route package VPR [2], our algorithm achieves channel width reduction on 70% of the 20 largest MCNC benchmark circuits (10.1% on average) while keeping the channel width of the remaining 30% benchmarks unchanged. A distinct feature of our algorithm is that the critical path delay is not elongated on average, and in most cases reduced.
In this research, we introduce FPGA based fuzzy logic controller (FLC). the benefit of using FPGA based FLC compare to software FLC is that the computation time reduction. Using this FLC, we design automated car back ...
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ISBN:
(纸本)9781424403127
In this research, we introduce FPGA based fuzzy logic controller (FLC). the benefit of using FPGA based FLC compare to software FLC is that the computation time reduction. Using this FLC, we design automated car back parallel parking system also with complete FPGA based controller. We build a small-scaled robot car and test on a real environment with VHDL code for wall following and parking. this paper describes the background of fuzzy logic system, the design of fuzzy logic system with FPGA and the experimental results.
An FPGA based trigger system for an imaging particle detector has been designed and produced. the main capabilities of the system are the recognition of the track pattern of the incoming particles, the calculation of ...
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ISBN:
(纸本)9781424403127
An FPGA based trigger system for an imaging particle detector has been designed and produced. the main capabilities of the system are the recognition of the track pattern of the incoming particles, the calculation of its stopping pixel and the time discrimination of events. the description of the implemented algorithms, the FPGA architecture, the developed hardware and the main operation results are included in this paper. the trigger system has already been installed in the FAST detector and operated during the 2005 data taking period with very satisfactory performance. therefore, this trigger system will be used in the detector for further operation in the incoming years.
We propose a novel, high speed, low memory fully programable FPGA decoder architecture to decode quasi-cyclic LDPC codes. By performing optimizations at the code construction, algorithmic and architecture levels we ar...
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ISBN:
(纸本)9781424403127
We propose a novel, high speed, low memory fully programable FPGA decoder architecture to decode quasi-cyclic LDPC codes. By performing optimizations at the code construction, algorithmic and architecture levels we are able to achieve significant throughput and memory storage advantages over current FPGA decoder implementations. Our decoder employs the modified turbo decoding algorithm, to achieve a decoding throughput of 223Mbps for a framed length of 3200 bits whilst only consuming 71Kb of memory,using a Xilinx Virtex-4 architecture.
this tutorial describes the Why and How of the new 65-nm families of Virtex-5 FPGAs. It describes several aspects of the technology that affect speed, density, and power consumption. the basic device structure and pac...
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