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16th international conference on field programmable logic and applications

作者： Martinez, Antonio Reynery, Leonardo Pelayo, Francisco Morillas, Christian Romero, Samuel Univ Alicante Dept Comp Technol Alicante Spain Polytecn Torino Dept Elect Turin Italy Univ Granada Dept Comp Engn E-18071 Granada Spain Univ Jaen Dept Comp Sci Jaen Spain

ISBN: (纸本)9781424403127

this paper presents a synthesis tool for the automatic translation and optimization of bioinspired vision models into a FPL implementation. the software allows functional simulation and high level specification of the model, and produces a data-flow model using VHDL, which is synthesizable with different lower-level synthesis tools and for various FPGA technologies. the proposed design platform extends the features of the codesign environment CodeSimulink for implementing visual processing systems, starting from purely functional specifications. An optimization strategy based on the calculation of the Pareto front is also introduced to perform a multi-objective minimization of both, the circuit area and the root mean square of the computation error. Performance measure-ments for the FPL implementation of an example retina-like vision model on a FPGA-based PCI board are provided.

关键词： field programmable gate arrays (FPGA)

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FPGA based acceleration of the linpack benchmark: A high level code transformation approach

FPGA based acceleration of the linpack benchmark: A high lev...

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16th international conference on field programmable logic and applications

作者： Turkington, Kieron Masselos, Konstantinos Constantinides, George A. Leong, Philip Univ London Imperial Coll Dept Elect & Elect Engn London England Univ London Imperial Coll Dept Comp London England

ISBN: (纸本)9781424403127

Due to their increasing resource densities, field programmable gate arrays (FPGAs) have become capable of efficiently implementing large scale scientific applications involving floating point computations. In this paper FPGAs are compared to a high end microprocessor with respect to sustained performance for a popular floating point CPU performance benchmark, namely LINPACK 1000. A set of translation and optimization steps have been applied to transform a sequential C description of the LINPACK benchmark, based on a monolithic memory model, into a parallel Handel-C description that utilizes the plurality of memory resources available on a realistic reconfigurable computing platform. the experimental results show that the latest generation of FPGAs, programmed using Handel-C, can achieve a sustained floating point performance up to 6 times greater than the microprocessor while operating at a clock frequency that is 60 times lower. the transformations are applied in a way that could be generalized, allowing efficient compilation approaches for the mapping of high level descriptions onto FPGAs.

关键词： field programmable gate arrays (FPGA)

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Secure content distribution system based on run-time partial hardware reconfiguration

Secure content distribution system based on run-time partial...

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16th international conference on field programmable logic and applications

作者： Hori, Yohei Yokoyama, Hiroyuki Toda, Kenji AIST 1-1-1 Umezono Tsukuba Ibaraki Japan KDDI R&D Lab Inc Saitama 3568502 Japan

ISBN: (纸本)9781424403127

A secure content distribution system is prototyped based on run time partial reconfigurability of an FPGA. the system provides a robust content protection scheme for online con tent download services. the key idea is to divide the security module in a user terminal into ontent Specific ircuit (S) and Terminal uild in ircuit (T) and to dynamically reconfigure S. S is customi ed for each content and transferred from a server in the form of encrypted con figuration data. T is a uniquely identifiable processing unit that is combined with particular S to decrypt and de code contents. A content is properly decrypted and played by the security module only if its S is interlocked with the authori ed T To reali e this S T interlock authen tication mechanism, partial reconfigurability of the FPGA is essential. this paper discusses the robustness and feasibility of the content distribution system through a proof of concept demonstration.

关键词： field programmable gate arrays (FPGA)

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ON-FPGA COMMUNICATION ARCHITECTURES AND DESIGN FACTORS

<bold>ON-FPGA COMMUNICATION ARCHITECTURES AND DESIGN FACTORS...

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16th international conference on field programmable logic and applications

作者： Mak, Terrence S. T. Sedcole, Pete Cheung, Peter Y. K. Luk, Wayne Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England Imperial Coll London Dept Comp London England

ISBN: (纸本)9781424403127

the recent development of Platform-FPGA or field-programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing power as well as opportunities for rapid system prototyping. these platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication. However, as the number of embedded processors increases, communication bandwidth between embedded components becomes a limiting factor to overall system performance. In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies. Salient factors, which include quantitative performance metrics and qualitative factors, relevant to design are identified and used to analyze and classify the on-FPGA communication architectures. this survey aims to facilitate innovation in and development of future on-FPGA communication architectures.

关键词： field programmable gate arrays (FPGA)

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An FPGA-based system on chip for the measurement of QCM sensors resolution

An FPGA-based system on chip for the measurement of QCM sens...

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16th international conference on field programmable logic and applications

作者： Moure, Maria Jose Valdes, Maria Dolores Rodiz, Pablo Rodriguez-Pardo, Loreto Farina, Jose Univ Vigo Dept Tecnol Elect Inst Elect Aplicada Pedro Barrie de la Maza Campus Univ As Lagoas Marcosende Vigo Spain

ISBN: (纸本)9781424403127

this paper describes the design of an FPGA-based SoC system intended to measure the mass resolution of quartz crystal microbalance (QCM) sensors. the implemented system integrates the frequency measurement and the computation of the sensor resolution in a single FPGA to configure an standalone measurement system. A Virtex-4 FPGA from Xilinx was chosen as hardware platform due to its suitable architecture to support SoC and DSP applications. the developed measurement system combines the 32-bit embedded MicroBlaze((R)) soft processor with a specific hardware coprocessor designed to accelerate the computations required for real-time processing. A data flow based on techniques as recursive formulas and jump prediction was proposed in order to reduce the computations and memory requirements of the coprocessor. Finally, the implemented system was validated with a 9 MHz QCM sensor in damping media used for electrochemical applications and the results were compared with a full floating point implementation.

关键词： field programmable gate arrays (FPGA)

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FPGA implementation of an efficient correlator for complementary sets of sequences

FPGA implementation of an efficient correlator for complemen...

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16th international conference on field programmable logic and applications

作者： Perez, M. C. Urena, J. Hernandez, A. De Marziani, C. Ochoa, A. Marnane, W. P. Univ Alcala de Henares Dept Elect Campus Univ S-N Alcala De Henares Spain Univ Coll Cork Dept Elect & Elect Engn Cork Ireland

ISBN: (纸本)9781424403127

the use of complementary sets of sequences is especially relevant in multisensorial systems, with simultaneous emissions from different sources and low signal-to-noise ratio (SNR). there exist efficient generation and correlation algorithms that give a reduction in the computational load and complexity of a hardware implementation. In this work a new hardware design approach for an efficient correlator of complementary sets of sequences (CCS) is presented. It is based on utilising reconfigurable logic to gain the required flexibility in terms of correlator parameters. the configuration of the design is carried out at the pre-synthesis stage, so the user can change this configuration according to the requirements of the application.

关键词： field programmable gate arrays (FPGA)

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Application-specific memory interleaving for FPGA-based grid computations: A general design technique

Application-specific memory interleaving for FPGA-based grid...

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16th international conference on field programmable logic and applications

作者： VanCourt, Tom Herbordt, Martin Boston Univ Dept Elect & Comp Engn 8 St Marys St Boston MA 02215 USA

ISBN: (纸本)9781424403127

Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA implementations of such algorithms would improve if there were concurrent, non-interfering access to all points in each cluster. When clusters contain dozens of points and access patterns are irregular, multiported memories are infeasible and vector-oriented approaches are inapplicable. Instead, the grid points can be distributed across multiple interleaved memory banks so that, when accessing any cluster, each point comes from a different memory bank. We present a general technique based on the knowledge of the application's multidimensional indexing. this technique maps access clusters into a custom-interleaved memory using the FPGA's multiple on-chip RAMs and configurable data paths. Case studies examine rectangular and nonrectangular grids of different dimensionality, including performance vs. resource tradeoffs when cluster sizes are not powers of two. We also present a prototype tool for generating interleaved memories automatically from concise, application-specific definitions.

关键词： field programmable gate arrays (FPGA)

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Architectural modifications to improve floating-point unit efficiency in FPGAS

Architectural modifications to improve floating-point unit e...

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16th international conference on field programmable logic and applications

作者： Beauchamp, Michael J. Hauck, Scott Underwood, Keith D. Hemmert, K. Scott Univ Washington Box 352500 Seattle WA 98195 USA Scalable Comp Syst Sandia Natl Labs Albuquerque NM 87185 USA

ISBN: (纸本)9781424403127

FPGAs have reached densities that can implement floating-point applications, but floating-point operations still require a large amount of FPGA resources. One major component of IEEE compliant floating-point computations is variable length shifters. they account for over 30% of a double-precision floating-point adder and 25% of a double-precision multiplier. this paper introduces two alternatives for implementing these shifters. One alternative is a coarse-grained approach: embedding variable length shifters in the FPGA fabric. these units provide significant area savings with a modest clock rate improvement over existing architectures. Another alternative is a fine-grained approach: adding a 4:1 multiplexer inside the slices, in parallel to the LUTs. While providing a more modest area savings, these multiplexers provide a significant boost in clock rate with a small impact on the FPGA fabric.

关键词： field programmable gate arrays (FPGA)

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FPGA programmable logic block evaluation using quantified Boolean satisfiability

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 165-172页

作者： Ling, A. C. Singh, D. P. Brown, S. D. Univ Toronto Toronto ON M5S 3G4 Canada Altera Toronto Technol Ctr Toronto ON M5S 1S4 Canada

A novel field programmable gate array (FPGA) logic synthesis technique that determines if a logic function can be implemented in a given programmable circuit is presented, and how this problem can be formalised and solved using quantified Boolean satisfiability is described. this technique is general enough to be applied to any type of logic function and programmable circuit;thus, it has many applications to FPGAs. the application demonstrated is the FPGA programmable logic block evaluation and the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.

关键词： logic synthesis field programmable gate arrays Formal logic logic functions

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An FPGA implementation of high throughput stochastic simulator for large-scale biochemical systems

An FPGA implementation of high throughput stochastic simulat...

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16th international conference on field programmable logic and applications

作者： Yoshimi, Masato Osana, Yasunori Iwaoka, Yow Nishikawa, Yuri Kojima, Toshinori Funahashi, Akira Hiroi, Noriko Shibata, Yuichiro Iwanaga, Naoki Kitano, Hiroaki Amano, Hideharu Keio Univ Yokohama Kanagawa 223 Japan ERATO-SORST JST Kitano Symbiotic Syst Project Tokyo Japan Nagasaki Univ Nagasaki Japan

ISBN: (纸本)9781424403127

Stochastic simulation of biochemical systems has become one of major approaches to study life processes as system, yet is a computational challenge to run the simulation due to its vast calculation cost. this paper shows the implementation and evaluation of a stochastic simulation algorithm (SSA) called "First Reaction Method" on an FPGA-based biochemical simulator. It achieves high throughput by (1) consecutively throwing data into deeply-pipelined floating point arithmetic units, and (2) by distruibuting multiple simulators for parallel execution. As the result of evaluation on an FPGA-based simulation platform called ReCSiP2, the simulator outperforms execution on Xeon 2.80 GHz by approximately 80 times, even with large-scale biochemical systems.

关键词： field programmable gate arrays (FPGA)

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