the proceedings contain 70 papers. the topics discussed include: design of parallel implementations by means of abstract dynamic critical path based profiling of complex sequential algorithms;handheld system energy re...
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ISBN:
(纸本)3540390944
the proceedings contain 70 papers. the topics discussed include: design of parallel implementations by means of abstract dynamic critical path based profiling of complex sequential algorithms;handheld system energy reduction by OS-driven refresh;delay constrained register transfer level dynamic power estimation;heuristic for two-level cache hierarchy exploration considering energy consumption and performance;system level multi-bank main memory configuration for energy reduction;circuit sizing and supply-voltage selection for low-power digital circuit design;estimation of power reduction by on-chip transmission line for 45nm technology;methodology for dynamic power verification of contactless smartcards;and the design of a dataflow coprocessor for low power embedded hierarchical processing.
the proceedings contain 43 papers. the topics discussed include: convex optimization of resource allocation in asymmetric and heterogeneous SoC;power efficient digital IE design for a medical application with high rel...
ISBN:
(纸本)9781479954124
the proceedings contain 43 papers. the topics discussed include: convex optimization of resource allocation in asymmetric and heterogeneous SoC;power efficient digital IE design for a medical application with high reliability requirements;robust sub-powered asynchronous logic;a unique network EDA tool to create optimized ad hoc binary to residue number system converters;evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices;parametric yield optimization using leakage-yield-driven floorplanning;tuning software-based fault-tolerance techniques for poweroptimization;energy management of highly dynamic server workloads in an heterogeneous data center;method to evaluate energy saving techniques in data buses;equivalence of clock gating and synchronization with applicability to gals communication;and rate-distortion and energy performance of HEVC video encoders.
the proceedings contain 47 papers. the topics discussed include: performance estimation of program partitions on multi-core platforms;pipelining for dual supply voltages;thermally-aware composite run-time CPU power mo...
ISBN:
(纸本)9781509007332
the proceedings contain 47 papers. the topics discussed include: performance estimation of program partitions on multi-core platforms;pipelining for dual supply voltages;thermally-aware composite run-time CPU power models;investigation of electrical and thermal properties of carbon nanotube interconnects;multi-scale electrothermal simulation and modeling of resistive random access memory devices;thermoelectric effects in graphene and grapheme-based nanostructures using atomistic simulation;fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing;hold-time violation analysis and fixing in near-threshold region;and design challenges for near and sub-threshold operation: a case study with an ARM Cortex-M0+ based WSN subsystem.
the proceedings contain 26 papers. the topics discussed include: response time schedulability analysis for hard real-time systems accounting DVFS latency on heterogeneous cluster-based platform;calculation of worst-ca...
ISBN:
(纸本)9781467394192
the proceedings contain 26 papers. the topics discussed include: response time schedulability analysis for hard real-time systems accounting DVFS latency on heterogeneous cluster-based platform;calculation of worst-case execution time for multicore processors using deterministic execution;a n unconventional computing technique for ultra- fast and ultra-low power data mining;dedicated network for distributed configuration in a mixed-signal wireless sensor node circuit;energy management via PI control for data parallel applications withthroughput constraints;dynamic current reduction of CMOS digital circuits through design and process optimization;unified power format (UPF) methodology in a vendor independent flow;a synchronous sub-threshold ultra-low power processor;and constructing stability-based clock gating with hierarchical clustering.
the proceedings contain 83 papers. the topics discussed include: a power-efficient and scalable load-store queue design;power consumption reduction using dynamic control of micro processor performance;temperature awar...
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ISBN:
(纸本)3540290133
the proceedings contain 83 papers. the topics discussed include: a power-efficient and scalable load-store queue design;power consumption reduction using dynamic control of micro processor performance;temperature aware datapath scheduling;memory hierarchy energy cost of a direct filtering implementation of the wavelet transformation;optimization of reliability and power consumption in systems on a chip;power supply selective mapping for accurate timing analysis;a CAD platform for sensor interfaces in low-power applications;an integrated environment for embedded hard real-time systems scheduling withtiming and energy constraints;and static noise margin analysis of sub-threshold SRAM cells in deep sub-micron technology.
the proceedings contain 36 papers. the topics discussed include: robust low power embedded SRAM design: from system to memory cell;variability in advanced nanometer technologies: challenges and solutions;subthreshold ...
ISBN:
(纸本)3642118011
the proceedings contain 36 papers. the topics discussed include: robust low power embedded SRAM design: from system to memory cell;variability in advanced nanometer technologies: challenges and solutions;subthreshold circuit design for ultra-low-power applications;SystemC AMS extensions: new language - new methods - new applications;process variation aware performance analysis of asynchronous circuits considering spatial correlation;interpreting SSTA results with correlation;residue arithmetic for variation-tolerant design of multiply-add units;exponent Monte Carlo for quick statistical circuit simulation;clock repeater characterization for jitter-aware clock tree synthesis;a hardware implementation of the user-centric display energy management;on-chip thermal modeling based on spice simulation;switching noise optimization in the wake-up phase of leakage-aware power gating structures;and data-driven clock gating for digital filters.
the proceedings contain 58 papers. the topics discussed include: system-level application-specific NoC design for network and multimedia applications;an automatic design flow for mapping application onto a 2D mesh NoC...
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ISBN:
(纸本)9783540744412
the proceedings contain 58 papers. the topics discussed include: system-level application-specific NoC design for network and multimedia applications;an automatic design flow for mapping application onto a 2D mesh NoC architecture;template vertical dictionary-based program compression scheme on the TTA;a heuristic for reducing dynamic power dissipation in clocked sequential designs;computation of joint timing yield of sequential networks considering process variations;Modelling the impact of high level leakage optimization techniques on the delay of RT-components;design-in reliability for 90-65nm CMOS nodes submitted to hot-carriers and NBTI degradation;clock distribution techniques for low-EMI design;weakness identification for effective repair of power distribution network;automated instruction set characterization and power profile driven software optimization for mobile devices;low power elliptic curve cryptography;and exploiting input variations for energy reduction.
the proceedings contain 32 papers. the special focus in this conference is on power and timingmodeling. the topics include: Self-timed SRAM for energy harvesting systems;l1 data cache power reduction using a forwardi...
ISBN:
(纸本)9783642177514
the proceedings contain 32 papers. the special focus in this conference is on power and timingmodeling. the topics include: Self-timed SRAM for energy harvesting systems;l1 data cache power reduction using a forwarding predictor;statistical leakage poweroptimization of asynchronous circuits considering process variations;Optimizing and comparing CMOS implementations of the C-element in 65nm technology: Self-timed ring case;hermes-A – an asynchronous NoC router with distributed routing;practical and theoretical considerations on low-power probability-codes for networks-on-chip;Logic architecture and VDD selection for reducing the impact of intra-die random VTvariations on timing;impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis;Transistor-level gate modeling for nano CMOS circuit verification considering statistical process variations;an automated framework for power-critical code region detection and power peak optimization of embedded software;white-box current source modeling including parameter variation and its application in timingsimulation;controlled-precision pure-digital square-wave frequency synthesizer;an all-digital phase-locked loop with high resolution for local on-chip clock synthesis;clock network synthesis with concurrent gate insertion;modeling time domain magnetic emissions of ICs;power profiling of embedded analog/mixed-signal systems;open-people: Open power and energy optimization platform and estimator;Early power estimation in heterogeneous designs using SoCLib and SystemC-AMS;ASTEC: Asynchronous technology for low power and secured embedded systems;OPENTLM and SOCKET: Creating an open ecosystem for virtual prototyping of complex SOCs;system level power estimation of system-on-chip interconnects in consideration of transition activity and crosstalk;Variability-conscious circuit designs for low-voltage memory-rich nano-scale CMOS LSIs.
the proceedings contain 92 papers. the special focus in this conference is on Buses and Communication. the topics include: Connecting e-dreams to deep-submicron realities;design methodology for rapid development of So...
ISBN:
(纸本)3540230955
the proceedings contain 92 papers. the special focus in this conference is on Buses and Communication. the topics include: Connecting e-dreams to deep-submicron realities;design methodology for rapid development of SoC ICs based on an innovative system architecture with emphasis to timing closure and power consumption optimization;nick kanopoulos;adaptive subthreshold leakage reduction through N/P wells reverse biasing;leakage in CMOS circuits;randomness in nanometer design;crosstalk cancellation for realistic PCB buses;a low-power encoding scheme for gigabyte video interfaces;dynamic wire delay and slew metrics for integrated bus structures;perfect 3-limited-weight code for low power I/O;a high-level DSM bus model for accurate exploration of transmission behaviour and power estimation of global system buses;performance metric based optimization protocol;temperature dependence in low power CMOS UDSM process;yield optimization by means of process parameters estimation;high yield standard cell libraries;a study of crosstalk through bonding and package parasitics in CMOS mixed analog-digital circuits;sleepy stack reduction of leakage power;a cycle-accurate energy estimator for CMOS digital circuits;leakage reduction at the architectural level and its application to 16 bit multiplier architectures;reducing cross-talk induced power consumption and delay;investigation of low-power low-voltage circuit techniques for a hybrid full-adder cell;leakage power analysis and comparison of deep submicron logic gates;threshold mean larger ratio motion estimation in MPEG encoding using LNS and energy- and area-efficient deinterleaving architecture for high-throughput wireless applications.
the proceedings contain 45 papers. the topics discussed include: subthreshold FIR filter architecture for ultra low pow applications;improving the power-delay performance in subthreshold source-coupled logic circuits;...
the proceedings contain 45 papers. the topics discussed include: subthreshold FIR filter architecture for ultra low pow applications;improving the power-delay performance in subthreshold source-coupled logic circuits;design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction;temporal discharge current driven clustering for improved leakage power reduction in row-based power-gating;Intelligate: scalable dynamic invariant learning for power reduction;analysis of effects of input arrival time variations on on-chip bus power consumption;untraditional approach to computer energy reduction;poweroptimization of parallel multipliers in systems with variable word-length;a study on CMOS time uncertainty with technology scaling;a comparison between two logic synthesis forms from digital switching noise viewpoint;and ultra low voltage high speed differential CMOS inverter.
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