the proceedings contain 24 papers. the topics discussed include: an automated framework for power-critical code region detection and power peak optimization of embedded software;system level power estimation of system...
ISBN:
(纸本)3642177514
the proceedings contain 24 papers. the topics discussed include: an automated framework for power-critical code region detection and power peak optimization of embedded software;system level power estimation of system-on-chip interconnects in consideration of transition activity and crosstalk;residue arithmetic for designing low-power multiply-add units;an on-chip flip-flop characterization circuit;a temperature-aware time-dependent dielectric breakdown analysis framework;on line poweroptimization of data flow multi-core architecture based on VDD-hopping for local DVFS;statistical leakage poweroptimization of asynchronous circuits considering process variations;optimizing and comparing CMOS implementations of the C-element in 65nm technology: self-timed ring case;practical and theoretical considerations on low-power probability-codes for networks-on-chip;and impact of process variations on pulsed flip-flops: yield improving circuit-level techniques and comparative analysis.
the proceedings contain 34 papers. the special focus in this conference is on RTL powermodeling, power Estimation, System-Level Design, Transistor-Level modeling and Asynchronous Circuit Design. the topics include: A...
ISBN:
(纸本)9783540410683
the proceedings contain 34 papers. the special focus in this conference is on RTL powermodeling, power Estimation, System-Level Design, Transistor-Level modeling and Asynchronous Circuit Design. the topics include: Architectural design space exploration achieved through innovative RTL power estimation techniques;power models for semi-autonomous RTL macros;RTL estimation of steering logic power;reducing power consumption through dynamic frequency scaling for a class of digital receivers;framework for high-level power estimation of signal processing architectures;adaptive bus encoding techique for switching activity reduced data transfer over wide system buses;accurate power estimation of logic structures based on timed Boolean functions;a holistic approach to system level energy optimization;design-space exploration of low power coarse grained reconfigurable datapath array architectures;internal power dissipation modeling and minimization for submicronic CMOS design;degradation delay model extension to CMOS gates;second generation delay model for submicron CMOS process;semi-modular latch chains for asynchronous circuit design;comparative study on self-checking carry-propagate adders in terms of area, power and performance;VLSI Implementation of a low-power high-speed self-timed adder;low power design techniques for contactless chipcards;dynamic memory design for low data-retention power;data-reuse and parallel embedded architectures for low-power, real-time multimedia applications and modeling of power consumption of adiabatic gates versus fan in and comparison with conventional gates.
the proceedings contain 68 papers. the special focus in this conference is on Gate-Level modeling, Low Level modeling, Characterization, Interconnect modeling and Asynchronous Techniques. the topics include: Architect...
ISBN:
(纸本)3540200746
the proceedings contain 68 papers. the special focus in this conference is on Gate-Level modeling, Low Level modeling, Characterization, Interconnect modeling and Asynchronous Techniques. the topics include: Architectural challenges for the next decade integrated platforms;a genetic bus encoding technique for poweroptimization of embedded systems;reduced leverage of dual supply voltages in ultra deep submicron technologies;a compact charge-based crosstalk induced delay model for submicronic CMOS gates;CMOS gate sizing under delay constraint;process characterization for low Vth and low power design;power and energy consumption of CMOS circuits: measurement methods and experimental results;effects of temperature in deep-submicron global interconnect optimization;interconnect parasitic extraction tool for radio-frequency integrated circuits;a block-based approach for SoC global interconnect electrical parameters characterization;interconnect driven low power high-level synthesis;bridging clock domains by synchronizing the mice in the mousetrap;power-consumption reduction in asynchronous circuits using delay path unequalization;statistic implementation of QDI asynchronous primitives;the emergency of design for energy efficiency;the most complete mixed-signal simulation solution with advance MS;power management in synopsys galaxy design platform;open multimedia platform for next-generation mobile devices;a statistic power model for non-synthetic RTL operators;stand-by power reduction for storage circuits and a flexible framework for fast multi-objective design space exploration of embedded systems.
the proceedings contain 49 papers. the special focus in this conference is on Arithmetics, Low-Level modeling, Characterization, Asynchronous and Adiabatic Techniques. the topics include: An improved power macro-model...
ISBN:
(纸本)9783540441434
the proceedings contain 49 papers. the special focus in this conference is on Arithmetics, Low-Level modeling, Characterization, Asynchronous and Adiabatic Techniques. the topics include: An improved power macro-model for arithmetic Datapath components;performance comparison of VLSI adders using logical effort;a high-performance low power DSP architecture;impact of technology in power-grid-induced noise;exploiting metal layer characteristics for low-power routing;instrumentation set-up for instruction level powermodeling;resonant multistage charging of dominant capacitances;a new methodology to design low-power asynchronous circuits;designing carry look-ahead adders with an adiabatic logic standard-cell library;clocking and clocked storage elements in multi-GHZ environment;dual supply voltage scaling in a conventional power-driven logic synthesis environment;robust sat-based search algorithm for leakage power reduction;a new methodology for efficient synchronization of RNS-based VLSI systems;clock distribution network optimization under self-heating and timing constraints;a compact charge-based propagation delay model for submicronic CMOS buffers;output waveform evaluation of basic pass transistor structure;an approach to energy consumption modeling in RC ladder circuits;structure independent representation of output transition time for CMOS library;a low energy clustered instruction memory hierarchy for long instruction word processors;design and realization of a low power register file using energy model;register file energy reduction by operand data reuse;trends in ultralow-voltage ram technology and offline data profiling techniques to enhance memory compression in embedded systems.
this paper describes a novel gate-level dual-threshold static poweroptimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications u...
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this paper describes a novel gate-level dual-threshold static poweroptimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. the cell libraries come in fixed threshold-high V-th for good standby power and low V-th for high speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library. (C) 2007 Elsevier B.V. All rights reserved.
this paper describes a novel gate-level dual-threshold static poweroptimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 9...
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ISBN:
(纸本)3540390944
this paper describes a novel gate-level dual-threshold static poweroptimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 90nm MTCMOS technology. the cell libraries come in fixed threshold - high V-th for good standby power and low V-th for high-speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.
the aim of this study is to provide a multi level VHDL-AMS modeling of an analog Phase Locked Loop (PLL). three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. the char...
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ISBN:
(纸本)3540390944
the aim of this study is to provide a multi level VHDL-AMS modeling of an analog Phase Locked Loop (PLL). three model levels are described, analyzed and compared in terms of simulation CPU times and accuracy. the characteristic parameters of the PLL, such as the settling time, overshoot, voltage variations linked to charge pump architecture and final voltage are extracted from the intermediate level.
Considering the complexity of the future 4G telecommunication systems, power consumption management becomes a major challenge for the designers, particularly for base-band modem functionalities. System level low-power...
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ISBN:
(纸本)3540390944
Considering the complexity of the future 4G telecommunication systems, power consumption management becomes a major challenge for the designers, particularly for base-band modem functionalities. System level low-power policies which optimize dynamically the consumption, achieve major power savings compared to low level optimisations (e.g gated clock or transistor optimisation). We present an innovative powermodeling methodology of a 4G modem which allows to accurately qualify such low power solutions. then, we show the energy savings attended by these power management methods considering silicium technology.
In this paper, an ABCD modeling approach is proposed to model the inductive and capacitive coupling effect between the interconnect lines in DSM circuits. then, a physical aspect model is introduced to analyze the wor...
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ISBN:
(纸本)3540390944
In this paper, an ABCD modeling approach is proposed to model the inductive and capacitive coupling effect between the interconnect lines in DSM circuits. then, a physical aspect model is introduced to analyze the worst case crosstalk noise effect on the delay and rise time of the driver. It is observed that the inductive coupling effect can have a great effect on the timing characteristic of the interconnect line. Experimental results show that the method proposed in this paper differs from the HSPICE simulation with an average error less than 2.5% for boththe 50% delay and the rise time.
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