检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

4,353 篇 会议
68 篇 期刊文献
14 册 图书

馆藏范围

4,435 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

2,489 篇 工学
- 2,305 篇 计算机科学与技术...
- 1,055 篇 软件工程
- 492 篇 电气工程
- 430 篇 信息与通信工程
- 194 篇 电子科学与技术（可...
- 121 篇 控制科学与工程
- 102 篇 网络空间安全
- 89 篇 动力工程及工程热...
- 73 篇 生物工程
- 48 篇 机械工程
- 47 篇 生物医学工程（可授...
- 41 篇 光学工程
- 34 篇 建筑学
- 30 篇 材料科学与工程（可...
- 22 篇 仪器科学与技术
- 22 篇 土木工程
- 22 篇 化学工程与技术
604 篇 理学
- 427 篇 数学
- 97 篇 物理学
- 83 篇 生物学
- 67 篇 系统科学
- 61 篇 统计学（可授理学、...
- 23 篇 化学
339 篇 管理学
- 253 篇 管理科学与工程(可...
- 139 篇 工商管理
- 100 篇 图书情报与档案管...
61 篇 医学
- 45 篇 临床医学
- 38 篇 基础医学(可授医学...
40 篇 经济学
- 40 篇 应用经济学
38 篇 法学
- 33 篇 社会学
11 篇 教育学
11 篇 农学
6 篇 文学
1 篇 艺术学

主题

1,186 篇 computer archite...
446 篇 hardware
376 篇 high performance...
287 篇 concurrent compu...
279 篇 computational mo...
237 篇 application soft...
231 篇 parallel process...
217 篇 computer science
213 篇 distributed comp...
187 篇 costs
186 篇 bandwidth
179 篇 field programmab...
173 篇 delay
166 篇 throughput
159 篇 cloud computing
156 篇 grid computing
140 篇 computer network...
138 篇 resource managem...
133 篇 laboratories
123 篇 scalability

机构

16 篇 university of ch...
12 篇 school of comput...
12 篇 institute of com...
8 篇 department of co...
8 篇 georgia inst tec...
8 篇 univ chicago dep...
8 篇 barcelona superc...
8 篇 school of comput...
8 篇 carnegie mellon ...
8 篇 mathematics and ...
8 篇 intel corporatio...
7 篇 department of el...
7 篇 college of compu...
7 篇 univ illinois ur...
7 篇 computer systems...
7 篇 department of co...
7 篇 mathematics and ...
7 篇 intel corp santa...
7 篇 univ fed rio gra...
6 篇 univ toronto on

作者

13 篇 navaux philippe ...
11 篇 d.k. panda
9 篇 viktor k. prasan...
9 篇 prasanna viktor ...
9 篇 mutlu onur
9 篇 i. foster
8 篇 dhabaleswar k. p...
8 篇 dongarra jack
8 篇 guedes dorgival
7 篇 borin edson
7 篇 cristal adrian
7 篇 chong frederic t...
7 篇 loh gabriel h.
7 篇 kim nam sung
7 篇 zhou huiyang
7 篇 panda dhabaleswa...
7 篇 magoules frederi...
7 篇 ferreira renato
7 篇 xiaowei li
7 篇 buyya rajkumar

语言

4,403 篇 英文
23 篇 其他
10 篇 中文
2 篇 葡萄牙文
1 篇 法文

检索条件"任意字段=16th Symposium on Computer Architecture and High Performance Computing"

共 4435 条记录，以下是91-100 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing 29

VAQUERO: A Scratchpad-based Vector Accelerator for Query Pro...

引用

29th IEEE International symposium on high-performance computer architecture (HPCA)

作者： Pavon, Julian Vargas Valdivieso, Ivan Marimon, Joan Figueras, Roger Moll, Francesc Unsal, Osman Valero, Mateo Cristal, Adrian Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9781665476522

Database Management Systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centers. there have been many efforts to accelerate DBMS application performance. One of the most explored techniques is the use of vector processing. Unfortunately, conventional vector architectures have not been able to exploit the full potential of DBMS acceleration. In this paper, we present VAQUERO, our Scratchpad-based Vector Accelerator for QUEry pROcessing. VAQUERO improves the efficiency of vector architectures for DBMS operations such as data aggregation and hash joins featuring lookup tables. Lookup tables are significant contributors to the performance bottlenecks in DBMS processing suffering from insufficient ISA support in the form of scatter-gather instructions. VAQUERO introduces a novel Advanced Scratchpad Memory specifically designed with two mapping modes - direct- and associative-mode. these mapping modes enable VAQUERO to accelerate real-world databases with workload sizes that significantly exceed the scratchpad memory capacity. Additionally, the associative-mode allows to use VAQUERO with DBMS operators that use hashed keys, e.g. hash-join and hash-aggregate. VAQUERO has been designed considering general DBMS algorithm requirements instead of being based on a particular database organization. For this reason, VAQUERO is capable to accelerate DBMS operators for both row- and column-oriented databases. In this paper, we evaluate the efficiency of VAQUERO using two highly optimized popular open-source DBMS, namely the row-based PostgreSQL and column-based MonetDB. We implemented VAQUERO at the RTL level and prototype it, by performing Place&Route, at the 7nm technology node. VAQUERO incurs a modest 0.15% area overhead compared with an Intel Ice Lake processor. Our evaluation shows that VAQUERO significantly outperforms PostgreSQL and MonetDB by 2.09x and 3.32x respectively, when processing operators and queries

关键词： Vector computing Scratchpad Memory Database Accelerator PostgreSQL MonetDB

来源：评论

学校读者我要写书评

暂无评论

Message from Program Chairs

Proceedings - Symposium on Computer Architecture and High Pe...

引用

Proceedings - symposium on computer architecture and high performance computing 2024年 X页

作者： Osthoff, Carla Nelson Amaral, J. National Laboratory for Scientific Computing Brazil University of Alberta Canada

来源：评论

学校读者我要写书评

暂无评论

iNUMAlloc: Towards Intelligent Memory Allocation for AI Accelerators with NUMA 21

iNUMAlloc: Towards Intelligent Memory Allocation for AI Acce...

引用

21st IEEE International symposium on Parallel and Distributed Processing with Applications, 13th IEEE International Conference on Big Data and Cloud computing, 16th IEEE International Conference on Social computing and Networking and 13th International Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Xu, Yuanchao Qian, Ruyi Wang, Yida Huo, Qirun Capital Normal University College of Information Engineering Beijing China Skl of Computer Architecture Institute of Computing Technology Cas Beijing China

ISBN: (纸本)9798350329223

the amazing success of deep neural network benefits from the rise of big data. As deep learning models are becoming more scale than ever before, their requirements for memory bandwidth are growing at a tremendous pace. Some AI accelerators adopt non-uniform memory access (NUMA) architecture to mitigate this issue and hence complicate device memory allocation. Although extensive studies have been conducted on how to mitigate resource contention and reduce latency, almost all of them target on CPU-oriented NUMA systems but not on AI accelerators where memory allocation precedes task scheduling. the current memory allocator generally adopts an interleaved memory allocation strategy, which is very easy to implement but far from *** tackle this issue, this paper proposes iNUMAlloc, an intelligent memory allocator specialized for AI accelerators with NUMA architecture by combining program behavior and predictable hardware resources altogether. Preliminary evaluation shows that it can help to improve the accuracy and efficiency of memory allocation, thereby achieving stable execution time. © 2023 IEEE.

关键词： Deep neural networks

来源：评论

学校读者我要写书评

暂无评论

MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency 23

MXFaaS: Resource Sharing in Serverless Environments for Para...

引用

50th Annual International symposium on computer architecture (ISCA)

作者： Stojkovic, Jovan Xu, Tianyin Franke, Hubertus Torrellas, Josep Univ Illinois Champaign IL 61820 USA IBM Res Yorktown Hts NY USA

ISBN: (纸本)9798400700958

Although serverless computing is a popular paradigm, current serverless environments have high overheads. Recently, it has been shown that serverless workloads frequently exhibit bursts of invocations of the same function. Such pattern is not handled well in current platforms. Supporting it efficiently can speed-up serverless execution substantially. In this paper, we target this dominant pattern with a new serverless platform design named MXFaaS. MXFaaS improves function performance by efficiently multiplexing (i.e., sharing) processor cycles, I/O bandwidth, and memory/processor state between concurrently executing invocations of the same function. MXFaaS introduces a new container abstraction called MXContainer. To enable efficient use of processor cycles, an MXContainer carefully helps schedule same-function invocations for minimal response time. To enable efficient use of I/O bandwidth, an MXContainer coalesces remote storage accesses and remote function calls from same-function invocations. Finally, to enable efficient use of memory/processor state, an MXContainer first initializes the state of its container and only later, on demand, spawns a process per function invocation, so that all invocations can share unmodified memory state and hence minimize memory footprint. We implement MXFaaS in two serverless platforms and run diverse serverless benchmarks. With MXFaaS, serverless environments are much more efficient. Compared to a state-of-the-art serverless environment, MXFaaS on average speeds-up execution by 5.2x, reduces P99 tail latency by 7.4x, and improves throughput by 4.8x. In addition, it reduces the average memory usage by 3.4x.

关键词： Serverless computing cloud computing resource management

来源：评论

学校读者我要写书评

暂无评论

MapZero: Mapping for Coarse-grained Reconfigurable architectures with Reinforcement Learning and Monte-Carlo Tree Search 23

MapZero: Mapping for Coarse-grained Reconfigurable Architect...

引用

50th Annual International symposium on computer architecture (ISCA)

作者： Kong, Xiangyu Huang, Yi Zhu, Jianfeng Man, Xingchen Liu, Yang Feng, Chunyang Gou, Pengfei Tang, Minggui Wei, Shaojun Liu, Leibo Tsinghua Univ BNRist Sch Integrated Circuits Beijing Peoples R China GBA Innovat Inst High Performance Server Guangzhou Guangdong Peoples R China HEXIN Technol Co Ltd Guangzhou Guangdong Peoples R China

ISBN: (纸本)9798400700958

Coarse-grained reconfigurable architecture (CGRA) has become a promising candidate for data-intensive computing due to its flexibility and high energy efficiency. CGRA compilers map data flow graphs (DFGs) extracted from applications onto CGRAs, playing a fundamental role in fully exploiting hardware resources for acceleration. Yet the existing compilers are time-demanding and cannot guarantee optimal results due to the traversal search of enormous search spaces brought about by the spatio-temporal flexibility of CGRA structures and the complexity of DFGs. Inspired by the amazing progress in reinforcement learning (RL) and Monte-Carlo tree search (MCTS) for real-world problems, we consider constructing a compiler that can learn from past experiences and comprehensively understand the target DFG and CGRA. In this paper, we propose an architecture-aware compiler for CGRAs based on RL and MCTS, called MapZero - a framework to automatically extract the characteristics of DFG and CGRA hardware and map operations onto varied CGRA fabrics. We apply Graph Attention Network to generate an adaptive embedding for DFGs and also model the functionality and interconnection status of the CGRA, aiming at training an RL agent to perform placement and routing intelligently. Experimental results show that MapZero can generate superior-quality mappings and reduce compilation time hundreds of times compared to state-of-the-art methods. MapZero can find high-quality mappings very quickly when the feasible solution space is rather small and all other compilers fail. We also demonstrate the scalability and broad applicability of our framework.

关键词： Coarse-Grained Reconfigurable architecture Compiler Graph Neural Network Reinforcement Learning

来源：评论

学校读者我要写书评

暂无评论

Exploring the Effects of Silent Data Corruption in Distributed Deep Learning Training 34

Exploring the Effects of Silent Data Corruption in Distribut...

引用

34th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Rojas, Elvis Perez, Diego Meneses, Esteban Costa Rica Inst Technol Cartago Costa Rica Natl Univ Costa Rica Heredia Costa Rica Costa Rica Natl High Technol Ctr San Jose Costa Rica

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

the profound impact of recent developments in artificial intelligence is unquestionable. the applications of deep learning models are everywhere, from advanced natural language processing to highly accurate prediction of extreme weather. those models have been continuously increasing in complexity, becoming much more powerful than their original versions. In addition, data to train the models is becoming more available as technological infrastructures sense and collect more readings. Consequently, distributed deep learning training is often times necessary to handle intricate models and massive datasets. Running a distributed training strategy on a supercomputer exposes the models to all the considerations of a large-scale machine;reliability is one of them. As supercomputers integrate a colossal number of components, each fabricated on an ever decreasing feature-size, faults are common during execution of programs. A particular type of fault, silent data corruption, is troublesome because the system does not crash and does not immediately give an evident sign of an error. We set out to explore the effects of that type of faults by inspecting how distributed deep learning training strategies cope with bit-flips that affect their internal data structures. We used checkpoint alteration, a technique that permits the study of this phenomenon on different distributed training platforms and with different deep learning frameworks. We evaluated two distributed learning libraries (Distributed Data Parallel and Horovod) and found out Horovod is slightly more resilient to SDCs. However, fault propagation is similar in both cases, and the model is more sensitive to SDCs than the optimizer.

关键词： Deep learning resilience checkpoint neural networks HDF5 fault injection high performance computing

来源：评论

学校读者我要写书评

暂无评论

A Research Retrospective on the AMD Exascale computing Journey 50

A Research Retrospective on the AMD Exascale Computing Journ...

引用

50th Annual International symposium on computer architecture (ISCA)

作者： Loh, Gabriel H. Aga, Shaizeen Alsop, Johnathan Blagodurov, Sergey Chalmers, Noel Cownie, David Dutu, Alexandru Greathouse, Joseph L. Hossamani, Sachin Kalamatianos, John Lowell, Daniel Manne, Srilatha Mishkin, Michael Potter, Brandon Rao, Karthik Slice, John Vishnu, Abhinav Wyse, Mark Schulte, Michael J. Aguren, Derrick Bauman, Paul T. Boraten, Travis Chen, Shaoming Curtis, Nicholas Eckert, Yasuko Gurumurthi, Sudhanva Huang, Wei Kayiran, Onur Madan, Niti Mashimo, Susumu Nutter, Mark Punniyamurthy, Kishore Rodgers, Gregory Sridharan, Vilas Wasmundt, Samuel Yalavarti, Adithya Ignatowski, Mike Agrawal, Varun Beckmann, Bradford M. Boyer, Michael Cheng, Kevin Del Pino, Joris Erb, Christopher Gutierrez, Anthony Islam, Mahzabeen Kotra, Jagadish Majumdar, Abhinandan McDougall, Damon Paul, Indrani Puthoor, Sooraj Scrbak, Marko van Oostrum, Rene Wilkening, Mark Yudanov, Dmitri Adhinarayanan, Vignesh Aji, Ashwin M. Beigi, Majed Valad Brantley, William C. Chu, Michael L. Duong, Nam Freitag, Chip Hamidouche, Khaled Jayasena, Nuwan Lee, Alan Malaya, Nicholas Mednick, Elliot Poremba, Matthew Raasch, Steven E. Seyedzadeh, Mohammad van Tassell, Eric Wolfe, Noah Adv Micro Devices Inc Santa Clara CA 95054 USA

ISBN: (纸本)9798400700958

the pace of advancement of the top-end supercomputers historically followed an exponential curve similar to (and driven in part by) Moore's Law. Shortly after hitting the petaflop mark, the community started looking ahead to the next milestone: Exascale. However, many obstacles were already looming on the horizon, such as the slowing of Moore's Law, and others like the end of Dennard Scaling had already arrived. Anticipating significant challenges for the overall high-performance computing (HPC) community to achieve the next 1000x improvement, the U.S. Department of Energy (DOE) launched the Exascale computing Program to enable and accelerate fundamental research across the many technologies needed to achieve exascale computing. AMD had the opportunity to contribute to the so-called "*Forward" programs from the DOE, which were a series of public-private partnerships focused on research and co-design activities covering compute architectures, interconnects, memory systems, chiplets and packaging, software stacks, applications, and more. Some of the research from these programs can now be found in the world's first exascale supercomputer, some were a little ahead of their time and may have an impact in the coming years, and others simply did not pan out. In this paper, we provide a retrospective of AMD's nearly decade-long research journey covering how we tried to predict the architecture of a supercomputer a decade into the future, what we got right, what we got wrong, and some of the insights and learnings that we discovered along the way.

关键词： Exascale HPC high-performance computing supercomputing Frontier memory chiplets heterogeneous compute accelerated processing unit research

来源：评论

学校读者我要写书评

暂无评论

Strategies for Fault-Tolerant Tightly-Coupled HPC Workloads Running on Low-Budget Spot Cloud Infrastructures 34

Strategies for Fault-Tolerant Tightly-Coupled HPC Workloads ...

引用

34th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Munhoz, Vanderlei Castro, Marcio Mendizabal, Odorico Fed Univ Santa Catarina UFSC Florianopolis SC Brazil

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

Cloud providers can rent their spare computing capacity at substantial discounts, reclaiming it whenever there is a more profitable higher-priority request - a business model well known as spot infrastructure market. Users can attain significant cloud investment savings using spot machines, however with the caveat of increasing software complexity, given the fault tolerance requirements of this environment. Improvements in virtualization and network technology, combined with the development of key new software tools, may allow the HPC community to effectively take advantage of cheap cloud resources, cutting expensive maintenance costs. this study aims to evaluate the viability of budget-constrained cloud environments for tightly-coupled MPI applications, exploring both spot and traditional low-budget infrastructures from real public cloud platforms. We propose and evaluate two different fault tolerance strategies tailored for unreliable spot cloud environments: system-level rollback restart with Berkeley Labs Checkpoint/Restart (BLCR) and in-memory rollback restart with User-Level Failure Mitigation (ULFM). We also propose a provider-agnostic empirical method for testing and predicting MPI workloads execution times and cloud infrastructure costs. A detailed cost analysis and performance benchmark of a case-study application is provided, with data gathered from experiments with both spot and persistent machines from AWS and Vultr Cloud, respectively. Our results show that: (i) adequate cluster sizing plays an important role in the overall job execution performance and cost-effectiveness, regardless of the type of selected instances;(ii) fault tolerance strategies based on BLCR may have worse performance than ULFM, but still be cost-effective considering software migration costs;(iii) the use of spot infrastructure does not guarantee costs savings depending on the chosen machine flavors and discounts, as experiments with persistent low-budget options attained better c

关键词： high-performance computing Cloud computing Spot Instances Fault Tolerance MPI Virtual Clusters

来源：评论

学校读者我要写书评

暂无评论

Development of More Robust and Stable Logic Gates Using Novel Parameter Values for SiDB 16

Development of More Robust and Stable Logic Gates Using Nove...

引用

16th IEEE Latin American symposium on Circuits and Systems, LASCAS 2025

作者： Ruella, Emanuel V.C. Ferreira, Ricardo S. Vilela Neto, Omar P Nacif, Jose Augusto M. Science and Technology Institute Universidade Federal de Viçosa Brazil Brazil Universidade Federal de Minas Gerais Computer Science Department Brazil Brazil

ISBN: (纸本)9798331522124

As CMOS technology approaches its physical limits, there is a growing need to explore alternatives beyond CMOS, such as Silicon Dangling Bonds (SiDBs). SiDBs, utilizing Coulombic interactions, offer the potential for ultra-low energy consumption and high integration density. Recent research has introduced new parameter values for SiDB technology, specifically the thomas-Fermi Screening Length (Tp=1.80nm) and relative permittivity (r=4.10). this study presents a comprehensive library of logic gates based on these novel values, demonstrating significant stability and interference reduction improvements. Our contributions include: (1) A library of standard Boolean function gates, (2) Additional gates adapted from existing designs, and (3) A detailed comparison of gate performance using new versus old parameter values. the findings indicate that these new parameters enable more robust and compact circuit designs, advancing the potential of SiDB technology. © 2025 IEEE.

关键词： CMOS integrated circuits

来源：评论

学校读者我要写书评

暂无评论

μManycore: A Cloud-Native CPU for Tail at Scale 23

μManycore: A Cloud-Native CPU for Tail at Scale

引用

50th Annual International symposium on computer architecture (ISCA)

作者： Stojkovic, Jovan Liu, Chunao Shahbaz, Muhammad Torrellas, Josep Univ Illinois Champaign IL 61820 USA Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9798400700958

Microservices are emerging as a popular cloud-computing paradigm. Microservice environments execute typically-short service requests that interact with one another via remote procedure calls (often across machines), and are subject to stringent tail-latency constraints. In contrast, current processors are designed for traditional monolithic applications. they support global hardware cache coherence, provide large caches, incorporate microarchitecture for long-running, predictable applications (such as advanced prefetching), and are optimized to minimize average latency rather than tail latency. To address this imbalance, this paper proposes mu Manycore, an architecture optimized for cloud-native microservice environments. Based on a characterization of microservice applications, mu Manycore is designed to minimize unnecessary microarchitecture and mitigate overheads to reduce tail latency. Indeed, rather than supporting manycore-wide hardware cache coherence, mu Manycore has multiple small hardware cache-coherent domains, called Villages. Clusters of villages are interconnected with an on-package leaf-spine network, which has many redundant, low-hop-count paths between clusters. To minimize latency overheads, mu Manycore schedules and queues service requests in hardware, and includes hardware support to save and restore process state when doing a context-switch. Our simulation-based results show that mu Manycore delivers high performance. A cluster of 10 servers with a 1024-core mu Manycore in each server delivers 3.7x lower average latency, 15.5x higher throughput, and, importantly, 10.4x lower tail latency than a cluster with iso-power conventional server-class multicores. Similar good results are attained compared to a cluster with power-hungry iso-area conventional server-class multicores.

关键词： Microservices cloud computing manycore architecture

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共444页 << < 6 7 8 9 10 11 12 13 14 15 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：