Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In safety-critical applications, the risks of such events should be...
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ISBN:
(纸本)9798350332773
Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In safety-critical applications, the risks of such events should be managed to prevent injuries or material damage. this paper provides a comprehensive overview of the challenges associated with designing and verifying safe and reliable systems, as well as the potential of the RISC-V architecture in addressing these challenges. We present several state-of-the-art safety and reliability verification techniques in the design phase. these include a highly-automated verification flow, an automated fault injection and analysis tool, and an AI-based fault verification flow. Furthermore, we discuss core hardening and fault mitigation strategies at the design level. We focus on automated SoC hardening using model-driven development and resilient processing based on sensing and prediction for space and avionic applications. By combining these techniques withthe inherent flexibility of the RISC-V architecture, designers can develop tailored solutions that balance cost, performance, and fault tolerance to meet the requirements of various safety-critical applications in different safety domains, such as avionics, automotive, and space. the insights and methodologies presented in this paper contribute to the ongoing efforts to improve the dependability of computing systems in safety-critical environments.
the proceedings contain 85 papers. the topics discussed include: direct spatial implementation of sparse matrix multipliers for reservoir computing;CAMA: energy and memory efficient automata processing in content-addr...
ISBN:
(纸本)9781665420273
the proceedings contain 85 papers. the topics discussed include: direct spatial implementation of sparse matrix multipliers for reservoir computing;CAMA: energy and memory efficient automata processing in content-addressable memories;leaky frontends: security vulnerabilities in processor frontends;abusing cache line dirty states to leak information in commercial processors;cottage: coordinated time budget assignment for latency, quality and power optimization in web search;enabling efficient large-scale deep learning training with cache coherent disaggregated memory systems;Hercules: heterogeneity-aware inference serving for at-scale personalized recommendation;ANNA: specialized architecture for approximate nearest neighbor search;and hardware-accelerated hypergraph processing with chain-driven scheduling.
Online user dynamics has been actively studied in recent years and bandwagon behavior is one of the most representative topics which can provide valuable insights for user identity change. Many previous studies have c...
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Frequency estimation, a.k.a. histograms, is a workhorse of data analysis, and as such has been thoroughly studied under differentially privacy. In particular, computing histograms in the local model of privacy has bee...
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Currently available automotive radars are designed to stream real-time 2D image data over high-speed links to a central ADAS (Advance Driver-Assistance System) computer for object recognition, which considerably contr...
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ISBN:
(数字)9781665454087
ISBN:
(纸本)9781665454087
Currently available automotive radars are designed to stream real-time 2D image data over high-speed links to a central ADAS (Advance Driver-Assistance System) computer for object recognition, which considerably contributes to the system's power consumption and complexity. this paper presents a preliminary work for the implementation of a new in-sensor computerarchitecture to extract representative features from raw sensor data to detect and identify objects with radar signals. Such new architecture makes it possible to reduce the data transferred between sensors and the central ADAS computer significantly, giving rise to significant energy savings and latency reductions, while still maintaining sufficient accuracy and preserving image details. An experimental prototype has been built using the Texas Instruments AWR1243 Frequency-Modulated Continuous Wave (FMCW) radar board. We carried out experiments using the prototype to collect radar images, to preprocess raw data, and to transfer feature vectors to the central ADAS computer for classification and object detection. Two different approaches will be presented in this paper: First, a vanilla autoencoder will demonstrate the possibility of data reduction on radar signals. Second, a convolutional neural network based cross-domain deep learning architecture is presented by using a sample dataset to show the feasibility of computing Range-Angle Heatmaps directly on the sensor board eliminating the need for the raw data preprocessing on the central ADAS computer. We show that the reconstruction of Range-Angle Heatmaps can be predicted with a very high accuracy by leveraging deep learning architectures. Implementation of such a deep learning architecture on the sensor board can reduce the amount of data transferred from sensors to the central ADAS computer implying great potential for an energy efficient deep learning architecture in such environments.
the field has expanded as supercomputers deal with different characteristics of workloads such as traditional scientific computing and data intensive computing. A batch queue-based Parallel Batch System (PBS) schedule...
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Link Prediction(LP) is a fundamental problem in graph machine learning that aims to predict the existence of links between nodes. Most current research on LP adopts Graph Neural Networks (GNNs) to learn the representa...
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Withthe ever-growing network traffic and the vast amount of abnormal traffic being created, anomaly detection methods have attracted close attention in the cybersecurity domain. Generative adversarial networks (GANs)...
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Optimal resource placement and service placement are key factors for resource utilization and service availability in mobile edge computing (MEC) systems. However, efficiently utilizing the resources of MEC servers fo...
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Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by running software programs on the processor core, requiring no Design for Testability (DfT) infrastructure. Traditionally, the gen...
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