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检索条件"任意字段=16th Symposium on Computer Architecture and High Performance Computing"

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An Image Processing VLIW architecture for Real-Time Depth Detection 28

An Image Processing VLIW Architecture for Real-Time Depth De...

引用

28th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Iorga, Dan Nane, Razvan Lu, Yi Van Dalen, Edwin Bertels, Koen Delft Univ Technol Comp Engn Res Grp Mekelweg 4 NL-2628 CD Delft Netherlands Intel Benelux BV High Tech Campus 83 NL-5656 AG Eindhoven Netherlands

ISBN: (纸本)9781509061082

Numerous applications for mobile devices require 3D vision capabilities, which in turn require depth detection since this enables the evaluation of an object's distance, position and shape. Despite the increasing popularity of depth detection algorithms, available solutions need expensive hardware and/or additional ASICs, which are not suitable for low-cost commodity hardware devices. In this paper, we propose a low-cost and low-power embedded solution to provide high speed depth detection. We extend an existing off-the-shelf VLIW image processor and perform algorithmic and architectural optimizations in order to achieve the requested real-time performance speed. Experimental results show that by adding different functional units and adjusting the algorithm to take full advantage of them, a 640x480 image pair with 64 disparities(1) can be processed at 36.75 fps on a single processor instance, which is an improvement of 23% compared to the best state-of-the-art image processor.

关键词： Stereo vision VLIW

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Profiling and optimization of software-based network-analysis applications 15

Profiling and optimization of software-based network-analysi...

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15th symposium on computer architecture and high performance computing

作者： Degioanni, L Baldi, M Risso, F Varenni, G Politecn Torino Dipartimento Automat & Informat I-10129 Turin Italy

ISBN: (纸本)0769520464

A large set of tools for network monitoring and accounting, security, traffic analysis and prediction more broadly, for network operation and management require direct and efficient real-time access to data traveling on the network. Software tools are often preferred because of their low cost and high versatility. However, these tools are often considered to suffer from performance problems on high-speed networks. this paper demonstrates that, despite the common belief the performance limits for software real-time network analysis tools are still far from being reached and it can even improved with limited hardware support. this work analyzes the performance of a widely used library for network analysis, WinPcap, highlights its bottlenecks, and proposes some solutions that almost double the overall speed, thus enabling the deployment of software-based tools on high speed networks.

关键词： Application software Costs Data security Hardware high-speed networks Monitoring performance analysis Software performance Software tools Telecommunication traffic

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A high performance, Race Eliminated, Two Phase Nonoverlapping Clocked All-N-Logic for both Strong and Subthreshold Designs

A High Performance, Race Eliminated, Two Phase Nonoverlappin...

引用

16th CSI International symposium on computer architectures and Digital Systems (CADS)

作者： Kargar, M. Ghaznavi-Ghoushchi, M. B. Shahed Univ Sch Engn Tehran Iran

ISBN: (纸本)9781467314824;9781467314817

In this paper, a new structure of ANL logic, named TPANL, is presented to achieve higher performance, lower power consumption and eliminating glitches. Different ANL logics suffer from output glitches due to race problem. Our proposed TPANL logic by two phase nonoverlapping clocks eliminates output glitches and reduces glitch power. TPANL logic speedup is mainly due to reduced capacitance at each evaluation node of a dynamic circuit. this logic works in both operational region of strong inversion and subthreshold region, with 1 OGHz to 12.5 MHz respectively. In spite of NonInv./Inv. pipeline in ANL logics, TPANL is based on NonInv./NonInv. pipeline and therefore it solves the voltage drops on NMOS Inv. stages in subthreshold regions. the simulation results of 4-bit CLA adder show 27% and 72.9% power consumption reduction, also, 60% and 50% performance improvement, in strong inversion region rather than ANL and DPANL respectively. the 4-bit CLA adder with TPANL logic in the subthreshold region has about 92nW power consumption.

关键词： Dynamic circuits All-N-Logic (ANL) low power nonoverlapping clocks

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Enabling Efficient Job Dispatching in Accelerator-extended Heterogeneous Systems with Unified Address Space 30

Enabling Efficient Job Dispatching in Accelerator-extended H...

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Kornaros, Georgios Coppola, Marcello Technol Educ Inst Crete Dept Informat Engn Iraklion 71500 Crete Greece STMicroelectronics Grenoble France

ISBN: (纸本)9781538677698

In addition to GPUs that see increasingly widespread use for general-purpose computing, special-purpose accelerators are widely used for their high efficiency and low power consumption, attached to general-purpose CPUs, thus forming Heterogeneous System architectures (HSAs). this paper presents a new communication model for heterogeneous computing, that utilizes a unified memory space for CPUs and accelerators and removes the requirement for virtual-to-physical address translation through an I/O Memory Management Unit (IOMMU), thus making stronger the adoption of Heterogeneous System architectures in SoCs that do not include an IOMMU but still representing a large number in real products. By exploiting user-level queuing, workload dispatching to specialized hardware accelerators allows the removal of drawbacks present when copying objects through using the operating system calls. Additionally, dispatching is structured to enable fixed-size packet management that hardware specialized logic accelerates. To also eliminate IOMMU performance loss and IOMMU management complexity, we propose direct accelerator data placement in contiguous space in system-memory, where, the dispatcher provides trasparent access to the accelerators and at the same time offers an easy abstraction in the programming layer for the application. We demonstrate dispatching rates that exceed ten thousand jobs per second implementing architectural support on a low-cost embedded System-on-Chip, bounded only by the computing capacity of the hardware accelerators.

关键词： Hardware Kernel Graphics processing units Dispatching computer architecture System-on-chip Runtime

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Exploiting loop-level parallelism with the shift architecture 14

Exploiting loop-level parallelism with the shift architectur...

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14th symposium on computer architecture and high performance computing

作者： Lima, CD Nakamura, T Tohoku Univ Grad Sch Informat Sci Comp Architecture Lab Sendai Miyagi 9808579 Japan

ISBN: (纸本)0769517722

the limited amount of instruction-level parallelism inherent in applications is a limiting factor for improving the performance of most conventional microprocessors. A promising solution to overcome this problem is to exploit coarser granularities of parallelism. In this paper we propose exploiting loop-level parallelism in a multithreaded fashion. We use the Shift architecture [9] as a baseline architecture, with improved compiler support and registerfile. the compiler converts iterations of a loop into threads, to be executed by multiple processing elements. the hardware provides a selective register shifting mechanism in order to allow the execution of loops containing loop-carried data dependences, which are very difficult to execute by using conventional architectures. In this paper we simulate and discuss the parameters of major importance for the implementation of this architectural approach. Our initial results show that, on two simple numerical benchmarks, a considerable amount of iteration overlapping can be potentially achieved by an implementation of the Shift architecture, in comparison with a multiprocessor machine.

关键词： Application software computer architecture Continuous improvement Delay Hardware Laboratories Microprocessors Parallel processing Proposals Yarn

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Hybrid system, a new low cost parallel cluster 16

Hybrid system, a new low cost parallel cluster

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16th Annual International symposium on high performance computing Systems and Applications, HPCS 2002

作者： Sim, Leo Chin Schroder, Heiko Leedham, Graham Sch. of Computer Engineering NTU Singapore Singapore Sch of Computer Sc. and IT RMIT Melbourne Australia

ISBN: (纸本)0769516262

this paper describes a new parallel architectural system which we called Hybrid System. As the name implies, Hybrid System is a combination of both SIMD and MIMD systems working concurrently. this new parallel architecture has the capability of achieving speed-up rates more than MIMD can achieve alone and can also be more flexible than multiple SIMD on a single station. In this paper, we introduce our new SIMD concept and also show the contribution of the SIMD on the Hybrid System. We also developed a general formula for determining the speedup of the Hybrid System so that accurate predictions can be made on its performance. this, we establish by comparing the measured speedup with the computed speedup for a volume rendering application. © 2002 IEEE.

关键词： Hybrid systems

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Optimizing Green Energy Consumption of Fog computing architectures 32

Optimizing Green Energy Consumption of Fog Computing Archite...

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32nd IEEE International symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Gougeon, Adrien Camus, Benjamin Orgerie, Anne-Cecile Univ Rennes INRIA CNRS IRISAENS Rennes Rennes France

ISBN: (纸本)9781728199245

the Cloud already represents an important part of the global energy consumption, and this consumption keeps increasing. Many solutions have been investigated to increase its energy efficiency and to reduce its environmental impact. However, with the introduction of new requirements, notably in terms of latency, an architecture complementary to the Cloud is emerging: the Fog. the Fog computing paradigm represents a distributed architecture closer to the end-user. Its necessity and feasibility keep being demonstrated in recent works. However, its impact on energy consumption is often neglected and the integration of renewable energy has not been considered yet. the goal of this work is to exhibit an energy-efficient Fog architecture considering the integration of renewable energy. We explore three resource allocation algorithms and three consolidation policies. Our simulation results, based on real traces, show that the intrinsic low computing capability of the nodes in a Fog context makes it harder to exploit renewable energy. In addition, the share of the consumption from the communication network between the computing resources increases in this context, and the communication devices are even harder to power through renewable sources.

关键词： Fog computing Job scheduling Renewable energy

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Multicore performance Engineering of Sparse Triangular Solves Using a Modified Roofline Model 30

Multicore Performance Engineering of Sparse Triangular Solve...

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Wittmann, Markus Hager, Georg Janalik, Radim Lanser, Martin Klawonn, Axel Rheinbach, Oliver Schenk, Olaf Wellein, Gerhard Friedrich Alexander Univ Erlangen Reg Comp Ctr Erlangen Germany Univ Svizzera Italiana Fac Informat Inst Computat Sci Lugano Switzerland Univ Cologne Fac Math & Nat Sci Cologne Germany TU Bergakad Freiberg Fac Math & Comp Sci Freiberg Germany Friedrich Alexander Univ Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781538677698

the Roofline model is widely used to visualize the performance of executed code together with the upper performance bounds given by the memory bandwidth and the processor peak performance. the model can thus provide an insightful visualization of bottlenecks. In this paper, we try to establish realistic bandwidth ceilings for the sparse triangular solve step of PARDISO, a leading sparse direct solver package, which is also part of the Intel MKL library. the performance of the forward and backward substitution process is analyzed and benchmarked for a representative set of sparse matrices on seven modern x86-type multicore architectures and the Knights Landing manycore architecture. It is shown how to accurately measure the necessary quantities also for threaded code, and the measurement approach, its validation, as well as limitations are discussed. Our modeling approach covers the serial and parallel execution phases, allowing for in-socket performance predictions.

关键词： Sparse matrices Particle separators Analytical models Computational modeling computer architecture Mathematical model Hardware

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Network-aware energy-efficient virtual machine management in distributed Cloud infrastructures with on-site photovoltaic production 30

Network-aware energy-efficient virtual machine management in...

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Camus, Benjamin Dufosse, Fanny Blavette, Anne Quinson, Martin Orgerie, Anne-Cecile Univ Rennes CNRS INRIA IRISA Rennes France INRIA LIG Grenoble France Univ Rennes CNRS SATIE Rennes France

ISBN: (纸本)9781538677698

Distributed Clouds are nowadays an essential component for providing Internet services to always more numerous connected devices. this growth leads the energy consumption of these distributed infrastructures to be a worrying environmental and economic concern. In order to reduce energy costs and carbon footprint, Cloud providers could resort to producing on-site renewable energy, with solar panels for instance. In this paper, we propose NEMESIS: a Network-aware Energy-efficient Management framework for distributEd cloudS Infrastructures with on-Site photovoltaic production. NEMESIS optimizes VM placement and balances VM migration and green energy consumption in Cloud infrastructure embedding geographically distributed data centers with on-site photovoltaic power supply. We use the Simgrid simulation toolbox to evaluate the energy efficiency of NEMESIS against state-of-the-art approaches.

关键词： Distributed cloud computing renewable energy energy-efficient scheduling on-site production network-aware migration consolidation

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Accelerating CNN Algorithm with Fine-grained Dataflow architectures 20

Accelerating CNN Algorithm with Fine-grained Dataflow Archit...

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20th IEEE International Conference on high performance computing and Communications (HPCC) / 16th IEEE International Conference on Smart City (SmartCity) / 4th IEEE International Conference on Data Science and Systems (DSS)

作者： Xiang, Taoran Feng, Yujing Ye, Xiaochun Tan, Xu Li, Wenming Zhu, Yatao Wu, Meng Zhang, Hao Fan, Dongrui Chinese Acad Sci ICT State Key Lab Comp Architecture Beijing Peoples R China UCAS Sch Comp & Control Engn Beijing Peoples R China

ISBN: (纸本)9781538666142

Convolutional Neural Network(CNN) is a hot and state-of-the-art algorithm which is widely used in applications such as face recognition, intelligent monitoring, image recognition and text recognition. Because of its high computational complexity, many efficient hardware accelerators have been proposed to exploit high degree of parallel processing for CNN. However, accelerators which are implemented on FPGAs and ASICs usually sacrifice generality for higher performance and lower power consumption. Other accelerators, such as GPUs, are general enough, but they lead to higher power consumption. Fine-grained dataflow architectures, which break conventional Von Neumann architectures, show natural advantages in processing CNN-like algorithms with high computational efficiency and low power consumption. At the same time, it remains broadly applicable and adaptable. In this paper, we propose a scheme for implementing and optimizing CNN on fine-grained dataflow architecture based accelerators. the experiment results reveal that by using our scheme, the performance of AlexNet running on the dataflow accelerator is 3.11x higher than that on NVIDIA Tesla K80, and the power consumption of our hardware is 8.52x lower than that of K80.

关键词： fine-grained dataflow Convolutional Neural Network general accelerator data reuse high parallel

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