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Optical Interconnects between Microprocessor and Memories 16

Optical Interconnects between Microprocessor and Memories

引用

16th IEEE International Conference on high performance computing and Communications HPCC 2014\11th IEEE International Conference on Embedded Software and Systems ICESS 2014\6th International symposium on Cyberspace Safety and Security CSS 2014

作者： Luo, Daxin Liu, Yaoda Liu, Xiaoying Zhang, Bin Li, Gang Liao, Qi Hao, Qinfen Wei, Zhulin Huawei Technol Co Ltd Shannon Lab Shenzhen Guangdong Peoples R China

ISBN: (纸本)9781479961238

More memories will be required in a future server as the number of cores per microprocessor keeps growing, which means either the capacity of a memory chip or the number of memory chips connected to a microprocessor needs to catch up with the increasing core counts. With electrical interconnects between microprocessor and memories, layout and placement of memory chips around the microprocessor becomes a bottleneck. Optical interconnects will solve this problem by putting memory chips further away from a microprocessor. We investigate in this paper the performance of a computer with optically connected remote memory instead of electrically connected local memory, and verified that an operating system can successfully run with only optically connected memory. the experimental results demonstrated the feasibility of utilizing optically connected remote memory as memory instead of storage as discussed mostly in the literature.

关键词： computer architecture optical interconnects latency microprocessor memory

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SCARF: A Scalable Data Management Framework for Context-Aware Applications in Smart Environments 16

SCARF: A Scalable Data Management Framework for Context-Awar...

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16th EAI International Conference on Mobile and Ubiquitous Systems - computing, Networking and Services (MobiQuitous)

作者： Shin, Eun-Jeong Ghosh, Dhrubajyoti Mehrotra, Sharad Venkatasubramanian, Nalini Univ Calif Irvine Irvine CA 92717 USA

ISBN: (纸本)9781450372831

this paper proposes a context data management framework for efficient context data collection and evaluation to support context-aware applications. the proposed framework named SCARF leverages two architectures: a server-based centralized architecture and an edge-based architecture to address the problem of scalability of context collection and evaluation. SCARF collects the context data efficiently from resource constrained mobile/edge and multiple insitu sensors (not resource constrained) deployed in smart environments. In particular, SCARF takes a set of contextual queries from applications and optimizes the rate at which the context data needs to be collected and/or transmitted from the sensor to the server. Furthermore, SCARF decides whether the code for evaluating context should be executed on the server or on the edge. Execution on the edge will result in reduced communication between the server and the edge but can result in low performance due to resource constraints of the edge. On the other hand, evaluation of context on the server, will require SCARF to transmit sensor data from the sensor to the server but can result in high performance due to high resource availability of the server. SCARF is an adaptive framework which generates an optimal context acquisition plan and a context evaluation plan such that the overall latency is minimized.

关键词： Context-aware applications Mobile computing Smart Environments Scalable Data Management

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I/O performance of multiscale finite element simulations on HPC environments 34

I/O performance of multiscale finite element simulations on ...

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34th IEEE International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Boito, Francieli Gomes, Antonio Tadeu A. Peyrondet, Louis Teylo, Luan Univ Bordeaux LaBRI INRIA Bordeaux INPCNRSUMR 5800 F-33400 Talence France Lab Nacl Comp Cient LNCC Av Getulio Vargas 333 BR-25651075 Petropolis RJ Brazil

ISBN: (数字)9781665451574

ISBN: (纸本)9781665451574

In this paper, we present MSLIO, a code to mimic the I/O behavior of multiscale simulations. Such an I/O kernel is useful for HPC research, as it can be executed more easily and more efficiently than the full simulations when researchers are interested in the I/O load only. We validate MSLIO by comparing it to the I/O performance of an actual simulation, and we then use it to test some possible improvements to the output routine of the MHM (Multiscale Hybrid Mixed) library.

关键词： high-performance computing parallel I/O numeric library I/O kernel mini-app multiscale simulation

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JRastro: A trace agent for debugging multithreaded and distributed Java programs 15

JRastro: A trace agent for debugging multithreaded and distr...

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15th symposium on computer architecture and high performance computing

作者： da Silva, GJ Schnorr, LM Stein, BD Univ Fed Santa Maria Lab Sistemas Computacao BR-97010590 Santa Maria RS Brazil

ISBN: (纸本)0769520464

Program tracing is one of the most used techniques to debug parallel and distributed programs. In this technique, events are recorded in trace files during the execution of the program for post mortem visualization of its behavior this article describes JRastro, a trace agent capable of tracing Java programs. the agent was designed to cover three key features: to be transparent to the application developer to use unmodified Java Virtual Machines and to observe Remote Method Invocations. By integrating these three features, JRastro differentiates itself from similar tools. Unfortunately, for a complete and clean implementation of RMI visualization, additional support on the Java monitoring system is needed.

关键词： computerized monitoring Concurrent computing Condition monitoring Data visualization Debugging Distributed computing Java Remote monitoring Virtual machine monitors Virtual machining

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Applying scheduling by edge reversal to constraint partitioning 15

Applying scheduling by edge reversal to constraint partition...

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15th symposium on computer architecture and high performance computing

作者： Pereira, MR Vargas, PK França, FMG de Castro, MCS Dutra, ID Univ Fed Rio de Janeiro COPPE BR-21945 Rio De Janeiro Brazil

ISBN: (纸本)0769520464

Scheduling by Edge Reversal (SER) is a fully distributed scheduling mechanism based on the manipulation of acyclic orientations of a graph. this work uses SER to perform constraint partitioning of Constraint Satisfaction Problems (CSP). In order to apply the SER mechanism, the graph representing the constraints must receive an acyclic orientation. Since obtaining an optimal acyclic orientation is an NP-hard problem, this work studies three non-deterministic strategies known in the literature: Alg-Neigh, Alg-Edges, and Alg-Colour. We implemented the three algorithms and the SER scheduling mechanism, applying them to the CSP constraint networks generated from 3 applications. Our results show that SER has a great potential to perform a good partitioning of the constraint graphs.

关键词： Concurrent computing Distributed algorithms Distributed computing NP-hard problem Partitioning algorithms Processor scheduling Programming environments Scheduling algorithm System recovery Time factors

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Exploring Power Budget Scheduling Opportunities and Tradeoffs for AMR-based Applications 30

Exploring Power Budget Scheduling Opportunities and Tradeoff...

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30th International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Qin, Yubo Rodero, Ivan Subedi, Pradeep Parashar, Manish Rigo, Sandro Rutgers State Univ Rutgers Discovery Informat Inst RDI2 Piscataway NJ 08854 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781538677698

Computational demand has brought major changes to Advanced Cyber-Infrastructure (ACI) architectures. It is now possible to run scientific simulations faster and obtain more accurate results. However, power and energy have become critical concerns. Also, the current roadmap toward the new generation of ACI includes power budget as one of the main constraints. Current research efforts have studied power and performance tradeoffs and how to balance these (e.g., using Dynamic Voltage and Frequency Scaling (DVFS) and power capping for meeting power constraints, which can impact performance). However, applications may not tolerate degradation in performance, and other tradeoffs need to be explored to meet power budgets (e.g., involving the application in making energy-performance-quality tradeoff decisions). this paper proposes using the properties of AMR-based algorithms (e.g., dynamically adjusting the resolution of a simulation in combination with power capping techniques) to schedule or re-distribute the power budget. It specifically explores the opportunities to realize such an approach using checkpointing as a proof-of-concept use case and provides a characterization of a representative set of applications that use Adaptive Mesh Refinement (AMR) methods, including a Low-Mach-Number Combustion (LMC) application. It also explores the potential of utilizing power capping to understand power-quality tradeoffs via simulation.

关键词： Power demand Task analysis Degradation Power system management Power measurement Two dimensional displays computer architecture

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high performance floating-point unit with 116 bit wide divider

High performance floating-point unit with 116 bit wide divid...

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16th IEEE symposium on computer Arithmetic

作者： Gerwig, G Wetter, H Schwarz, EM Haess, J IBM Corp Server Div Armonk NY 10504 USA

ISBN: (纸本)076951894X

the next generation zSeries floating-point unit is unveiled which is the first IBM mainframe with a fused multiply-add dataflow. It supports both S/390 hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture which was first implemented in S/390 on the 1998 S/390 G5 floating-point unit. the new floating-point unit supports a total of 6 formats including single, double, and quadword formats implemented in hardware. the floating-point pipeline is 5 cycles with a throughput of 1 multiply-add per cycle. Both hexadecimal and binary floating-point instructions are capable of this performance due to a novel way of handling both formats. Other key developments include new methods for handling denormalized numbers and quad precision divide engine dataflow. this divider uses a radix-4 SRT algorithm and is able to handle quad precision divides in multiple floating-point and fixed-point formats. the number of iterations for fixed-point divisions depend on the effective number of quotient bits. It uses a reduced carry-save form for the partial remainder, with only 1 carry bit for every 4 sum bits, to save area and power.

关键词： Digital arithmetic

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high-performance traffic classification on GPU 26

High-performance traffic classification on GPU

引用

26th International symposium on computer architecture and high performance computing, SBAC-PAD 2014

作者： Zhou, Shijie Nittoor, Prashant Rao Prasanna, Viktor K. Ming Hsieh Department of Electrical Engineering University of Southern California Los AngelesCA90089 United States

ISBN: (纸本)9781479969043

Traffic classification is an essential task in network management. Recently, there has been a new trend in exploring Graphics Processing Unit (GPU) for network applications. these applications typically do not perform floating point operations and obtaining speedup can be challenging. In this paper, we design a high-performance traffic classifier based on an alternate representation of the C4.5 decision-tree algorithm and implement it using Compute Unified Device architecture (CUDA). To remedy the unbalanced nature of the decision-trees arising in traffic classification, we convert the C4.5 decision-tree into a set of completely balanced range-trees. Classification is performed by searching the range-trees and merging the search results. We optimize our design by storing the range-trees using compact arrays without explicit pointers in shared memory. By exploiting thread level parallelism, we develop throughput-optimized as well as latency-optimized designs. Experimental results show that for a typical decision-tree containing 128 leaf nodes and 6 features, our design achieves a throughput of over 1600 million classifications per second (MCPS). Compared with the state-of the-art multi-core implementation, our design demonstrates 16x improvement with respect to throughput. We also demonstrate similar performance improvements on a variety of decision-trees with respect to number of leaf nodes, structure of the tree and number of features. © 2014 IEEE.

关键词： Graphics processing unit

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On the Challenge of Training Small Scale Neural Networks on Large Scale computing Systems 16

On the Challenge of Training Small Scale Neural Networks on ...

引用

16th IEEE International symposium on Computational Intelligence and Informatics (CINTI)

作者： Malysiak, Darius Grimm, Matthias Hsch Ruhr West Inst Comp Sci Bottrop Germany

ISBN: (纸本)9781467385206

We present a novel approach of distributing small-to mid-scale neural networks onto modern parallel architectures. In this context we discuss the induced challenges and possible solutions. We provide a detailed theoretical analysis with respect to space and time complexities and reinforce our computation model with evaluations which show a performance gain over state of the art approaches.

关键词： statistics gradient descent gpgpu high performance computing neural networks backpropagation opencl cuda

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ANALYSIS AND OPTIMIZATION OF ENGINES FOR DYNAMICALLY TYPED LANGUAGES 27

ANALYSIS AND OPTIMIZATION OF ENGINES FOR DYNAMICALLY TYPED L...

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IEEE 27th International symposium on computer architecture and high performance computing

作者： Dot, Gem Martinez, Alejandro Gonzalez, Antonio Univ Politecn Cataluna Barcelona Spain ARM Cambridge England

ISBN: (纸本)9781467380119

Dynamically typed programming languages have become very popular in the recent years. these languages ease the task of the programmer but introduce significant overheads since assumptions about the types of variables have to be constantly validated at run time. JavaScript is a widely used dynamically typed language that has gained significant popularity in recent years. In this paper, we provide a detailed analysis of the two main sources of overhead in the JavaScript execution. the first one is the runtime overhead needed for dynamic compilation and housekeeping activities (i.e. garbage collector, compilation, etc.). the second one is the additional checks and guards introduced by the dynamic nature of JavaScript. then, we propose three new HW/SW optimizations that reduce this latter type of overhead. We show that these two types of overhead represent 35% and 25% respectively of the total execution time on average for a representative workload, and the proposed optimizations provide a 6% average speedup.

关键词： Dynamic typed languages Dynamic Compilation computer architecture

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