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Ouroboros: a tool for building generic, hybrid, divide & conquer algorithms

Ouroboros: a tool for building generic, hybrid, divide & con...

引用

International symposium on Parallel and Distributed Processing (IPDPS)

作者： J.R. Johnson I. Foster Department of Computer Science University of Chicago Chicago IL U.S.A. Computing Applns. & Research Dept. Lawrence Livermore Natl. Lab. Livermore CA U.S.A Math and Computer Science Division Argonne National Laboratory Argonne IL U.S.A

Summary form only given. A hybrid divide and conquer algorithm is one that switches from a divide and conquer to an iterative strategy at a specified problem size. Such algorithms can provide significant performance improvements relative to alternatives that use a single strategy. However, the identification of the optimal problem size at which to switch for a particular algorithm and platform can be challenging. We describe an automated approach to this problem that first conducts experiments to explore the performance space on a particular platform and then uses the resulting performance data to construct an optimal hybrid algorithm on that platform. We implement this technique in a tool, Ouroboros, that automatically constructs a high-performance hybrid algorithm from a set of registered algorithms. We present results obtained with this tool for several classical divide and conquer algorithms, including matrix multiply and sorting, and report speedups of up to six times achieved over nonhybrid algorithms.

关键词： Algorithm design and analysis Iterative algorithms Sorting Switches computer science Laboratories Space exploration Read-write memory Software algorithms computer architecture

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Reconfigurable molecular dynamics simulator

Reconfigurable molecular dynamics simulator

引用

Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： N. Azizi I. Kuon A. Egier A. Darabiha P. Chow Department of ECE University of Toronto Toronto ONT Canada

Current high-performance applications are typically implemented on large-scale general-purpose distributed or multiprocessing systems often based on commodity microprocessors. Field-Programmable Gate Arrays (FPGAs) have now reached a level of sophistication that they too could be used for such applications. In this paper we explore the feasibility of using FPGAs to implement large-scale application-specific computations by way of a case study that implements a novel molecular dynamics system. the system has been designed such that it is scalable and parallelizable. On the Transmogrifier 3 (TM3), the system performs calculations on an 8,192 particle system in 37 seconds at 26 MHz. this implementation shows that by scaling to more modern parts running at 100 MHz, a speedup of over 20 x can be achieved compared to a state-of-the-art microprocessor. this can also be achieved at less cost, using less power and taking less space than a standard microprocessor-based system, while maintaining the computational precision required.

关键词： Application specific processors Field programmable gate arrays Large-scale systems Microprocessors Space technology computer architecture Multiprocessing systems computer applications Application software Buildings

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Benchmark performance on cluster grid with NGB

Benchmark performance on cluster grid with NGB

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： L. Peng S. See J. Song A. Stoelwinder H.K. Neo Asia Pacific Science and Technology Center Sun Microsystems Inc. Nanyang Center for Supercomputing and Visualization Nanyang Technological University Singapore

Summary form only given. Along with the development of computational grids, it is more and more desirable to evaluate performance of the grids by using standard benchmarks. However, few benchmark suites have been developed and widely used so far, which results in an obstacle to the wide acceptance of grid in current e-science age. Meanwhile, the dynamic and heterogeneous nature of grid environment makes performance evaluation and its generic applicability challenging. NGB (NAS Grid Benchmarks) is a recently proposed benchmark suite for computational grids. In this paper, we use NGB to evaluate the performance of cluster grid with Sun Grid Engine and Globus, which are basic components of the campus grid in our university. the performance metrics we used include turnaround time and CPU utilization. Our preliminary experimental results show that the Sun Grid Engine's overhead is less than that of Globus because Globus has more procedures in job submission, both of them become negligible when the problem size increases. Moreover, in NGB less loosely coupled grid applications may not necessary result in higher resource utilization, due to various characteristics of applications.

关键词： Grid computing Sun Engines Benchmark testing Resource management high performance computing Middleware computer architecture Asia Visualization

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Design and implementation of MPICH2 over InfiniBand with RDMA support

Design and implementation of MPICH2 over InfiniBand with RDM...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： J. Liu W. Jiang P. Wyckoff D.K. Panda D. Ashton D. Buntinas W. Gropp B. Toonen Computer and Information Science Ohio State Uinversity Columbus OH USA Ohio Supercomputer Center Columbus OH USA Mathematics and Computer Science Division Argonne National Laboratory Argonne IL USA

Summary form only given. For several years, MPI has been the de facto standard for writing parallel applications. One of the most popular MPI implementations is MPICH. Its successor, MPICH2, features a completely new design that provides more performance and flexibility. To ensure portability, it has a hierarchical structure based on which porting can be done at different levels. In this paper, we present our experiences in designing and implementing MPICH2 over InfiniBand. Because of its high performance and open standard, InfiniBand is gaining popularity in the area of high-performance computing. Our study focuses on optimizing the performance of MPl-1 functions in MPICH2. One of our objectives is to exploit remote direct memory access (RDMA) in InfiniBand to achieve high performance. We have based our design on the RDMA channel interface provided by MP1CH2, which encapsulates architecture-dependent communication functionalities into a very small set of functions. Starting with a basic design, we apply different optimizations and also propose a zero-copy-based design. We characterize the impact of our optimizations and designs using microbenchmarks. We have also performed an application-level evaluation using the NAS parallel benchmarks. Our optimized MPICH2 implementation achieves 7.6/spl mu/s latency and 857 MB/s bandwidth, which are close to the raw performance of the underlying InfiniBand layer. Our study shows that the RDMA channel interface in MPICH2 provides a simple, yet powerful, abstraction that enables implementations with high performance by exploiting RDMA operations in InfiniBand. To the best of our knowledge, this is the first high-performance design and implementation ofMPICH2 on InfiniBand using RDMA support.

关键词： Concurrent computing Laboratories Writing Design optimization Delay Bandwidth Access protocols Communication standards Information science Supercomputers

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Ultrasound therapy system and ablation results utilizing miniature imaging/therapy arrays

Ultrasound therapy system and ablation results utilizing min...

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IEEE symposium (IUS) Ultrasonics

作者： P.G. Barthe M.H. Slayton P.M. Jaeger I.R.S. Makin L.A. Gallagher T.D. Mast M.M. Runk W. Faid Guided Therapy Systems Mesa AZ USA Ethicon Endo-Surgery Cincinnati OH USA

Array-based imaging and therapy systems have several advantages over single element approaches, and it was previously shown that the imaging and therapy functionality may be combined into dual-mode arrays. In this work, minimally invasive, miniature (2.2 mm /spl times/ 50 mm aperture, 3.3 mm diameter) dual-mode linear arrays have been developed into probes with high acoustic power output (100 W, and >120 W/cm/sup 2/ at the source), high transmit efficiency (>65% typical), and good imaging performance (3.4 MHz center frequency, 50% fractional bandwidth, >100 mm deep field of view). these therapy / imaging probes have been integrated into a flexible intense ultrasound surgery platform which also includes conventional diagnostic imaging probes. A system architecture has been developed which includes a 64-channel therapy driver with software selection of array aperture and phasing (1/16th wavelength), frequency (0.5-8 MHz), drive amplitude (5 W/channel, nominal), mechanical rotational steering (/spl plusmn/180 degrees), and temporal sequencing/switching of imaging, and therapy modes. the array-based imaging/therapy system has produced encouraging results in preclinical studies of bulk tissue ablation, imaging and treatment monitoring of liver in vitro and in vivo, examples of which are presented. the system can be applied to ablation of other soft tissue pathologies, e.g. kidney, heart, uterus, brain, GI, etc.

关键词： Ultrasonic imaging Medical treatment Acoustic imaging Probes Apertures Frequency Minimally invasive surgery Acoustic arrays Bandwidth computer architecture

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An IPSec-aware TCP PEP for integrated mobile satellite networks

An IPSec-aware TCP PEP for integrated mobile satellite netwo...

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IEEE International symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： G. Ciccarese M. De Blas L. Patrono P. Marra G. Tomasicchio Dep. of Innovation Engineering University of Lecce Lecce Italy Universita del Salento Lecce Puglia IT Dept. of Innovation Eng. Lecce Univ. Italy Business Multimedia Unit Alenia Spazio Rome Italy

Mobile computing and security in Internet have become two of the most important challenges in the information technology world. Among wireless technologies which support user mobility, satellites will play a very important role. Unfortunately, TCP does not perform well on satellite channels because of the related high delay-bandwidth product, high bit error rate (BER) and burst errors mainly due to shadowing. In order to obtain improvements in TCP performance, an approach local to the satellite link could be adopted. In fact, recently, some studies showed the effectiveness of the use of a reliable data link protocol that is well suited to mobile geo-stationary satellite channel characteristics. However, the resultant more variable end-to-end delay causes, as a side effect, a new problem: the competition between retransmission mechanisms at transport layer and data link layer. the introduction of a suitable performance enhancing proxy (PEP) on the satellite gateway has proved to be a viable technique to face the problem. However, the compatibility with the usage of network layer security mechanisms, such as IPSec, should be pursued. this paper just deals with the definition of an IPSec-aware TCP PEP, called secure PEP (SPEP), that is completely transparent to IPSec architecture. the performances of SPEP have been validated in the context of Web application by using network simulator tool. the simulation results, in terms of Web-page download mean time, have shown that the proposed solution provides substantial improvements in TCP performance.

关键词： Satellites Bit error rate Mobile computing Information security Internet Information technology Communication system security Delay computer errors Shadow mapping

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System-level fault-tolerance in large-scale parallel machines with buffered coscheduling

System-level fault-tolerance in large-scale parallel machine...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： F. Petrini K. Davis J.C. Sancho Performance and Architecture Laboratory (PAL) Computer and Computational Sciences (CCS) Division Los Alamos National Laboratory NM USA

Summary form only given. As the number of processors for multiteraflop systems grows to tens of thousands, with proposed petaflops systems likely to contain hundreds of thousands of processors, the assumption of fully reliable hardware has been abandoned. Although the mean time between failures for the individual components can be very high, the large total component count will inevitably lead to frequent failures. It is therefore of paramount importance to develop new software solutions to deal with the unavoidable reality of hardware faults. We will first describe the nature of the failures of current large-scale machines, and extrapolate these results to future machines. Based on this preliminary analysis we will present a new technology that we are currently developing, buffered coscheduling, which seeks to implement fault tolerance at the operating system level. Major design goals include dynamic reallocation of resources to allow continuing execution in the presence of hardware failures, very high scalability, high efficiency (low overhead), and transparency - requiring no changes to user applications. Preliminary results show that this is attainable with current hardware.

关键词： Fault tolerant systems Large-scale systems Parallel machines Hardware Laboratories Supercomputers Operating systems Application software Concurrent computing computer aided manufacturing

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Analysis and evaluation of topological and application characteristics of unreliable mobile wireless ad-hoc network

Analysis and evaluation of topological and application chara...

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Pacific Rim International symposium on Dependable computing

作者： S. Cabuk N. Malhotra L. Lin S. Bagchi N. Shroff School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

We present a study of topological characteristics of mobile wireless ad-hoc networks. the characteristics studied are connectivity, coverage, and diameter. Knowledge of topological characteristics of a network aids in the design and performance prediction of network protocols. We introduce intelligent goal-directed mobility algorithms for achieving desired topological characteristics. A simulation-based study shows that to achieve low, medium and high network QoS defined in terms of combined requirements of the three metrics, the network needs respectively 8, 16, and 40 nodes. If nodes can fail, the requirements increase to 8, 36 and 60 nodes respectively. We present a theoretical derivation of the improvement due to the mobility models and the sufficient condition for 100% connectivity and coverage. Next, we show the effect of improved topological characteristics in enhancing QoS of an application level protocol, namely, a location determination protocol called Hop-Terrain. the study shows that the error in location estimation is reduced by up to 68% with goal-directed mobility.

关键词： Ad hoc networks Protocols Sensor phenomena and characterization Mobile ad hoc networks Wireless sensor networks Radio frequency computer networks Signal processing algorithms Actuators Application software

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A way-halting cache for low-energy high-performance systems

A way-halting cache for low-energy high-performance systems

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International symposium on Low Power Electronics and Design (ISLPED)

作者： Chuanjun Zhang F. Vahid Jun Yang W. Najjar Department of Electrical Engineering University of California Riverside USA Department of Computer Science and Engineering University of California Riverside USA

Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. the look-up in the hall tag array is done in parallel with, and is no slower than, the set-index decoding. the hall tag array pre-determines which tags cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has an additional feature of using static logic only, rather than dynamic logic used in highly associative caches. We provide data from experiments on 17 benchmarks drawn from MediaBench and Spec 2000, based on our layouts in 0.18 micron CMOS technology, On average, 55% savings of memory-access related energy were obtained over a conventional four-way set-associative cache. We show that energy savings are greater than previous methods, and nearly twice that of highly-associative caches, while imposing no performance overhead and only 2% cache area overhead.

关键词： Logic arrays Energy consumption CMOS logic circuits computer science Power engineering and energy Embedded computing Microprocessors Decoding Costs Permission

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Proceedings - symposium on computer architecture and high performance computing

Proceedings - Symposium on Computer Architecture and High Pe...

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15th symposium on computer architecture and high performance computing, SBAC-PAD 2003

ISBN: (纸本)0769520464

the proceedings contain 30 papers. the topics discussed include: adaptive compressed caching: design and implementation;enabling dual-core mode in BlueGene/L: challenges and solutions;complex branch profiling for dynamic conditional execution;the limits of speculative trace reuse on deeply pipelined processors;performance analysis of DECK collective communication service;a modeling methodology and pre-runtime scheduling for embedded real-time software;performance issues of bandwidth reservations for grid computing;an evaluation of cJava system architecture;ProGrid: a proxy-based architecture for grid operation and management;optimizing packet capture on symmetric multiprocessing machines;a parallel implementation of the LTSn method for a radiative transfer problem;and parallel implementation of a lattice-gauge-theory code: studying quark confinement on PC Clusters.

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