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9th International symposium on high-performance computer architecture

作者： Ibrahim, KZ Byrd, GT Rotenberg, E N Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA

ISBN: (纸本)0769518710

Scalability of applications on distributed shared-memory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism yields diminishing returns or even degrades performance. When increasing concurrency is futile, we propose an additional mode of execution, called slipstream mode, that instead enlists extra processors to assist parallel tasks by reducing perceived overheads. We consider DSM multiprocessors built from dual-processor chip multiprocessor (CMP) nodes with shared L2 cache. A task is allocated on one processor of each CMP node. the other processor of each node executes a reduced version of the same task. the reduced version skips shared-memory stores and synchronization, running ahead of the true task. Even with the skipped operations, the reduced task makes accurate forward progress and generates an accurate reference stream, because branches and addresses depend primarily on private data. Slipstream execution mode yields two benefits. First, the reduced task prefetches data on behalf of the true task. Second, reduced tasks provide a detailed picture of future reference behavior, enabling a number of optimizations aimed at accelerating coherence events, e.g., self-invalidation. For multiprocessor systems with up to 16 CMP nodes, slipstream, mode outperforms running one or two conventional tasks per CMP in 7 out of 9 parallel scientific benchmarks. Slipstream mode is 12-19% faster with prefetching only and up to 29% faster with self-invalidation enabled.

关键词： Acceleration Character generation Coherence Concurrent computing Degradation Multiprocessing systems Parallel processing performance gain Prefetching Scalability

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FPGA-based SIMD processor 11

FPGA-based SIMD processor

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11th Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM 2003)

作者： Li, SYC Cheuk, GCK Lee, KH Leong, PHW Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin Hong Kong Peoples R China

ISBN: (纸本)0769519792

A massively parallel single instruction multiple data stream (SIMD) processor designed specifically for cryptographic key search applications is presented. this design aims to exploit fine grain parallelism and the high memory bandwidth available in an FPGA by integrating 95 simple processors and memory on a single FPGA chip. performance is compared with a previously reported hardwired design on a RC4 key search application.

关键词： Application software computer science Decoding Field programmable gate arrays Process design Random access memory Read-write memory Registers Software performance Testing

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Catching accurate profiles in hardware 9

Catching accurate profiles in hardware

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9th International symposium on high-performance computer architecture

作者： Narayanasamy, S Sherwood, T Sair, S Calder, B Varghese, G Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92103 USA

ISBN: (纸本)0769518710

Run-time optimization is one of the most important ways of getting performance out of modern processors. Techniques such as prefetching, trace caching, memory disambiguation etc., are all based upon the principle of observation followed by adaptation, and all make use of some sort of profile information gathered at run-time. Programs are very complex, and the real trick in generating useful run-time profiles is sifting through all the unimportant and infrequently occurring events to find those that are important enough to warrant optimization. In this paper, we present the Multi-Hash architecture to catch important events even in the presence of extensive noise. Multi-hash uses a small amount of area, between 7 to 16 Kilobytes, to accurately capture these important events in hardware, without requiring any software support. this is achieved using multiple hash tables for the filtering, and interval-based profiling to help identify how important an event is in relationship to all the other events. We evaluate our design for value and edge profiling, and show that over a set of benchmarks, we get an average error less than 1%.

关键词： computer architecture computer errors computer science Filtering Hardware Prefetching Runtime Software systems Software tools System software

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A configurable network protocol for cluster based communications using modular hardware primitives on an intelligent NIC 11

A configurable network protocol for cluster based communicat...

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11th Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM 2003)

作者： Jaganathan, RG Underwood, KD Sass, R Clemson Univ ECE Dept Parallel Architecture Res Lab Clemson SC 29634 USA

ISBN: (纸本)0769519792

the high overhead of generic protocols like TCP/IP provides strong motivation for the development of a better protocol architecture for cluster-based parallel computers. Reconfigurable computing has a unique opportunity to contribute hardware level protocol acceleration while retaining the flexibility to adapt to changing needs. thus, it is possible to provide application-specific protocol processing to improve performance and to reduce space utilization. Reducing space utilization permits the use of a greater portion of the FPGA for other application-specific processing. this paper focuses on work to create a set of components that can be put together as needed to obtain a customized protocol for each application. the components are parameterizable, increasing the protocol's flexibility. To study the feasibility of such an architecture, hardware components for the reconfigurable logic on the NIC were built such that they can be stitched together as required to provide the required functionality. Feasibility is demonstrated using four different protocol configurations in this paper the different configurations illustrate trade-offs between chip space and functionality.

关键词： computer architecture Delay Electronic mail Hardware Intelligent networks Laboratories Parallel architectures Protocols Switches Table lookup

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NSM: A distributed storage architecture for data-intensive applications 20

NSM: A distributed storage architecture for data-intensive a...

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20th IEEE Conference on Mass Storage Systems and Technology/11th NASA Goddard Conference on Mass Storage Systems and Technology

作者： Ali, Z Malluhi, Q Jackson State Univ Dept Comp Sci Distributed Comp Lab Jackson MS 39217 USA

ISBN: (纸本)0769519148

Several solutions have been developed to provide data-intensive applications with the highest possible data rates. Such solutions tried to utilize the available network resources through parallel I/O and TCP/IP tuning in order to achieve a better data throughput. the focus was on achieving the highest possible data rate while other performance enhancements factors were ignored. Furthermore, most of those solutions were point solutions and designed to work in a specific environment for a particular application. In this paper, we introduce the Network Storage Manager (NSM). NSM is a java-based, high-performance, distributed storage system with auto reconfigurability that has been developed in the Distributed computing Laboratory at Jackson State University. the system is designed as a framework for data-intensive distributed applications of different natures. In addition to an architecture that employs parallelism, scalability, crash recovery, and portability, NSM provides applications with full control to optimize other application-controllable features by allowing applications to fine-tune. such features or even plug-in their modules and use it instead of the standard NSM implementation.

关键词： computer architecture computer crashes computer network management Distributed computing Java Laboratories Parallel processing Scalability TCPIP throughput

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A performance study of monitoring and information services for distributed systems 12

A performance study of monitoring and information services f...

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12th IEEE International symposium on high performance Distributed computing, HPDC 2003

作者： Zhang, Xuechai Freschl, Jeffrey L. Schopf, Jennifer M. Department of Computer Science University of Chicago IL United States Department of Computer Science University of California at Santa Cruz United States Mathematics and Computer Science Division Argonne National Laboratory Australia

ISBN: (纸本)0769519652

Monitoring and information services form a key component of a distributed system, or Grid. A quantitative study of such services can aid in understanding the performance limitations, advise in the deployment of the monitoring system, and help evaluate future development work. To this end, we study the performance of three monitoring and information services for distributed systems: the Globus Toolkitreg/Monitoring and Discovery Service (MDS2), the European Data Grid Relational Grid Monitoring architecture (R-GMA) and Hawkeye, part of the Condor project. We perform experiments to test their scalability with respect to number of users, number of resources and amount of data collected. Our study shows that each approach has different behaviors, often due to their different design goals. In the four sets of experiments we conducted to evaluate the performance of the service components under different circumstances, we found a strong advantage to caching or pre-fetching the data, as well as the need to have primary components at well-connected sites because of the high load seen by all systems. © 2003 IEEE.

关键词： computer architecture

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Proceedings of the IEEE International symposium on high performance Distributed computing

Proceedings of the IEEE International Symposium on High Perf...

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12th IEEE International symposium on high performance Distributed computing, HPDC 2003

ISBN: (纸本)0769519652

the proceedings contain 25 papers. the topics discussed include: impact of high performance sockets on data intensive applications;performance analysis of scheduling and replication algorithms on grid datafarm architecture for high-energy physics applications;security for grid services;trace-based simulations of processor co-allocation policies in multiclusters;policy driven heterogeneous resource co-allocation with gangmatching;dynamic virtual clusters in a grid site manager;grid workflow: a flexible failure handling framework for the grid;pipeline and batch sharing in grid workloads;SODA: a service-on-demand architecture for application service hosting utility platforms;and using views for customizing reusable components in component-based frameworks.

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Towards merging context-aware, mobile and grid computing

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INTERNATIONAL JOURNAL OF high performance computing APPLICATIONS 2003年第2期17卷 191-203页

作者： Yamin, AC Barbosa, JV Augustin, I da Silva, LC Real, R Geyer, C Cavallheiro, G Univ Catolica Pelotas Dept Informat Pelotas RS Brazil Univ Fed Santa Maria Comp & Elect Dept BR-97119900 Santa Maria RS Brazil Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil Univ Vale Rio dos Sinos PIP CA Ctr 6 Sao Leopoldo RS Brazil

ISAM is a proposal directed to supporting physical and logical mobility, context-awareness, dynamic adaptation and the execution of large-scale distributed applications In order to achieve its goals, ISAM uses, as strategy, an integrated environment that provides: (a) a programming language;(b) an execution environment;(c) a context recognition server. the integration is accomplished through an adaptation process that uses a multilevel collaborative model, in which both the system and the application contribute for that. In this paper we discuss the main components used to implement the ISAM features, and we also present a distributed application that explores some of this features.

关键词： context-aware applications Grid computing Adaptive Execution

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A performance evaluation of memory hierarchy in embedded systems 35

A performance evaluation of memory hierarchy in embedded sys...

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35th Southeastern symposium on System theory

作者： Milenkovic, A Milenkovic, N Barnes, N Univ Alabama Dept Elect & Comp Engn Huntsville AL 35899 USA

ISBN: (纸本)0780376978

the increasing speed gap between processors and memory makes the design of memory hierarchy one of the critical issues in general purpose embedded systems. As memory requirements for embedded applications grow, especially in emerging area of handheld multimedia devices, cache memories become crucial for providing high performance and reducing power. this paper describes a performance evaluation of typical cache design issues such as cache size and organization, block size, and replacement policy. the evaluation is done using simulation tools for architectural exploration based on ARM instruction set and MiBench benchmark suite. Our performance evaluation includes monitoring of dynamic cache behavior, since embedded systems designers are interested not only in the total number of cache misses, but also in the number of cache misses throughout application execution.

关键词： Cache memory Clocks computer architecture computer industry Costs Design engineering Embedded computing Embedded system Monitoring performance gain

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Boosting performance of I/O-intensive workload by preemptive job migrations in a cluster system 15

Boosting performance of I/O-intensive workload by preemptive...

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15th symposium on computer architecture and high performance computing, SBAC-PAD 2003

作者： Qin, X. Jiang, H. Zhu, Y. Swanson, D.R. Department of Computer Science and Engineering University of Nebraska-Lincoln LincolnNE68588-0115 United States

ISBN: (纸本)0769520464

Load balancing in a cluster system has been investigated extensively, mainly focusing on the effective usage of global CPU and memory resources. However, if a significant portion of applications running in the system is I/O-intensive, traditional load balancing policies that focus on CPU and memory usage may cause the system performance to decrease substantially. To solve this problem, a new I/O-aware load-balancing scheme with preemptive job migration is presented to sustain the high performance of a cluster with a diverse set of workload conditions. the proposed scheme dynamically detects I/O load imbalance on nodes of a cluster, and determines whether to preempt some running jobs on overloaded nodes and migrate them to other less- or under-loaded nodes. Besides balancing I/O load, the scheme takes into account both CPU and memory load sharing in clusters, thereby maintaining the same level of performance as existing schemes when I/O load is low or well balanced. Results from a trace-driven simulation show that, compared to the existing approaches that only consider I/O with nonpreemptive job migrations, the proposed schemes achieve the improvement in mean slowdown by up to a factor of 10. © 2003 IEEE.

关键词： Remote sensing

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