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检索条件"任意字段=16th Symposium on Computer Architecture and High Performance Computing"

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high performance floating-point unit with 116 bit wide divider

High performance floating-point unit with 116 bit wide divid...

引用

computer Arithmetic (ARIth)

作者： G. Gerwig H. Wetter E.M. Schwarz J. Haess IBM Division Germany IBM Division USA

the next generation zSeries floating-point unit is unveiled which is the first IBM mainframe with a fused multiply-add dataflow. It supports both S/390 hexadecimal floating-point architecture and the IEEE 754 binary floating-point architecture which was first implemented in S/390 on the 1998 S/390 G5 floating-point unit. the new floating-point unit supports a total of 6 formats including single, double, and quadword formats implemented in hardware. the floating-point pipeline is 5 cycles with a throughput of 1 multiply-add per cycle. Both hexadecimal and binary floating-point instructions are capable of this performance due to a novel way of handling both formats. Other key developments include new methods for handling denormalized numbers and quad precision divide engine dataflow. this divider uses a radix-4 SRT algorithm and is able to handle quad precision divides in multiple floating-point and fixed-point formats. the number of iterations for fixed-point divisions depend on the effective number of quotient bits. It uses a reduced carry-save form for the partial remainder, with only 1 carry bit for every 4 sum bits, to save area and power.

关键词： Digital arithmetic

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Boosting performance of I/O-intensive workload by preemptive job migrations in a cluster system

Boosting performance of I/O-intensive workload by preemptive...

引用

International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： X. Qin H. Jiang Y. Zhu D.R. Swanson Department of Computer Science and Engineering University of Nebraska Lincoln Lincolnshire NE USA

Load balancing in a cluster system has been investigated extensively, mainly focusing on the effective usage of global CPU and memory resources. However, if a significant portion of applications running in the system is I/O-intensive, traditional load balancing policies that focus on CPU and memory usage may cause the system performance to decrease substantially. To solve this problem, a new I/O-aware load-balancing scheme with preemptive job migration is presented to sustain the high performance of a cluster with a diverse set of workload conditions. the proposed scheme dynamically detects I/O load imbalance on nodes of a cluster, and determines whether to preempt some running jobs on overloaded nodes and migrate them to other less- or under-loaded nodes. Besides balancing I/O load, the scheme takes into account both CPU and memory load sharing in clusters, thereby maintaining the same level of performance as existing schemes when I/O load is low or well balanced. Results from a trace-driven simulation show that, compared to the existing approaches that only consider I/O with nonpreemptive job migrations, the proposed schemes achieve the improvement in mean slowdown by up to a factor of 10.

关键词： Boosting Load management System performance computer science Application software Computational modeling Remote sensing Bridges Costs throughput

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Iterated robust tabu search for MAX-SAT 1

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16th Conference of the Canadian Society for Computational Studies of Artificial Intelligence, AI 2003

作者： Smyth, Kevin Hoos, Holger H. Stützle, thomas Department of Computer Science University of British Columbia VancouverBCV6T 1Z4 Canada Fachbereich Informatik Technische Universität Darmstadt Alexanderstr. 10 DarmstadtD-64289 Germany

ISBN: (数字)9783540448860

ISBN: (纸本)3540403000

MAX-SAT, the optimisation variant of the satisfiability problem in propositional logic, is an important and widely studied combinatorial optimisation problem with applications in AI andot her areas of computing science. In this paper, we present a new stochastic local search (SLS) algorithm for MAX-SAT that combines IteratedLo cal Search and Tabu Search, two well-known SLS methods that have been successfully appliedt o many other combinatorial optimisation problems. the performance of our new algorithm exceeds that of current state-of-the-art MAX-SAT algorithms on various widely studied classes of unweighted andw eighted MAX-SAT instances, particularly for Random-3-SAT instances with high variance clause weight distributions. We also report promising results for various classes of structuredM AX-SAT instances. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Tabu search

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A BSP/CGM algorithm for computing Euler tours in graphs

A BSP/CGM algorithm for computing Euler tours in graphs

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： E.N. Caceres C.Y. Nasu Universidade Federal de Mato Grosso do Sul Campo Grande Mato Grosso do Sul Brazil

We describe a parallel algorithm using the BSP/CGM model (Bulk Synchronous Parallel/Coarse Grained Multicomputer) to obtain the Euler tours in graphs. It is based on the PRAM (parallel random access machine) algorithm by Caceres et al. For an input graph of n vertices and m edges, the algorithm requires local computation time of O((m+n)/p), O((m+n'p) memory and O(logp) communication rounds, where p is the number of processors. To our knowledge there are no other parallel algorithms under the coarse-grained models for the Euler tours in graphs. the proposed algorithm is implemented using MPI (message passing interface) and the C language. the parallel program runs on a Beowulf with 66 nodes. the implementation results confirm the theoretical complexity results of the algorithm.

关键词： User-generated content Bridges Parallel algorithms Phase change random access memory Cities and towns Message passing Graph theory Rivers Search methods Data structures

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Accelerating sine and cosine evaluation with compiler assistance

Accelerating sine and cosine evaluation with compiler assist...

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computer Arithmetic (ARIth)

作者： P. Markstein Hewlett Packard Laboratories Palo Alto CA USA

Some software libraries add special entry points to enable both the sine and cosine to be evaluated with one call for performance purposes. We propose another method which does not involve new function names. By having the compiler front end recognize trigonometric function invocations, and replace them with a call to a common function which executes the code common to all the functions, followed by a short routine to produce the desired computation, it is possible to compute both the sine and cosine, when needed in about the same time as to compute only one of them.

关键词： Acceleration Laboratories Milling machines Software libraries Code standards Functional programming Programming profession Concurrent computing Algorithms Optimizing compilers

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Adaptive compressed caching: design and implementation

Adaptive compressed caching: design and implementation

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： R.S. de Castro A.P.D. Lago D. da Silva Department of Computer Science Universidade de Sáo Paulo Brazil IBM T.J IBM Thomson J.Watson Research Center USA

We reevaluate the use of adaptive compressed caching in order to improve system performance through reduction of accesses to the backing stores. We propose a new and simple adaptability policy that adjusts the compressed cache size on-the-fly, and evaluate a compressed caching system with this policy through an implementation in a widely used operating system, Linux. We also redesign compressed caching in order to provide performance improvements for all tested workloads and address the problems faced in previous works and implementations that led to nonconclusive results. Among these fundamental modifications, our compressed cache is the first one to also compress file cache pages, to adaptively disable compression of clean pages when necessary and to address applications with poor compressibility. We tested a system with our adaptive compressed cache under many applications and benchmarks, each one with different memory pressures. the results showed performance improvements (up to 171.4%) in all of them if under memory pressure, and minimal overhead (up to 0.39%) when there is very light memory pressure. We show that this adaptive compressed cache design is actually considered as an effective mechanism for improvement in system performance.

关键词： System performance Operating systems Linux Kernel computer science System testing Adaptive systems Benchmark testing Data compression Hard disks

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Applying scheduling by edge reversal to constraint partitioning

Applying scheduling by edge reversal to constraint partition...

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International symposium on computer architecture and high performance computing (SBAC-PAD)

作者： M.R. Pereira P.K. Vargas F.M.G. Franca M.C.S. de Castro I. de Castro Dutra COPPE-Engenharia de Sistemas e Computação Universidade Federal do Rio de Janeiro Rio de Janeiro Rio de Janeiro Brazil Instituto de Matemática e Estatística Universidade Estadual do Rio de Janeiro Rio de Janeiro Rio de Janeiro Brazil

Scheduling by edge reversal (SER) is a fully distributed scheduling mechanism based on the manipulation of acyclic orientations of a graph. this work uses SER to perform constraint partitioning of constraint satisfaction problems (CSP). In order to apply the SER mechanism, the graph representing the constraints must receive an acyclic orientation. Since obtaining an optimal acyclic orientation is an NP-hard problem, we study three nondeterministic strategies known in the literature: Alg-Neigh, Alg-Edges, and Alg-Colour. We implemented the three algorithms and the SER scheduling mechanism, applying them to the CSP constraint networks generated from 3 applications. Our results show that SER has a great potential to perform a good partitioning of the constraint graphs.

关键词： Processor scheduling Distributed computing NP-hard problem Partitioning algorithms Scheduling algorithm Time factors Concurrent computing Programming environments Distributed algorithms System recovery

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Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS arc...

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Annual International symposium on computer architecture, ISCA

作者： K. Sankaralingam R. Nagarajan Haiming Liu Changkyu Kim Jaehyuk Huh D. Burger S.W. Keckler C.R. Moore Computer Architecture and Technology Laboratory Department of Computer Sciences University of Texas Austin USA

We describe the polymorphous TRIPS architecture, which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism. To adapt to small and large-grain concurrency, the TRIPS architecture contains four out-of-order, 16-wide-issue grid processor cores, which can be partitioned when easily extractable fine-grained parallelism exists. this approach to polymorphism provides better performance across a wide range of application types than an approach in which many small processors are aggregated to run workloads with irregular parallelism. Our results show that high performance can be obtained in each of the three modes-ILP, TLP, and DLP-demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.

关键词： Parallel processing computer architecture Hardware Concurrent computing Out of order Microprocessors Streaming media Process design Space technology Field programmable gate arrays

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Energy-delay estimation technique for high-performance microprocessor VLSI adders

Energy-delay estimation technique for high-performance micro...

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computer Arithmetic (ARIth)

作者： V.G. Oklobdzija B.R. Zeydel H. Dao S. Mathew Ram Krishnamurthy ACSEL University of California Davis CA USA Circuit Research Laboratories Intel Corporation Hillsboro OR USA

We motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating the energy-delay space of various high-performance VLSI adder topologies. Further, we show that our estimates accurately represent tradeoffs in the energy-delay space for high-performance 32-bit and 64-bit processor adders in 0.13/spl mu/m and 0.10/spl mu/m CMOS technologies, with an accuracy of 8% in delay estimates and 20% in energy estimates, compared with simulated data.

关键词： Microprocessors Very large scale integration Adders Space technology Circuit topology Delay estimation Digital arithmetic CMOS technology Logic Circuit simulation

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A performance study of monitoring and information services for distributed systems 03

A performance study of monitoring and information services f...

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International symposium on high performance Distributed computing

作者： Xuechai Zhang J.L. Freschl J.M. Schopf Department of Computer Science University of Chicago USA Department of Computer Science University of California Santa Cruz USA Mathematics and Computer Science Division Argonne National Laboratory USA

ISBN: (纸本)9780769519654

Monitoring and information services form a key component of a distributed system, or Grid. A quantitative study of such services can aid in understanding the performance limitations, advise in the deployment of the monitoring system, and help evaluate future development work. To this end, we study the performance of three monitoring and information services for distributed systems: the Globus Toolkit/spl reg/ Monitoring and Discovery Service (MDS2), the European Data Grid Relational Grid Monitoring architecture (R-GMA) and Hawkeye, part of the Condor project. We perform experiments to test their scalability with respect to number of users, number of resources and amount of data collected. Our study shows that each approach has different behaviors, often due to their different design goals. In the four sets of experiments we conducted to evaluate the performance of the service components under different circumstances, we found a strong advantage to caching or pre-fetching the data, as well as the need to have primary components at well-connected sites because of the high load seen by all systems.

关键词： computerized monitoring computer science Testing Scalability Relational databases computer architecture Mathematics Laboratories performance evaluation File systems

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