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Modeling a reconfigurable system for computing the FFT in place via rewriting-logic 03

Modeling a reconfigurable system for computing the FFT in pl...

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： M. Ayala-Rincon R.B. Nogueira C.H. Llanos R.P. Jacobi R.W. Hartenstein Departamentos de Matemática Universidade de Brasília Brazil Engenharia Mecânica Universidade de Brasília Brazil Ciência da Computação Universidade de Brasília Brazil Fachbereich Informatik Universität Kaiserslautern Germany

ISBN: (纸本)9780769520094

the growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of design alternatives at higher abstraction levels are needed. this paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the fast Fourier transform (FFT) using rewriting-logic. It is shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions.

关键词： Hardware Field programmable gate arrays Brazil Council Reconfigurable architectures Computational modeling Signal processing algorithms Application specific integrated circuits Costs computer architecture Circuit simulation

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high-performance left-to-right array multiplier design

High-performance left-to-right array multiplier design

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computer Arithmetic (ARIth)

作者： Z. Huang M.D. Ercegovac Computer Science Department University of California Los Angeles CA USA

We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed design shows equivalent performance as tree multipliers for n/spl les/32. An efficient radix-4 recoding logic generates the partial products in a left-to-right order. the partial products are split into upper and lower groups. Each group is reduced using [3:2] adders with optimized signal flows and the carry-save results from two groups are combined using a [4:2] adder. the final product is obtained with a prefix adder optimized to match the non-uniform arrival profile of the inputs. Layout experiments indicate that upper/lower split multipliers have slightly less area and power than optimized tree multipliers while keeping the same delay for n/spl les/32.

关键词： Delay Logic arrays computer science Classification tree analysis Wiring Capacitance Logic design Minimization methods Time division multiplexing Signal design

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Work distribution for parallel ZSweep algorithm

Work distribution for parallel ZSweep algorithm

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Brazilian symposium on computer Graphics and Image Processing (SIBGRAPI)

作者： R. Farias C. Bentes A. Coelho S. Guedes L. Goncalves National Laboratory for Scientific Computing LNCC Petropolis Rio de Janeiro Brazil Department of Systems Engineering State University of Rio de Janeiro Brazil Electronic Computing Center NCE Federal University of Rio de Janeiro Brazil Department of Computer Enginnering and Automation Federal University of Rio Grande do Norte Brazil

Distributed systems such as clusters of PCs are low-cost alternatives for running parallel rendering systems, but they have high communication overhead, and limited memory capacity on each processing node. We focus on the strategy for distributing the parallel rendering work among the PCs. A good distribution strategy provides better load balance, and avoids the need for replicating data on the relatively small memory of each PC. Our goal is to study different distribution strategies on the scope of the Parallel ZSweep algorithm, introducing in PZSweep another work distribution strategy: work stealing. this strategy allows a decentralized control of the work to be done, and provides a dynamic load redistribution. We propose two different algorithms to select the processor that will be "stolen" and show that the simplest one, nearest neighbor, was the most efficient. We also showed that the load redistribution schemes strongly depended on the initial load distribution, with an interleaved assignment, our systems could outperform the original parallel ZSweep algorithm. We conclude that for running large datasets on a cluster of PCs, parallel ZSweep requires dynamic load distribution strategy.

关键词： Personal communication networks Distribution strategy Clustering algorithms Costs Laboratories Scientific computing Systems engineering and theory Automation Distributed control Nearest neighbor searches

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Code and data transformations for improving shared cache performance on SMT processors

引用

5th International symposium on high performance computing, ISHPC 2003

作者： Nikolopoulos, Dimitrios S. Department of Computer Science The College of William and Mary McGlothlin–Street Hall WilliamsburgVA23187–8795 United States

ISBN: (纸本)3540203591

Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessive conflict misses. this paper proposes software solutions for dynamically partitioning the shared cache of an SMT processor, via the use of three methods originating in the optimizing compilers literature: dynamic tiling, copying and block data layouts. the paper presents an algorithm that combines these transformations and two runtime mechanisms to detect cache sharing between threads and react to it at runtime. the first mechanism uses minimal kernel extensions and the second mechanism uses information collected from the processor hardware counters. Our experimental results show that for regular, perfect loop nests, these transformations are very effective in coping with shared caches. When the caches are shared between threads from the same address space, performance is improved by 16–29% on average. Similar improvements are observed when the caches are shared between threads from different address spaces. To our knowledge, this is the first work to present an all-software approach for managing shared caches on SMT processors. It is also one of the first performance and program optimization studies conducted on a commercial SMT-based multiprocessor using Intel’s hyperthreading technology. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Program compilers

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Active learning: Applying RinSCut thresholding strategy to uncertainty sampling 16th

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16th Australian Conference on Artificial Intelligence, AI 2003

作者： Lee, Kang Hyuk Kay, Judy Kang, Byeong Ho School of Information Technologies University of Sydney NSW2006 Australia School of Computing University of Tasmania HobartTAS7001 Australia

ISBN: (纸本)9783540206460

In many supervised learning approaches to text classification, it is necessary to have a large volume of manually labeled documents to achieve a high level of performance. this manual labeling process is time-consuming, expensive, and will have some level of inconsistency. Two common approaches to reduce the amount of expensive labeled examples are: (1) selecting informative uncertain examples for humanlabeling, rather than relying on random sampling, and (2) using many inexpensive unlabeled data with a small number of manually labeled examples. Previous research has been focused on a single approach and has shown the considerable reduction on the amount of labeled examples to achieve a given level of performance. In this paper, we investigate a new framework to combine both approaches for similarity-based text classification. By applying our new thresholding strategy, RinSCut, to the conventional uncertainty sampling, we propose a new framework which automatically selects informative uncertain data that should be presented to human expert for labeling and positive-certain data that could be directly used for learning without human-labeling. Extensive experiments have been conducted on Reuters-21578 dataset to compare our proposed scheme with random sampling and conventional uncertainty sampling schemes, based on micro and macro-averaged F1. the results showed that if both macro and micro-averaged measures are concerned, the optimal choice might be our new approach. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Classification (of information)

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RZSweep: a new hardware-assisted volume-rendering technique for regular datasets

RZSweep: a new hardware-assisted volume-rendering technique ...

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Brazilian symposium on computer Graphics and Image Processing (SIBGRAPI)

作者： Gautam Chaudhary Lakshmy Ramaswamy R. Farias University of California Irvine CA USA National Laboratory for Scientific Computing Petropolis Rio de Janeiro Brazil

A long-standing challenge in the field of volume rendering is to obtain high quality images in near real-time. this is particularly important for scientific datasets where highly precise results are required to ensure accurate data interpretation. We present RZSweep as a new hardware-assisted technique for volume rendering of regular datasets based on the plane-sweep paradigm. Although some research has been done in the past for irregular datasets, we present the first attempt to explore the capabilities of the plane sweep paradigm for regular datasets. RZSweep is an exact, object order, direct volume rendering (DVR), back-to-front projection algorithm wherein a plane sweeps through the volume in depth order, projecting all the data elements within the user specified threshold onto the image plane. the algorithm uses a hardware rendering pipeline to composite the final image. the space complexity of the algorithm is bound to the number of vertices in the largest diagonal plane of the dataset. A prototype of the algorithm renders a dataset of size 256/sup 3/ in near real-time of 0.77 seconds on a single off-the-shelf commodity hardware PC. Every data element within the specified threshold contributes to the final image in its correct spatial order that is guaranteed by the use of a heap.

关键词： Rendering (computer graphics) Transfer functions Hardware Data visualization Magnetic resonance imaging Computed tomography Positron emission tomography Lattices Laboratories Scientific computing

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A performance evaluation of memory hierarchy in embedded systems

A performance evaluation of memory hierarchy in embedded sys...

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Southeastern symposium on System theory

作者： A. Milenkovic M. Milenkovic N. Barnes Electrical and Computer Engineering Department University of Alabama Huntsville USA

the increasing speed gap between processors and memory makes the design of memory hierarchy one of the critical issues in general purpose embedded systems. As memory requirements for embedded applications grow, especially in emerging area of handheld multimedia devices, cache memories become crucial for providing high performance and reducing power. this paper describes a performance evaluation of typical cache design issues such as cache size and organization, block size, and replacement policy. the evaluation is done using simulation tools for architectural exploration based on ARM instruction set and MiBench benchmark suite. Our performance evaluation includes monitoring of dynamic cache behavior, since embedded systems designers are interested not only in the total number of cache misses, but also in the number of cache misses throughout application execution.

关键词： Embedded system Cache memory Clocks Embedded computing Design engineering Monitoring performance gain computer industry computer architecture Costs

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Novel design methodology for high-performance XOR-XNOR circuit design 03

Novel design methodology for high-performance XOR-XNOR circu...

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symposium on Integrated Circuits and Systems Design (SBCCI)

作者： S. Goel M.A. Elgamel M.A. Bayoumi Center for Advanced Computer Studies University of Louisiana Lafayette USA

ISBN: (纸本)9780769520094

As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are some of the characteristics for DSM circuits. A novel design methodology for the design of energy-efficient noise-tolerant XOR-XNOR circuits that can operate at low voltages is proposed. the proposed circuits are characterized and compared with previously published circuits for reliability and energy efficiency. To test their driving capability, the proposed gates are implanted in an existing 5-2 compressor design and are shown to provide superior performance. the average noise threshold energy is used for quantifying the noise immunity. Simulation results show that the proposed circuits are more noise-immune and displays better power consumption results as well as power-delay product characteristics. Also, the circuits prove to be faster and successfully work at all ranges of supply voltage starting from 0.6 V to 3.3 V.

关键词： Design methodology Circuit synthesis Circuit noise Low voltage Energy efficiency Frequency Circuit testing Circuit simulation Displays Energy consumption

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Error-injection-based failure characterization of the IEEE 1394 bus

Error-injection-based failure characterization of the IEEE 1...

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IEEE symposium on On-Line Testing (IOLTS)

作者： D.J. Beauregard Z. Kalbarczyk Rk. Iyer S. Chau L. Alkalai Coordinated Science Laboratory Center for Reliable and High-Performance Computing University of Illinois Urbana-Champaign USA Jet Propulsion Laboratory NASA USA

this paper investigates the behavior of the IEEE 1394 bus in the presence of transient errors in the hardware layers of the protocol. Software-implemented error injection is used to introduce errors into the internals of the 1394 bus hardware chipset. Results from this study indicate that the IEEE 1394 bus protocol provides robust network communication in the presence of single-bit errors in the chipset.

关键词： Hardware Physical layer Robustness computer errors computer network reliability Telecommunication network reliability Bandwidth computer architecture Access protocols Registers

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A configurable network protocol for cluster based communications using modular hardware primitives on an intelligent NIC

A configurable network protocol for cluster based communicat...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： R.G. Jaganathan K.D. Underwood R. Sass Parallel Architecture Research Lab ECE Department Clemson University Clemson SC USA Sandia National Laboratories Albuquerque NM USA

the high overhead of generic protocols like TCP/IP provides strong motivation for the development of a better protocol architecture for cluster-based parallel computers. Reconfigurable computing has a unique opportunity to contribute hardware level protocol acceleration while retaining the flexibility to adapt to changing needs. thus, it is possible to provide application-specific protocol processing to improve performance and to reduce space utilization. Reducing space utilization permits the use of a greater portion of the FPGA for other application-specific processing. this paper focuses on work to create a set of components that can be put together as needed to obtain a customized protocol for each application. the components are parameterizable, increasing the protocol's flexibility. To study the feasibility of such an architecture, hardware components for the reconfigurable logic on the NIC were built such that they can be stitched together as required to provide the required functionality. Feasibility is demonstrated using four different protocol configurations in this paper. the different configurations illustrate trade-offs between chip space and functionality.

关键词： Protocols Hardware Intelligent networks computer architecture Delay Switches Table lookup Parallel architectures Laboratories Electronic mail

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