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检索条件"任意字段=16th Symposium on Computer Architecture and High Performance Computing"

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Improving the communication network of a cluster of PC's to solve implicit CFD problems 14

Improving the communication network of a cluster of PC's to ...

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14th symposium on computer architecture and high performance computing

作者： Silva, RS Rivello, MFP Amorim, R Computer Science Dept. Laboratório Nacional de Computação Científica Brazil Computer Science Dept. Universidade Católica de Petrópolis Brazil

ISBN: (纸本)0769517722

In this work we investigate the feasibility of using a cluster of PC's built with mass market networks to deal with the necessities of the CFD community, in special for unstructured implicit CFD solvers that require very irregular pattern of communications. this paper reports the initial findings from a series of experiments with some well known benchmarks to determine CFD applications sensitivity to machine communication parameters. this is done by running these benchmarks on a cluster in which the communication network has been modified to allow an increase of the bandwidth by adding multiple channels and a reduction on the latency by using a lightweight protocol like the MV, a.

关键词： Bandwidth Bonding Communication networks Computational fluid dynamics computer networks computer science Delay Ethernet networks high performance computing Protocols

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Bulk synchronous parallel computing using a high bandwidth optical interconnect 16

Bulk synchronous parallel computing using a high bandwidth o...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Gourlay, I. Dew, P.M. Djemame, K. School of Computing University of Leeds LeedsLS2 9JT United Kingdom

ISBN: (纸本)0769515738

the list of applications requiring high performance computing resources is constantly growing. the cost of inter-processor communication is critical in determining the performance of massively parallel computing systems for many of these applications. this paper considers the feasibility of a commodity processor-based system which uses a free-space optical interconnect. A novel architecture, based on this technology, is presented. Analytical and simulation results based on an implementation of BSP (Bulk Synchronous Parallelism) are presented, indicating that a significant performance enhancement, over architectures using conventional interconnect technology, is possible. © 2002 IEEE.

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Simulating L3 caches in real time using hardware accelerated cache simulation (HACS): A case study with SPECint 2000 14

Simulating L3 caches in real time using hardware accelerated...

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14th symposium on computer architecture and high performance computing

作者： Watson, M Flanagan, JK Brigham Young Univ Dept Comp Sci Performance Evaluat Lab Provo UT 84602 USA

ISBN: (纸本)0769517722

Trace-driven simulation is a commonly used tool to evaluate memory-hierarchy designs. Unfortunately, trace collection is very expensive, and storage requirements for traces are very large. In this paper, we introduce HACS (Hardware Accelerated Cache Simulator), and describe the validation methods we used to demonstrate functionality. We also present some initial cache simulation results from SPECint 2000. We then propose future directions for research with HACS.

关键词： Acceleration Buffer storage Computational modeling computer aided software engineering computer science computer simulation Field programmable gate arrays Hardware Laboratories Probes

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Architectural extensions to support effcient communication using message prediction 16

Architectural extensions to support effcient communication u...

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16th Annual International symposium on high performance computing Systems and Applications, HPCS 2002

作者： Afsahi, Ahmad Dimopoulos, Nikitas J. Department of Electrical and Computer Engineering Queen's University KingstonK7L 3N6 Canada Department of Electrical and Computer Engineering University of Victoria and Computer Engineering Laboratory ITS Delft University of Technology Netherlands

ISBN: (纸本)0769516262

With increasing uniprocessor and SMP computation power, workstation clusters are becoming viable alternatives to high performance computing systems. Communication overhead affects the performance of parallel computers significantly. A significant portion of the software communication overhead is attributable to message copying. We argue that it is possible to address the message copying problem at the receiving side through speculation. We show that messages display a form of locality, and we introduce the notion of message prediction for the receiving side of message-passing systems. By predicting a receive communication call before it is posted, we are able to place the required message directly into the cache speculatively before it is needed so that effectively a zero-copy communication can be achieved Specific extensions to the ISA and the processor architecture accommodate late binding without requiring copying of the message. © 2002 IEEE.

关键词： Forecasting

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Exploiting loop-level parallelism with the shift architecture 14

Exploiting loop-level parallelism with the shift architectur...

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14th symposium on computer architecture and high performance computing

作者： Lima, CD Nakamura, T Tohoku Univ Grad Sch Informat Sci Comp Architecture Lab Sendai Miyagi 9808579 Japan

ISBN: (纸本)0769517722

the limited amount of instruction-level parallelism inherent in applications is a limiting factor for improving the performance of most conventional microprocessors. A promising solution to overcome this problem is to exploit coarser granularities of parallelism. In this paper we propose exploiting loop-level parallelism in a multithreaded fashion. We use the Shift architecture [9] as a baseline architecture, with improved compiler support and registerfile. the compiler converts iterations of a loop into threads, to be executed by multiple processing elements. the hardware provides a selective register shifting mechanism in order to allow the execution of loops containing loop-carried data dependences, which are very difficult to execute by using conventional architectures. In this paper we simulate and discuss the parameters of major importance for the implementation of this architectural approach. Our initial results show that, on two simple numerical benchmarks, a considerable amount of iteration overlapping can be potentially achieved by an implementation of the Shift architecture, in comparison with a multiprocessor machine.

关键词： Application software computer architecture Continuous improvement Delay Hardware Laboratories Microprocessors Parallel processing Proposals Yarn

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A metascheduler for the Grid 11

A metascheduler for the Grid

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Vadhiyar, SS Dongarra, JJ Univ Tennessee Comp Sci Dept Knoxville TN 37996 USA

ISBN: (纸本)0769516866

With the advent of Grid computing, scheduling strategies for distributed heterogeneous systems have either become irrelevant or have to be extended significantly to support Grid dynamics. In this paper, we describe a metascheduling architecture for a Grid system that takes into account both the application and system level considerations. Results are presented to demonstrate the usefulness of the metascheduler.

关键词： computer architecture computer science Contracts Distributed computing Dynamic scheduling Grid computing Libraries Lifting equipment Mars Processor scheduling

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T&D-Bench: an environment for modeling and simulating complex processor architectures 14

T&D-Bench: an environment for modeling and simulating comple...

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14th symposium on computer architecture and high performance computing

作者： Becker, DM Otero, JC Wagner, FR Univ Fed Rio Grande Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)0769517722

this paper presents T&D-Bench, an integrated suite Of tools for modeling and simulating state-of-the-art processors, which is composed of two main parts. SimPL is an object-oriented methodology for modeling the behavior of an instruction set, with precise information on the timing of basic instruction steps. the methodology is general and allows easy modeling of various architecture hypes. the second part of the suite is CSPSim, an open set of visualization tools that communicate with any number of SimPL models based on a client-server architecture. T&D-Bench gathers the main advantages of teaching environments, with a rich user interface, and design environments, with resources for modeling any complex processor architectures.

关键词： Computational modeling computer architecture Education Embedded system Object oriented modeling Pipelines Process design Timing User interfaces Visualization

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Hybrid system, a new low cost parallel cluster 16

Hybrid system, a new low cost parallel cluster

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16th Annual International symposium on high performance computing Systems and Applications, HPCS 2002

作者： Sim, Leo Chin Schroder, Heiko Leedham, Graham Sch. of Computer Engineering NTU Singapore Singapore Sch of Computer Sc. and IT RMIT Melbourne Australia

ISBN: (纸本)0769516262

this paper describes a new parallel architectural system which we called Hybrid System. As the name implies, Hybrid System is a combination of both SIMD and MIMD systems working concurrently. this new parallel architecture has the capability of achieving speed-up rates more than MIMD can achieve alone and can also be more flexible than multiple SIMD on a single station. In this paper, we introduce our new SIMD concept and also show the contribution of the SIMD on the Hybrid System. We also developed a general formula for determining the speedup of the Hybrid System so that accurate predictions can be made on its performance. this, we establish by comparing the measured speedup with the computed speedup for a volume rendering application. © 2002 IEEE.

关键词： Hybrid systems

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Instruction usage and the memory gap problem 14

Instruction usage and the memory gap problem

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14th symposium on computer architecture and high performance computing

作者： Fernandes, EST Barbosa, VC Ramos, F Univ Fed Rio de Janeiro COPPE Programa Engn Sistemas & Comp BR-21941 Rio De Janeiro Brazil

ISBN: (纸本)0769517722

the gap between memory and processor speeds is responsible for the substantial amount of idle time of current processors. To reduce the impact provoked by the so-called " memory gap problem," many software techniques (e.g., the code layout reorganization) together with hardware mechanisms (cache memory, translation look-aside buffer, branch prediction, speculative execution, trace cache, instruction reuse, and so on) have been successfully implemented. In this paper we present some experiments that explain why these mechanisms and techniques are so efficient. We found that only a small fraction of the object code is actually executed: our experiments disclosed that more than 50% of the instructions remain untouched during the whole execution, and the percentages of basic blocks which remain unused are slightly greater In addition to the usage of instructions and blocks, the paper provides further insights regarding the behavior of application programs, and gives some suggestions for extra performance gains.

关键词： Cache memory computer aided instruction computer architecture Delay Hardware performance gain performance loss Prefetching Random access memory Software performance

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Local discovery of system architecture - Application parameter sensitivity: An empirical technique for adaptive grid applications 11

Local discovery of system architecture - Application paramet...

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Corey, IR Johnson, JR Vetter, JS Lawrence Livermore Natl Lab Comp Applicat & Res Dept Livermore CA USA

ISBN: (纸本)0769516866

this study presents a technique that can significantly improve the performance of a distributed application by allowing the application to locally adapt to architectural characteristics of distinct resources in a distributed system. Application performance is sensitive to system architecture-application parameter pairings. In a distributed or Grid enabled application, a single parameter configuration for the whole application will not always be optimal for every participating resource. In particular, some configurations can significantly degrade performance. Furthermore, the behavior of a system may change during the course of the run. the technique described here provides an automated mechanism for run-time adaptation of application parameters to the local system architecture. Using a scaled-down simulation of a Monte Carlo physics code, we demonstrate that this technique can conservatively achieve speedups up to 65% on individual resources and may even provide order of magnitude speedup in the extreme case.

关键词： Application software computer applications computer architecture Degradation Distributed computing Laboratories Monte Carlo methods performance evaluation Processor scheduling Runtime

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