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检索条件"任意字段=16th Symposium on Computer Architecture and High Performance Computing"

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architecture requirements for commercializing Grid resources

Architecture requirements for commercializing Grid resources

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Kenyon, C Cheliotis, G IBM Corp Zurich Res Lab CH-8803 Ruschlikon Switzerland

ISBN: (纸本)0769516866

Contemporary computing systems, especially large-scale systems such as Grids promise ultra-fast ubiquitous utility computing, always available at the flip of a switch. A major unresolved issue is the organization and efficient usage of such infrastructure in a commercial context where several entities compete for shared resources. this has long been resolved for conventional utility resources such as gas and electricity through commoditization, a variety of market designs, customization, and decision support for the resulting portfolios of assets and commitments. this paper reviews the state of Grid commercialization and compares it to the commercialization of conventional resources. We draw specific lessons for commercialized Grids and detail them as architecture requirements at each level of the architecture stack. We provide an example to illustrate the benefits of commercialized resources in terms of the financial clarity it brings to decisions for different user groups, namely application users and IT managers.

关键词： computer architecture

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A distributed simulation management engine for ordinary differential equations

A distributed simulation management engine for ordinary diff...

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6th International symposium on Parallel architectures, Algorithms and Networks (I-SPAN 02)

作者： See, S Sun Microsystems Inc. Nanyang Technological University Singapore

ISBN: (纸本)0769515797

the Internet is quickly evolving into a global computing platform. Internetworking of computers means that computing resources available for personal use need not be confined to the users' local environment. Instead, the Internet provides a delivery channel where remote computing resources are easily accessible. computer simulations often require high performance computers (HPC) for fast number crunching. However, HPCs remain inaccessible to ordinary users due to the high cost involved. the aim of this project is to develop a web-based simulation architecture where users can input a simulation model, based on the European Space Agency Simulation Language (ESL), through a Java graphical front-end application, and letting backend HPCs to perform intensive computation on behalf of the user. We have successfully implemented this system within an Intranet environment, with the possibility of actual implementation on the World Wide Web. In this report, we will discuss the architectural merits of this framework, our design philosophy and proposals for improvements and future development.

关键词： Computational modeling computer architecture computer simulation Costs high performance computing Internet Internetworking Java Search engines Web sites

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Fine-grain priority scheduling on multi-channel memory systems 8

引用

8th International symposium on high-performance computer architecture

作者： Zhu, ZC Zhang, Z Zhang, XX Coll William & Mary Dept Comp Sci Williamsburg VA 23185 USA

ISBN: (纸本)0769515258

Configurations of contemporary DRAM memory systems become increasingly complex. A recent study [5] shows that application performance is highly sensitive to choices of configurations, and suggests that tuning burst sizes and channel configurations be an effective way to optimize the DRAM performance for a given memory-intensive workload. However, this approach is workload dependent. In this study we show that, by utilizing fine-grain priority access scheduling, we are able to find a workload independent configuration that achieves optimal performance on a multi-channel memory system. Our approach can well utilize the available high concurrency and high bandwidth on such memory systems, and effectively reduce the memory stall time of memory-intensive applications. Conducting execution-driven simulation of a 4-way issue, 2 GHz processor, we show that the average performance improvement for fifteen memory-intensive SPEC2000 programs by using an optimized fine-grain priority scheduling is about 13115 and 8116 for a 2-channel and a 4-channel Direct Rambus DRAM memory systems, respectively, compared with gang scheduling. Compared with burst scheduling, the average performance improvement is 16116 and 14% for the 2-channel and 4-channel memory systems, respectively.

关键词： Application software Bandwidth computer science Concurrent computing Delay Educational institutions Processor scheduling Random access memory Resumes System performance

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high-performance parallel and distributed computing for the BMI eigenvalue problem 16

High-performance parallel and distributed computing for the ...

引用

16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Aida, K. Futakata, Y. Hara, Shinji Tokyo Institute of Technology PRESTO JST Japan IBM Japan Japan Tokyo Institute of Technology University of Tokyo Japan

ISBN: (纸本)0769515738

the BMI Eigenvalue Problem is one of optimization problems and is to minimize the greatest eigenvalue or a bilinear matrix function. this paper proposes a parallel algorithm to compute the ϵ-optimal solution of the BMI Eigenvalue Problem on parallel and distributed computing systems. the proposed algorithm performs a parallel branch and bound method to compute the e-optimal solution using the Master-Worker paradigm. the performance evaluation results on PC clusters and a Grid computing system showed that the proposed algorithm reduced computation time of the BMI Eigenvalue problem to 1/91 of the sequential computation time on. a PC cluster with 128CPUs and reduced that to 1/7 on a Grid computing system. the results also showed that tuning of the computational granularity on a worker was required to achieve the best performance on a Grid computing system. © 2002 IEEE.

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Using kernel couplings to predict parallel application performance 11

Using kernel couplings to predict parallel application perfo...

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Taylor, V Wu, XF Geisler, J Stevens, R Northwestern Univ Dept Elect & Comp Engn Evanston IL 60208 USA

ISBN: (纸本)0769516866

performance models provide significant insight into the performance relationships between an application and the system used for execution. the major obstacle to developing performance models is the lack of knowledge about the performance relationships between the different functions that compose an application. this paper addresses the issue by using a coupling parameter, which quantifies the interaction between kernels, to develop performance predictions. the results, using three NAS Parallel Application Benchmarks, indicate that the predictions using the coupling parameter were greatly improved over a traditional technique of summing the execution times of the individual kernels in an application. In one case the coupling predictor had less than 1% relative error in contrast the summation methodology that had over 20% relative error. Further, as the problem size and number of processors scale, the coupling values go through a finite number of major value changes that is dependent on the memory subsystem of the processor architecture.

关键词： Algebra Analytical models Application software computer science Kernel Laboratories Mathematical model Mathematics performance analysis Predictive models

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thread-spawning schemes for speculative multithreading 8

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8th International symposium on high-performance computer architecture

作者： Marcuello, P González, A Univ Politecn Cataluna Dept Arquitectura Computadors ES-08034 Barcelona Spain

ISBN: (纸本)0769515258

Speculative multithreading has been recently proposed to boost performance by means of exploiting thread-level parallelism in applications difficult to parallelize. the performance of these processors heavily depends on the partitioning policy used to split the program into threads. Previous work uses heuristics to spawn speculative threads based on easily-detectable program constructs such as loops or subroutines. In this work we propose a profile-based mechanism to divide programs into threads by searching for those parts of the code that have certain features that could benefit from potential thread-level parallelism. Our profile-based spawning scheme is evaluated oil a Clustered Speculative Multithreaded Processor and results show large performance benefits. When the proposed spawning scheme is compared with traditional heuristics, we outperform them by almost 20%. When a realistic value predictor and a 8-cycle thread initialization penalty is considered, the performance difference between them is maintained. the speed-lip over a single thread execution is higher than 5x for a 16-thread-unit processor and close to 2x for a 4-thread-unit processor.

关键词： Algorithms computer architecture Hardware Microarchitecture Multithreading Parallel processing performance analysis Program processors Proposals Yarn

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Bit-matrix decomposition and dynamic reconfiguration: A unified arithmetic processor architecture, d 16

Bit-matrix decomposition and dynamic reconfiguration: A unif...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Lin, Rong Department of Computer Science SUNY- Geneseo GeneseoNY14454 United States

ISBN: (纸本)0769515738

this paper presents the architecture, design and test of a unified arithmetic processor, developed based on recently proposed partial product bit-matrix decomposition and dynamic reconfiguration parallel processing mechanism. By trading bitwidth for array size, the processor is able to perform several operations involving the multiplication of two 32-b numbers and two 4x4 matrices of 8-b numbers, as well as the evaluation of the inner product of two size-4 arrays of 16-b numbers. All of them are important to many applications including graphics and volume rendering. A set of very simple and efficient reconfigurable switches is utilized to achieve the high performance. Only two extra bits are needed for all reconfiguration controls. the architecture also possesses a superiority for high quality test. the circuit simulations with a 2.5V, 0.25μ process have shown that the processor performance including delay and VLSI area is comparable with the existing single-function counterparts. © 2002 IEEE.

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high level synthesis for programmable devices: the HADES project 16

High level synthesis for programmable devices: The HADES pro...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： A., Marongiu P., Palazzari V., Rosato CASPUR Rome Italy ENEA HPCN Project Rome Italy Unità di Ricerca Roma I Italy

ISBN: (纸本)0769515738

FPGAs allow the implementation of very complex designs (∼1million of gates);they are good candidates to host special purpose systems designed to boost conventional computing architectures. Several computationally intensive algorithms are poorly supported by standard computing architectures, so the design of dedicated devices implementing the intensive parts of such algorithms could significantly speedup the overall performances. (Re-)programmability, allowing the reusing of the same chip for different applications and avoiding the costly and cumbersome design of ASIC systems, is a key issue for the design of specialized computing architectures. Further crucial factors for the success of FPGA based coprocessors are both the possibility of achieving significantly larger performances than those attainable with conventional processors and the ability to produce a working prototype in very short times. this work presents the results achieved in the HADES (HArdware DEsign in Scientific applications) project, aimed at automatically extracting parallelism from affine iterative algorithms and at generating the synthesizable VHDL which describes the parallelized version of the algorithm. In the paper, along with the global HADES design flow, we present two cases, from the signal processing and the proteomic domains, in which FPGA based designs allowed to significantly increase the overall system performances. thanks to the nearly global automation of all the steps of the design flow, in both cases, a working prototype has been realized in one working week. © 2002 IEEE.

关键词： high level synthesis Field programmable gate arrays Signal processing algorithms computer architecture Algorithm design and analysis Hardware Prototypes Coprocessors Parallel processing Iterative algorithms

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Flexibility, manageability, and performance in a Grid storage appliance

Flexibility, manageability, and performance in a Grid storag...

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11th IEEE International symposium on high performance Distributed computing (HPDC-11)

作者： Bent, J Venkataramani, V LeRoy, N Roy, A Stanley, J Arpaci-Dusseau, AC Arpaci-Dusseau, RH Livny, M Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

ISBN: (纸本)0769516866

We present NeST. a flexible software-only storage appliance designed to-meet the storage needs of the Grid. NeST has three key features that make it well-suited for deployment in a Grid environment. First, NeST provides a generic data transfer architecture that supports multiple data transfer-protocols (including GridFTP and NFS), and allows for the easy addition of new protocols. Second, NeST is dynamic, adapting itself on-the-fly so that it runs effectively on amide range of hardware and software platforms. third, NeST is Grid-aware, implying that features that are necessary for integration into the Grid, such as storage space guarantees, mechanisms for resource and data discovery, user authentication, and quality of service, are a part of the NeST infrastructure.

关键词： computer architecture

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Massively parallel solutions for molecular sequence analysis 16

Massively parallel solutions for molecular sequence analysis

引用

16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Schmidt, B. Schröder, H. Schimmler, M. Nanyang Technological University School of Computer Engineering Singapore639798 Singapore Technische Universität Braunschweig Institut für Datentechnik und Kommunikationsnetze Hans-Sommer-Str. 66 Braunschweig38106 Germany

ISBN: (纸本)0769515738

In this paper we present new approaches to high performance protein database scanning on two novel massively parallel architectures to gain supercomputer power at low cost. the first architecture is built around a Beowulf PC-cluster linked by a high-speed network and fine-grained parallel Systola 1024 processor boards connected to each node. the second architecture is the Fuzion 150, a new parallel computer with a linear SIMD array of 1536 processing elements on a single chip. We present the design of a database scanning application based on the Smith-Waterman algorithm in order to derive efficient mappings onto these architectures. the implementations lead to significant runtime savings for large-scale database scanning. this result shows that both architectures provide high-throughput sequence similarity analysis solutions at a good price/performance ratio. © 2002 IEEE.

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