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检索条件"任意字段=16th Symposium on Computer Architecture and High Performance Computing"

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the viator approach: About four principles of autopoietic growth on the way to future hyperactive ne 16

The viator approach: About four principles of autopoietic gr...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Simeonov, P.L. Technology University of Ilmenau Faculty for Informatics and Automation Germany

ISBN: (纸本)0769515738

Viator, the Wandering Network approach, defines a new type of communications architecture chracterized by: • flexible, multi-modal specialization of network nodes as virtual subnetworks;• mobility and virtualization of the net functions in hardware und software;• self-organizing multi-feedback topology-on-demand. Network elemens can contain several exchangeable modules capable of executing diverse network functions in parallel. they can be invoked, transported to or generated in the nodes upon delivery of mobile code about the node's behaviour. © 2002 IEEE.

关键词： active networks adaptive systems autopoiesis mobility multimedia architecture reconfigurable computing

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On the dynamic allocation of mobile agents by on-line task scheduling 16

On the dynamic allocation of mobile agents by on-line task s...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Yang, Xinfeng Ma, Weimin You, J. Liu, J. Department of Computing HK Polytechnic University Kowloon Hong Kong School of Computing and Information Technology Griffith University QLD4111 Australia

ISBN: (纸本)0769515738

this paper presents a new approach to the dynamic allocation of mobile agents by on-line task scheduling for high performance in Internet computing. In contrast to the existing approaches, which apply predefined task scheduling schemes to allocate computing resources, we introduce a new on-line competitive algorithm to achieve flexibility. A guided allocation scheme based on the system competitive ratio is developed to optimize the allocation of mobile agents. the proposed system combines push-based technology with an innovative on-line task-scheduling scheme to speed up system response time and minimize system overheads. the system analysis and simulation demonstrate the feasibility and effectiveness of our approach to mobile agent-based Internet computing. © 2002 IEEE.

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CableS: thread control and memory management extensions for shared virtual memory clusters 8

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8th International symposium on high-performance computer architecture

作者： Jamieson, P Bilas, A Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)0769515258

Clusters of high-end workstations and PCs are currently used in many application domains to perform large-scale computations or as scalable servers for I/O bound tasks. Although clusters have many advantages, their applicability in emerging areas of applications has been limited. One of the main reasons for this is the fact that clusters do not provide a single system image and thus are hard to program. In this work we address this problem by providing a single cluster image with respect to thread and memory, management. We implement our system, CableS (Cluster enabled threads), on a 32-processor cluster interconnected with a low-latency, high-bandwidth system area network and conduct an early, exploration of the costs involved in providing the extra functionality. We demonstrate the versatility of CableS with a wide range of applications and show that clusters can be used to support applications that have been written for more expensive tightly-coupled systems, with very little effort on the programmer side: (a) We run legacy pthreads applications without any major modifications. (b) We use a public domain OpenMP compiler (OdinMP [8]) to translate OpenMP programs to pthreads and execute them on our system, with no or few modifications to the translated pthreads source code. (c) We provide an implementation of the M4 macros for our pthreads system and run the SPLASH-2 applications. We also show that the overhead introduced by the extra functionality, of CableS affects the parallel section of applications that have been tuned for the shared memory abstraction only in cases where the data placement is affected by operating system (WindowsNT) limitations in virtual memory mappings granularity.

关键词： Cables Cost function high performance computing Large-scale systems Memory management Personal communication networks Program processors Programming profession Workstations Yarn

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Parallel processing computer architectures for process control 34

Parallel processing computer architectures for process contr...

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34th Southeastern symposium on System theory

作者： Venkatesan, G Abachi, H Monash Univ Dept Elect & Comp Syst Engn Melbourne Vic 3168 Australia

ISBN: (纸本)0780373391

Modern, large-scale, high-speed process control automation is quite complex in nature. Continuous manufacturing processes currently in use require advanced computer technologies such as simultaneous parallel processing architecture for synchronous process operations that take place independent of each other. computer control of some processes involves a single super-computer that is responsible for all the inter-connected process operations. Or alternatively, plants can also be connected to each other within a huge plant area through single independent (stand-alone) computers that are responsible for each plant/process operation and connected to a local area network (LAN). the outputs of a process/plant may be an input to a neighbouring process/plant, for example, the refining of petroleum crude in which an output of a stage say, naphtha catalytic cracker is possibly an input to the next stage in a petroleum refinery. In processing high value output products, even a small but significant reduction in output variance can result in huge cost savings and improve system performance. In order to optimise the performance of a process control system measured through its output variance, suitably structured robust computing structures are necessary and also for multi-input/output process control. this paper describes (i) a Multi-ported-Memory, Star-Ring Parallel Processing computer architecture for process control of multiple inputs/outputs and (ii) a suitable parallel processing architecture for optimising the performance of an interconnected process control system. Both the architectures use a feedback control algorithm for multi-input/output process control by measuring its performance through its output product quality and for optimising the performance of the inter-connected process control system by using again the product quality output as a performance measure.

关键词： multi-input/multi-output and multi-plant/multi-processes regulator SISO parallel processing

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Protocols for fault-tolerant distributed-shared-memory on the SOME-bus multiprocessor architecture 16

Protocols for fault-tolerant distributed-shared-memory on th...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Hecht, D. Katsinis, C. Electrical and Computer Engineering Drexel University PhiladelphiaPA19104 United States

ISBN: (纸本)0769515738

the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network that directly links arbitrary pairs of processor nodes without contention, and can efficiently interconnect over one hundred nodes. Each node has a dedicated output channel and an array of receivers, with one receiver dedicated to every other node's output channel. the SOME-Bus eliminates the need for global arbitration and provides bandwidth that scales directly with the number of nodes in the system. Under the Distributed Shared Memory (DSM) paradigm, the SOME-bus allows strong integration of the transmitter, receiver and cache controller hardware to produce a highly integrated system-wide cache coherence mechanism. Backward Error Recovery fault-tolerance techniques can rely on DSM data replication and SOME-Bus broadcasts with little additional network traffic and corresponding performance degradation. this paper presents three protocols for fault-tolerant DSM and uses simulation to examine the performance of the protocols on the SOME-Bus multiprocessor architecture. © 2002 IEEE.

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MetaGrid: a scalable framework for wide-area service deployment and management

MetaGrid: a scalable framework for wide-area service deploym...

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IEEE International symposium on high performance computing Systems and Applications (HPCS)

作者： M. Maheswaran B. Maniymaran P. Card F. Azzedin TR Laboratories Winnipeg University of Manitoba Winnipeg Canada

Presents an architecture called the MetaGrid based on Grid computing concepts for resource provisioning for wide-area network-enabled applications. Resource provisioning for wide-area applications can involve coordinated allocation of computing and communication resources. A Grid computing system provides a virtual framework that facilitates controlled resource sharing among different institutions. the MetaGrid extends the Grid computing systems in two major ways: (a) introduces a notion of SubGrid that provides a coarse-grained resource allocation class and (b) introduces a framework for interconnecting Grids by facilitating peering, trading, and brokering among the different Grids. the paper presents (a) the overall architecture of the MetaGrid with a description of the different functional components, (b) the resource allocation model that is introduced by the notion of SubGrids, and (c) strategies of interconnecting Grids.

关键词： Resource management Grid computing computer architecture Internet Electronic mail Communication system control Control systems Quality of service computer network management Web sites

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Variable partitioning and scheduling of multiple memory architectures for DSP 16

Variable partitioning and scheduling of multiple memory arch...

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16th International Parallel and Distributed Processing symposium, IPDPS 2002

作者： Zhuge, Q. Xiao, B. Sha, E.H.-M. University of Texas at Dallas Department of Computer Science RichardsonTX75083 United States

ISBN: (纸本)0769515738

Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture are variable partitioning and scheduling. However, there's little research work that has been done on these problems. In this paper, we present a new graph model for tackling the variable partitioning problem, namely, Variable Independence Graph (VIG), which provides more precise information for variable partitioning compared to the previous graph models. We also present a scheduling algorithm that takes advantages of multiple memory modules, Rotation Scheduling with Variable Re-partition (RSVR). It's a new scheduling technique based on retiming and software pipelining. It may re-partition the variables if necessary during the scheduling process. the experiment results show that the average improvement on schedule length by using the algorithm is 44.8%. Another major contribution of this paper is that we invent an algorithm for design space exploration on multiple memory architecture. It produces more feasible solutions on a set of schedule length requirement. And our solution have less functional units that Interference Graph model. © 2002 IEEE.

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Bulk synchronous parallel computing using a high bandwidth optical interconnect

Bulk synchronous parallel computing using a high bandwidth o...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： I. Gourlay P.M. Dew K. Djemame School of Computing University of Leeds Leeds UK

the list of applications requiring high performance computing resources is constantly growing. the cost of inter-processor communication is critical in determining the performance of massively parallel computing systems for many of these applications. this paper considers the feasibility of a commodity processor-based system which uses a free-space optical interconnect. A novel architecture, based on this technology, is presented. Analytical and simulation results based on an implementation of BSP (Bulk Synchronous Parallelism) are presented, indicating that a significant performance enhancement, over architectures using conventional interconnect technology, is possible.

关键词： Parallel processing Bandwidth Optical interconnections Costs computer architecture Smart pixels Space technology Concurrent computing Optical computing Personal communication networks

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Fast processing of medical images using a new parallel architecture, the hybrid system 5

Fast processing of medical images using a new parallel archi...

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5th IEEE Southwest symposium on Image Analysis and Interpretation

作者： Leo, CS Schroder, H Nanyang Technol Univ Ctr High Performance Embedded Syst Singapore 2263 Singapore

ISBN: (纸本)0769515371

this paper describes an implementation of Volume Rendering on a new parallel architectural system, the Hybrid System. the Hybrid System is a combination of SIMD system with an MIMD system. For such an architecture, we have developed a new Volume Rendering algorithm called Slice Orientation. Using this new parallel architecture on the visualization algorithm, we have achieved speed-up rates more than its corresponding MIMD can achieve alone. In this paper, we also present a general formula for determining the Speedup of the Hybrid System so that accurate predictions can be made on the performance of the Hybrid System.

关键词： Biomedical image processing Biomedical imaging Casting Concurrent computing Data visualization Electronic mail Embedded system Magnetic resonance imaging Parallel architectures Rendering (computer graphics)

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Life with Ed: A case study of a linux BIOS/BProc cluster 16

Life with Ed: A case study of a linux BIOS/BProc cluster

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16th Annual International symposium on high performance computing Systems and Applications, HPCS 2002

作者： Choi, Sung-Eun Hendriks, Erik A. Minnich, Ronald G. Sottile, Matthew J. Marks, Aaron J. Advanced Computing Laboratory Los Alamos National Laboratory Los AlamosNM87545 United States Department of Computer and Information Science University of Pennsylvania PhiladelphiaPA19104 United States

ISBN: (纸本)0769516262

In this paper, we describe experienc es with our 127- no de/161-processor A lpha cluster testbed, Ed. Ed is unique for two distinct reasons. First, we have replac ed the standard BIOS on the cluster no des with the Lin- uxBIOS which loads Linux directly from non-volatile memory (Flash RAM). Se cond, the op erating system provides a single-system image of the entir e cluster, much like a traditional supercomputer. We will discuss the advantages of such a cluster, including time to boot (101 se conds for 100 nodes), upgrade (same as time to boot), and start processes (2.4 seconds for 15,000 pro- cesses). A dditionally,we have disc over edthat certain predictions about the nature of terascale clusters, such as the ne ed for hier archical structur e,are false. Fi- nally, we argue that to achieve true scalability, teras- cale clusters must be built in the way of Ed. © 2002 IEEE.

关键词： Linux

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