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Fast and guaranteed C compilation onto the PACT-XPP/spl trade/ reconfigurable computing platform

Fast and guaranteed C compilation onto the PACT-XPP/spl trad...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： J.M.P. Cardoso M. Weinhardt PACT Informationstechnologie AG Munich Germany

We introduce the XPP-VC high-level compiler, which maps C programs to the coarse-grained XPP architecture. XPP-VC's main feature is the integration of pipeline vectorization and temporal partitioning techniques. the former provides high-throughput inner loop computations and the later allows the compilation of large programs or the use of fewer XPP processing elements. Although the preliminary results are very encouraging, improvements on the generation of configurations are still required. the evaluation we have conducted shows that only a few seconds are required to generate, from algorithms in C, the binaries to program the XPP. To our knowledge this compilation performance is unmatched by any other compiler targeting reconfigurable architectures. Moreover the compiler still achieves high-performance implementations. Since the XPP is delivered as an IP core or device to be coupled to a host processor, a future version of XPP-VC will consider co-compilation, i.e., compilation to hybrid microprocessor/XPP architectures.

关键词： computer architecture Field programmable gate arrays Concurrent computing high performance computing Roads Parallel processing Adaptive arrays Array signal processing LAN interconnection Frequency synchronization

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GRIP: a reconfigurable architecture for host-based gigabit-rate packet processing

GRIP: a reconfigurable architecture for host-based gigabit-r...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： P. Bellows J. Flidr T. Lehman B. Schott K.D. Underwood Information Science Institute University of Southern California Arlington VA USA

One of the fundamental challenges for modern high-performance network interfaces is the processing capabilities required to process packets at high speeds. Simply transmitting or receiving data at gigabit speeds fully utilizes the CPU on a standard workstation. Any processing that must be done to the data, whether at the application layer or the network layer, decreases the achievable throughput. this paper presents an architecture for offloading a significant portion of the network, processing from the host CPU onto the network interface. A prototype, called the GRIP (Gigabit Rate IPSec) card, has been constructed based on an FPGA coupled with a commodity Gigabit Ethernet MAC. Experimental results based on the prototype are presented and analyzed. In addition, a second generation design is presented in the context of lessons learned from the prototype.

关键词： Reconfigurable architectures Network interfaces Prototypes computer networks Cryptography Application software Military computing Bandwidth Protocols computer interfaces

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Optimizing graph algorithms for improved cache performance

Optimizing graph algorithms for improved cache performance

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Joon-Sang Park M. Penner V.K. Prasanna University of Southern California France

Tiling has long been used to improve cache performance. Recursion hers recently been used as a cache-oblivious method of improving cache performance. Both of these techniques are normally applied to dense linear algebra problems. We develop new implementations by means of these two techniques for the fundamental graph problem of Transitive Closure, namely the Floyd-Warshall Algorithm, and prove their optimality with respect to processor-memory traffic. Using these implementations we show up to 10× improvement in execution time. We also address Dijkstra's algorithm for the single-source shortest path problem and Prim's algorithm for Minimum Spanning Tree, for which neither tiling nor recursion can be directly applied. For these algorithms, we demonstrate up to a 2× improvement by using a cache friendly graph representation. Experimental results are shown for the Pentium Ill, UltraSPARC Ill, Alpha 21264, and MIPS R12000 machines using problem sizes between 1024 and 4096 vertices. We demonstrate improved cache performance using the Simplescalar simulator.

关键词： Linear algebra Costs Distributed computing Optimizing compilers Tree graphs Traffic control Microprocessors Routing computer networks Circuit synthesis

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Finding good peers in peer-to-peer networks

Finding good peers in peer-to-peer networks

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： M. Krishna Ramanathan V. Kalogeraki J. Pruyne Department of Computer Sciences Purdue University IN USA Hewlett Packard Laboratory Palo Alto CA USA

As computing and communication capabilities have continued to increase, more and more activity is taking place at the edges of the network, typically in homes or on workers desktops. this trend has been demonstrated by the increasing popularity and usability of "peer-to-peer" systems, such as Napster and Gnutella. Unfortunately, this popularity has quickly shown the limitations of these systems, particularly in terms of scale. Because the networks form in an ad-hoc manner, they typically make inefficient use of resources. We propose a mechanism, using only local knowledge, to improve the overall performance of peer-to-peer networks based on interests. Peers monitor which other peers frequently respond successfully to their requests for information. When a peer is discovered to frequently provide good results, the peer attempts to move closer to it in the network by creating a new connection with that peer. this leads to clusters of peers with similar interests, and in turn allows us to limit the depth of searches required to find good results. We have implemented our algorithm in the context of a distributed encyclopedia-style information-sharing application which is built on top of the Gnutella network. In our testing environment, we have shown the ability to greatly reduce the amount of communication resources required to find the desired articles in the encyclopedia.

关键词： Intelligent networks Peer to peer computing computer networks Home computing Monitoring Scalability Bandwidth Usability Clustering algorithms Context

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On reliable and scalable peer-to-peer Web document sharing

On reliable and scalable peer-to-peer Web document sharing

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Li Xiao Xiaodong Zhang Zhichen Xu Department of Computer Science College of William and Mary Williamsburg VA USA Hewlett Packard Laboratories Internet Systems and Storage Laboratory Palo Alto CA USA

ISBN: (纸本)0769515738

We propose a peer-to-peer Web document sharing technique, called a "browser-aware proxy server". In this design, a proxy server connecting to a group of networked clients maintains an index file of data objects of all the clients' browser caches. If a user request misses in its local browser cache and the proxy cache, the browser-aware proxy server searches the index file, attempting to find it in another client's browser cache before sending the request to an upper-level proxy or to the Web server. If such a hit is found in a client, this client directly forwards the data object to the requesting client, or the proxy server fetches the data object from this client and then forwards it to the requesting client. Trace-driven simulations show that the amount of sharable data in browser caches is significant and can be utilized for peer-to-peer document sharing to improve Web caching performance and scalability. We also address the issues of data integrity and communication anonymity in order to build a reliable browser-aware proxy server.

关键词： Peer to peer computing Web server Distributed computing Internet Network servers Laboratories File servers Data security computer science Educational institutions

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Large system performance of SPEC OMP2001 Benchmarks

Large system performance of SPEC OMP2001 Benchmarks

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4th International symposium on high performance computing, ISHPC 2002

作者： Saito, Hideki Gaertner, Greg Jones, Wesley Eigenmann, Rudolf Iwashita, Hidetoshi Lieberman, Ron Van Waveren, Matthijs Whitney, Brian Intel Corporation SC12-301 3601 Juliette Lane Santa Clara CA 95052 United States Compaq Computer Corporation United States Silicon Graphics Incorporated United States Purdue University United States Fujitsu Limited Japan Hewlett-Packard Corporation United States Fujitsu European Centre for IT Limited Japan Sun Microsystems Incorporated United States

ISBN: (纸本)354043674X

performance characteristics of application programs on large-scale systems are often significantly different from those on smaller systems. SPEC OMP2001 is a benchmark suite intended for measuring performance of modern shared memory parallel systems. the first component of the suite, SPEC OMPM2001, is developed for medium-scale (4- to 16-way) systems. We present our experiences on benchmark development in achieving good scalability using the OpenMP API. this paper then analyzes the published results of SPEC OMPM2001 on large systems (32-way and larger), based on application program behavior and systems' architectural features. the ongoing development of the SPEC OMP2001 benchmark suites is also discussed. Its main feature is the increased data set for large-scale systems. We refer to this suite as SPEC OMPL2001, in contrast to the current SPEC OMPM2001 (medium data set) suite. © 2002 Springer Berlin Heidelberg.

关键词： Application programs

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the design of the Amalgam reconfigurable cluster

The design of the Amalgam reconfigurable cluster

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： J.D. Walstrom J.J. Cook D.B. Gottlieb S. Ferrera Chi-Wei Wang N.P. Carter Center for Reliable and High Performance Computing University of Illinois Urbana-Champaign USA

Amalgam is a novel architecture for multifunction embedded systems. It integrates multiple reconfigurable and programmable processing resources (known as clusters) to achieve high-performance with low design effort on a variety of multimedia applications. the reconfigurable cluster (RClust) enables Amalgam to exploit the natural parallelism and operator granularities of a target application. the RClust contains a ring of reconfigurable logic interleaved with a banked register file to support Amalgam's register-based inter-cluster communication mechanism. this low-latency mechanism allows the RClust to coordinate with a programmable cluster (PClust) as a special purpose junctional unit implementing small custom operations. the relatively large size of the cluster, however, allows it to implement larger, more independent computational kernels. In this extended abstract, we describe the initial design of the RClust and present results from mapping several benchmarks to Amalgam architectures with and without RClust elements.

关键词： Registers computer architecture Reconfigurable logic Programmable logic arrays Embedded system Parallel processing Logic arrays high performance computing Kernel Cellular phones

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A framework for using benefit functions in complex real time systems

A framework for using benefit functions in complex real time...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： D. Andrews L.R. Welch S. Brandt Electrical Eng. & Computer Science ITTC University of Kansas Lawrence KS Electrical Eng. & Computer Science Ohio University Athens Ohio

Researchers are currently investigating applying benefit, or utility functions for allocating resources in limited, soft real time systems. While the future of real-time computing research and practice will likely exploit the utility of benefit-based models, this will not occur until a suitable system level benefit framework has been defined. this paper provides an overview of ongoing work to develop such an initial framework that can formalize the use of benefit functions in complex real time systems. It is easily shown that this framework can support traditional hard/firm/soft real-time paradigms as well as support newer proposed models for future real time operation. We also show that our proposed framework unifies composition of benefit values derived from heterogeneous perspectives, including those derived from the application perspective.

关键词： Real time systems computer science Resource management Aggregates Lifting equipment System performance Radio spectrum management Distributed processing Bandwidth

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MySRB and SRB - components of a Data Grid

MySRB and SRB - components of a Data Grid

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International symposium on high performance Distributed computing

作者： A. Rajasekar M. Wan R. Moore San Diego Supercomputer Center University of California San Diego USA

Data Grids are becoming increasingly important in scientific communities for sharing large data collections and for archiving and disseminating them in a digital library framework. the Storage Resource Broker (SRB) provides transparent virtualized middleware for sharing data across distributed, heterogeneous data resources separated by different administrative and security domains. the MySRB is a Web-based interface to the SRB that provides a user-friendly interface to distributed collections brokered by the SRB. In this paper we briefly describe the use of the SRB infrastructure as tools in the data grid architecture for building distributed data collections, digital libraries, and persistent archives. We also provide details about the MySRB and its functionalities.

关键词： Software libraries Dissolved gas analysis Buildings Environmental management computer networks Middleware Space technology Linux Supercomputers Secure storage

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Mapping algorithms to the Amalgam programmable-reconfigurable processor

Mapping algorithms to the Amalgam programmable-reconfigurabl...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： J.J. Cook D.B. Gottlieb J.D. Walstrom S. Ferrera Chi-Wei Wang N.P. Carter Center for Reliable and High Performance Computing University of Illinois Urbana-Champaign USA

the Amalgam programmable-reconfigurable processor is designed to provide the computational power required by upcoming embedded applications without requiring the design of application-specific hardware. It integrates multiple programmable processors and blocks of reconfigurable logic onto a single chip, using a clustered architecture, similar to the one used on the M-Machine to reduce wire length and delay and allow implementation at high clock rates. the clustered architecture provides tremendous flexibility, allowing applications to exploit parallelism at whatever granularity is best-suited to the application, while the combination of reconfigurable logic and programmable processors delivers much higher performance than could be achieved through programmable processors alone. this abstract presents the results of our initial experiments in hand-mapping applications onto Amalgam. Five applications (IDCT, Rijndael encryption, nQueens, DNA sequence comparison, and image dithering) have been implemented, achieving speedups ranging from 8.7/spl times/ to 23.2/spl times/ over the performance of a single programmable cluster by using the complete resources of an Amalgam chip.

关键词： Reconfigurable logic Clustering algorithms Process design Embedded computing Hardware computer architecture Wire Delay Clocks Parallel processing

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