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Faster collective output through active buffering

Faster collective output through active buffering

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Xiaosong Ma M. Winslett Jonghyun Lee Shengke Yu Department of Computer Science University of Illinois Urbana-Champaign USA

Scientific applications often need to write out large arrays and associated metadata periodically for visualization or restart purposes. In this paper, we propose active buffering for collective I/O, in which processors actively organize their idle memory into a hierarchy of buffers for periodic output data. Active buffering exploits one-sided communication for I/O processors to fetch data from compute processors' buffers and performs actual writing in the background while compute processors are computing. It gracefully adapts as buffers at different level of the hierarchy fill and empty, and as new collective I/O requests arrive. Experimental results with synthetic benchmarks and a real rocket simulation code on the SGI Origin 2000 and IBM SP show that active buffering improves the apparent collective write throughput so that it approaches the local memory bandwidth or the MPI bandwidth under appropriate conditions. these speedups are due entirely to increased parallelism during I/O, and are in addition to any performance improvements that may come from buffering small requests.

关键词： File systems Data visualization throughput Bandwidth Buffer overflow Switches computer science Application software Writing Computational modeling

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Fine-grain priority scheduling on multi-channel memory systems

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IEEE symposium on high-performance computer architecture

作者： Zhichun Zhu Zhao Zhang Xiaodong Zhang

ISBN: (纸本)0769515258

Configurations of contemporary DRAM memory systems become increasingly complex. A recent study shows that the application performance is highly sensitive to choices of configurations. In this study we show that, by utilizing fine-grain priority access scheduling, we are able to find a workload independent configuration that achieves optimal performance on a multichannel memory system. Our approach can well utilize the available high concurrency and high bandwidth on such memory systems, and effectively reduce the memory stall time of memory-intensive applications. Conducting execution-driven simulation of a 4-way issue, a 2 GHz processor, we show that the average performance improvement for fifteen memory-intensive SPEC2000 programs by using an optimized fine-grain priority scheduling is about 13% and 8% for a 2-channel and a 4-channel Direct Rambus DRAM memory system, respectively, compared with gang scheduling. Compared with burst scheduling, the average performance improvement is 16% and 14% for the 2-channel and 4-channel memory systems, respectively.

关键词： Random access memory Processor scheduling Application software Concurrent computing Bandwidth Delay computer science Educational institutions Resumes System performance

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Scheduling multiple data visualization query workloads on a shared memory machine

Scheduling multiple data visualization query workloads on a ...

引用

International symposium on Parallel and Distributed Processing (IPDPS)

作者： H. Andrade T. Kurc A. Sussman J. Saltz Department of Computer Science University of Maryland College Park MD USA Department of Biomedical Informatics Ohio State Uinversity Columbus OH USA

Query scheduling plays an important role when systems are faced with limited resources and high workloads. It becomes even more relevant for servers applying multiple query optimization techniques to batches of queries, in which portions of datasets as well as intermediate results are maintained in memory to speed up query evaluation. We present a dynamic query scheduling model based on a priority queue implementation using a directed graph and a strategy for ranking queries. We examine the relative performance of several ranking strategies on a shared-memory machine using two different versions of an application, called the Virtual Microscope, for browsing digitized microscopy images.

关键词： Data visualization Data analysis Query processing Atomic force microscopy Processor scheduling computer science Educational institutions Biomedical informatics Relational databases Deductive databases

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the minimax cache: an energy-efficient framework for media processors

引用

IEEE symposium on high-performance computer architecture

作者： O.S. Unsal I. Koren C. Mani Krishna C.A. Moritz Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

ISBN: (纸本)0769515258

this work is based on our philosophy of providing interlayer system-level power awareness in computing systems. Here, we couple this approach with our vision of multi-partitioned memory systems, where memory accesses are separated based on their static predictability and memory footprint and managed with various compiler controlled techniques. We show that media applications are mapped more efficiently when scalar memory accesses are redirected to a mini-cache. Our results indicate that a partitioned 8K cache with the scalars being mapped to a 512 byte mini-cache can be more efficient than a 16K monolithic cache from both performance and energy point of view for most applications. In extensive experiments, we report 30% to 60% energy-delay product savings over a range of system configurations and different cache sizes.

关键词： Minimax techniques Energy efficiency Memory management Interference Hardware Application software Registers Power engineering computing Power system management Control systems

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Efficient pipelining of nested loops: unroll-and-squash

Efficient pipelining of nested loops: unroll-and-squash

引用

International symposium on Parallel and Distributed Processing (IPDPS)

作者： D. Petkov R. Harr S. Amarasinghe Massachusetts Institute of Technology UK Synopsys Inc. USA

the size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology to map abstract designs into silicon. Since streaming data processing in DSP applications is typically described by loop constructs in a high-level language, loops are the most critical portions of the hardware description and special techniques are developed to optimally synthesize them. We introduce a new method for mapping and pipelining nested loops efficiently into hardware. It achieves fine-grain parallelism even on strong intra- and inter-iteration data-dependent inner loops and, by sharing resources economically, improves performance at the expense of a small amount of additional area. We implemented the transformation within the Nimble Compiler environment and evaluated its performance on several signal processing benchmarks. the method achieves up to 2× improvement in the area efficiency compared to the best known optimization techniques.

关键词： Pipeline processing Hardware Very large scale integration computer languages Program processors Silicon Data processing Digital signal processing high level languages Environmental economics

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BioGRID - An European grid for molecular biology

BioGRID - An European grid for molecular biology

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International symposium on high performance Distributed computing

作者： P. Bala J. Pytlinski M. Nazaruk Faculty of Mathematics and Computer Science N. Copernicus University Torun Poland ICM Warsaw University Warsaw Poland

Recent advances in computer technology, especially grid tools makes them good candidate for development of user interfaces to computing programs and resources. Computational grids enable sharing a wide variety of geographically distributed resources and allow selection and aggregation of distributed resources across multiple organizations for solving large scale computational and data intensive problems in science. User point of view is most important principle in the development of the UNICORE software which was used to establish European computational grid - EUROGRID. BioGRID is application oriented grid which adopts EUROGRID infrastructure to the specific area, namely molecular biology and quantum chemistry. UNICORE is uniform interface to the computer resources which allows user to prepare, submit and control application specific jobs and file transfers. Compare to the other tools BioGRID, using UNICORE as main grid tool, has wider functionality, is more flexible and allows for much easier integration of the User interface with external quantum chemistry or biomolecular applications. Within the UNICORE environment user has a comfortable way to use distributed computing resources without having to learn for site or system specifics. Details of the UNICORE can be found elsewhere. the UNICORE architecture is based, as other grid middleware, on the three tier model. It consists of user, server and target system tier. the user tier consists of the graphical user interface - UNICORE client - written as Java application. User can specify target system and resources required for jobs using standard UNICORE client facilities. User can check job status, monitor execution and retrieve output to the local workstation. All these functions can be performed from the UNICORE client with the single login during client startup. User can monitor job status and retrieve output to any computer connected to the network with the UNICORE client installed. We have used UNICORE as framew

关键词： Biology computing Grid computing Application software computer interfaces User interfaces Distributed computing Chemistry Java computerized monitoring Large-scale systems

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A design space exploration framework for reduced bit-width Instruction Set architecture (rISA) design

A design space exploration framework for reduced bit-width I...

引用

International symposium on System Synthesis

作者： A. Halambi A. Shrivastava P. Biswas N. Dutt A. Nicolau Center for Embedded Computer Systems Department of Information and Computer Science University of California Irvine CA USA

Code size is a critical concern in many embedded system applications, especially those using RISC cores. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, space-efficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. this feature (termed rISA) can potentially reduce the code size by up to 50% with minimal performance degradation. However, contemporary processors incorporate only a simple rISA feature with severe restrictions on register accessibility. We present a compiler-in-the-loop Design Space Exploration framework that is capable of exploring various interesting rISA designs. We also present experimental results using this framework and show rISA designs that improve on the code size reduction obtained by existing rISA architectures.

关键词： Space exploration Reduced instruction set computing computer architecture Embedded system computer aided instruction Embedded computing Registers thumb Permission Read only memory

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HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform

HW/SW partitioning and code generation of embedded control a...

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International Workshop on Hardware/Software Codesign (CODES)

作者： M. Baleani F. Gennari Yunjian Jiang Y. Patel R.K. Brayton A. Sangiovanni-Vincentelli PARADES E.E.I.G. Rome Italy Department of EECS University of California Berkeley CA USA

this paper studies the use of a reconfigurable architecture platform for embedded control applications aimed at improving real time performance. the HW/SW codesign methodology from POLIS is used. It starts from high-level specifications, optimizes an intermediate model of computation (extended finite state machines) and derives both hardware and software, based on performance constraints. We study a particular architecture platform, which consists of a general purpose processor core, augmented with a reconfigurable function unit and data-path to improve run time performance. A new mapping flow and algorithms to partition hardware and software are proposed to generate implementations that best utilize this architecture. Encouraging preliminary results are shown for automotive electronic control examples.

关键词： Hardware computer architecture Reconfigurable architectures Application software Constraint optimization Computational modeling high performance computing Automata Software performance Partitioning algorithms

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Load balancing highly irregular computations with the adaptive factoring

Load balancing highly irregular computations with the adapti...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： I. Banicescu V. Velusamy Department of Computer Science Engineering Research Center for Computational Systems Mississippi State University USA

In heterogeneous environments, employing dynamic scheduling algorithms to improve performance of scientific applications via load balancing is essential. Presently, these algorithms require prior knowledge about workload via profiling resulting in higher overhead as problem sizes and number of processors increase. In addition, variations in work load at runtime may be unpredictable, making profiling work tedious and sometimes even obsolete. therefore, dynamic loop scheduling schemes such as Factoring, Fractiling, andWeighted Factoring have been proposed and proved to be extremely instrumental when used in scientific applications such as Monte-Carlo simulations, N-Body simulations, radar applications, and others. Adaptive Factoring, a technique that evolves from these schemes and addresses a wider range of irregularities has recently been proposed. this paper reports on performance improvements obtained by integrating the Adaptive Factoring, into a scientific application that invloves computational field simulation on unstructured grids. performance of this scientific application using the implementation with Adaptive Factoring is compared with implementations using other dynamic loop scheduling techniques. Reported experimental results confirm the benefits of using the Adaptive Factoring and its high potential for a successful integration in other scientific applications, especially the ones characterized by highly irregular behaviour whose performance degradation is primarily due to load imbalance.

关键词： Load management Computational modeling Delay Dynamic scheduling Heuristic algorithms Application software Runtime Processor scheduling Computational fluid dynamics computer science

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Peppermint and Sled: tools for evaluating SMP systems based on IA-64 (IPF) processors

Peppermint and Sled: tools for evaluating SMP systems based ...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： S. Basu S. Roy R. Kumar T. Fisher B.E. Blaho Hewlett-Packard Laboratories Hewlett Packard Company Palo Alto CA USA Technical Computing Division Hewlett Packard Company Fort Collins CO USA

In this paper, we describe Peppermint and Sled: tools developed for evaluations of computer systems based on IA-64 processors. Sled generates trace from applications running on IA-64 processors, while Peppermint models the complete system using cycle-accurate, trace-driven simulation. Peppermint is based on Augmint, which leaves open the possibility of doing execution-driven simulations in future. Peppermint and Sled allow us to perform a trace-based evaluation of 4 applications running on SMP systems based on Itanium and McKinley processors. We find that the improvement in IPC of McKinley relative to Itanium ranges from 7% to over 100% for our different applications. the improvement can be attributed to a variety of factors. these range from the availability of additional functional units and issue ports in the McKinley processor to our assumption of a better memory system. While the improvement in performance remains valid in SMP systems in some cases, higher contention for system bus and memory reduces the performance gain in other cases. Increasing the system bits bandwidth and size of queues for pending requests in the memory controller are identified as first steps for optimizing SMP performance.

关键词： Application software Cost accounting Computational modeling Laboratories Milling machines Read only memory Availability performance gain Bandwidth Size control

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