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10th Annual IEEE International symposium on high performance Distributed computing

作者： Czajkowski, K Fitzgerald, S Foster, I Kesselman, C Univ So Calif Inst Informat Sci Marina Del Rey CA 90292 USA

ISBN: (纸本)0769512968

Grid technologies enable large-scale sharing of resources within formal or informal consortia of individuals and/or institutions: what are sometimes called virtual organizations. In these settings, the discovery, characterization, and monitoring of resources, services, and computations are challenging problems due to the considerable diversity, large numbers, dynamic behavior and geographical distribution of the entities in which a user might be interested. Consequently, information services are a vital part of any Grid software infrastructure, providing fundamental mechanisins for discovery, and monitoring, and hence for planning and adapting application behavior We present here an information services architecture that addresses performance, security, scalability, and robustness requirements. Our architecture defines simple low-level enquiry and registration protocols that make it easy to incorporate individual entities into various information structures, such as aggregate directories that support a variety of different query languages and discovery strategies. these protocols can also be combined with other Grid protocols to construct additional higher-level services and capabilities such as brokering, monitoring, fault detection, and troubleshooting. Our architecture has been implemented as MDS-2, which forms part of the Globus Grid toolkit and has been widely deployed and applied.

关键词： Distributed computer systems

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the Logistical Session Layer

The Logistical Session Layer

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10th Annual IEEE International symposium on high performance Distributed computing

作者： Swany, DM Wolski, R Univ Tennessee Comp Sci Dept Knoxville TN 37996 USA

ISBN: (纸本)0769512968

the Logistical Session Layer is a system to enable enhanced functionality to distributed programming systems. the term Logistical refers to the fact that we enhance the traditional client-server model to allow for intermediate systems which are neither. this system generalizes the notion of caches but represents a cleaner architecture in that it explicitly declares itself to be a session layer protocol.

关键词： Client server computer systems

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Speculative precomputation: Long-range prefetching of delinquent loads

Speculative precomputation: Long-range prefetching of delinq...

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28th Annual International symposium on computer architecture

作者： Collins, JD Wang, H Tullsen, DM Hughes, C Lee, YF Lavery, D Shen, JP Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

ISBN: (纸本)0769511627

this paper explores Speculative Precomputation, a technique that uses idle thread contexts in a multithreaded architecture to improve performance of single-threaded applications. It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. this technique is evaluated by simulating the performance of a research processor based on the Itanium(TM) ISA supporting Simultaneous Multithreading. Two primary forms of Speculative Precomputation are evaluated. If only the non-speculative thread spawns speculative threads, performance gains of up to 30% are achieved when assuming ideal hardware. However this speedup drops considerably with more realistic hardware assumptions. Permitting speculative threads to directly spawn additional speculative threads reduces the overhead associated with spawning threads and enables significantly more aggressive speculation, overcoming this limitation. Even with realistic costs for spawning threads, speedups as high as 169% are achieved, with an average speedup of 76%.

关键词： Reduced instruction set computing

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Middleware support for global access to integrated computational collaboratories

Middleware support for global access to integrated computati...

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10th Annual IEEE International symposium on high performance Distributed computing

作者： Mann, V Parashar, M Rutgers State Univ Dept Elect & Comp Engn Appl Software Syst Lab Piscataway NJ 08854 USA

ISBN: (纸本)0769512968

the growth of the Internet and the advent of the computational "Grid" have made it possible to develop and deploy advanced computational collaboratories. these systems build on high-end computational resources and communication technologies underlying the Grid, and provide seamless and collaborative access to particular resources, services or applications. Integrating these 'focused" collaboratories presents significant challenges. Key among these is the design and development of robust middleware support that addresses scalability, service discovery, security and access control, and interaction and collaboration management for consistent access. In this paper we first investigate the architecture of such a middleware that enables global (web-based) access to collaboratories. We then present the design and implementation of a middle-ware substrate that enables a peer-to-peer integration of and global (collaborative) access to geographically, distributed instances of the DISCOVER computational collaboratory for interaction and steering.

关键词： computer supported cooperative work

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Dynamic thermal management for high-performance microprocessors

Dynamic thermal management for high-performance microprocess...

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7th International symposium on high-performance computer architecture

作者： Brooks, David Martonosi, Margaret Princeton Univ Princeton United States

With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPU power dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip's rated maximum power dissipation. However, system designers still must design thermal heat sinks to withstand the worst-case scenario. We define and investigate the major components of any dynamic thermal management scheme. Specifically we explore the tradeoffs between several mechanisms for responding to periods of thermal trauma and we consider the effects of hardware and software implementations. With appropriate dynamic thermal management, the CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications.

关键词： Microprocessor chips

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Pipelined all-to-all broadcast in all-port meshes and tori

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IEEE TRANSACTIONS ON computerS 2001年第10期50卷 1020-1032页

作者： Yang, YY Wang, JC SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA DataTreasury Corp Melville NY 11747 USA

All-to-all communication is one of the most dense communication patterns and occurs in many important applications in parallel computing. In this paper, we present a new all-to-all broadcast algorithm in all-port meshes and tori. the algorithm utilizes a controlled message flooding based on a novel broadcast pattern, which ensures a balanced traffic load in all dimensions in the network so that the optimal transmission time for all-to-all broadcast can be achieved. the broadcast pattern is described in a formal, generic way for each node in terms of a few simple operations and can be easily built into router hardware. Unlike existing all-to-all broadcast algorithms, the new algorithm overlaps message switching time with transmission time in a pipelined fashion to reduce the total communication delay of all-to-all broadcast. In most cases, the total communication delay is close to the lower bound of all-to-all broadcast within a small constant range. Finally, the algorithm is conceptually simple and symmetrical for every message and every node so that it can be easily implemented in hardware and achieves the optimum in practice.

关键词： parallel computing collective communication all-to-all communication all-to-all broadcast gossip broadcast tree routing interprocessor communication

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Parallel retrograde analysis on different architecture

Parallel retrograde analysis on different architecture

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10th Annual IEEE International symposium on high performance Distributed computing

作者： Wu, R Beal, DF HP Laboratories Hewlett-Packard Company Palo Alto CA United States

ISBN: (纸本)0769512968

Retrograde analysis is an efficient exhaustive search method. It is a powerful tool that can be used in solving problems where end states have known values but starting states do not. It has been widely used to solve mathematically-precise games such as chess endgames, and is potentially usable in energy-minimization problems. With increasing computing power, both in speed and storage capacity, retrograde analysis will become more and more useful. this paper looks at successful applications to games, the challenges ahead, and the modifications that are required to utilize distributed hardware. the power and the usefulness of retrograde analysis are still limited by the computing resources one has access to. Today, the best sequential retrograde algorithms are capable of solving problems with about 109 states in a few hours on a standard personal computer Bigger problems need more powerful computers, or take much longer to solve, or are simply out of reach of today's technologies, Introducing parallelism to retrograde analysis is a natural way to attack the bigger problems. there are today three main architectures available for doing parallel retrograde analysis: namely Symmetric Multiprocessor systems, high-speed network based distributed systems, and Internet based distributed systems. In this paper, we discuss some of the key issues in doing parallel retrograde analysis on these different architectures. Technical challenges are addressed in detail, as well as some examples and proposals. these examples and proposals are drawn from various board games, but the ideas can be applied to other problem domains.

关键词： Distributed computer systems

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architecture, implementation, and deployment of a high performance, high capacity resilient mass storage server (RMSS) 18

Architecture, implementation, and deployment of a high perfo...

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18th IEEE symposium on Mass Storage Systems and Technologies, MSS 2001

作者： Jones, Terry Sarnowska, Beata Lovato, Frank Magee, David Kothe, John Bldg 1001 Stennis Space Center MS39529 United States

ISBN: (纸本)0769508499

the Naval Oceanographic Office (NAVOCEANO) high performance computing (HPC) Major Shared Resource Center (MSRC) recently reengineered the existing mass storage system serving its high-performance compute platforms. the purpose was to provide significantly improved file system availability, to refresh the technology and the architectural design, and to position the MSRC to incorporate emerging technologies such as Storage Area Networks (SANs). the resultant configuration utilizes two SUN Enterprise 10000s (E10K) with 3 TB of switched Fibre Channel Disk Arrays and the latest generation of tape devices. the theoretical peak system capacity is in excess of 2 Terabytes (TB) per day, with management of up to 1 PetaBytes (PB) of storage and an aggregate external network throughput of 220 Megabytes (MB) per second. this paper discusses the technologies and considerations used in the design of the MSRC Resilient Mass Storage Server (RMSS), its architecture, implementation and integration, deployment and transition from the existing CRAY Data Migration Facility (DMF). © 2001 IEEE.

关键词： computer architecture

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Fault-tolerant embedded computer system-on-chip for endoscope control

Fault-tolerant embedded computer system-on-chip for endoscop...

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9th International symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems

作者： Khan, Gul N. Wee, Siew Hoon Dept. of Elec. and Comp. Engineering Ryerson University 350 Victoria Street Toronto Ont. M5B 2K3 Canada Innomedia Pte Ltd 10 Science Park Road 03-04 SSP II Singapore 117684 Singapore

the processor architecture of a fault tolerant embedded system is presented, which implements a machine vision based navigation system of a colonoscope. the automation of colonoscopy requires high performance computing for image analysis and navigation while fault-tolerance for patient safely. high performance computing and real-time control is achieved by a hardware engine of heterogeneous multiple processors. the software architecture consists of system as well as application level endoscope control processes. the target architecture adapts itself to the varying needs of machine vision and navigation algorithms. Embedded system development is a hardware software codesign problem where the hardware and software architectures are designed simultaneously. the virtual hardware system is constructed using HDL-based virtual processor cores and other hardware modules. the system and application software is developed and co-verified with the virtual hardware using Eagle;toolset. the hardware software co-verification results indicate that the system performance degrades gracefully under various fault scenarios.

关键词： Microprocessor chips

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Evolving the Web-based distributed SI/PDO architecture for high-performance visualization

Evolving the Web-based distributed SI/PDO architecture for h...

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34th Annual Simulation symposium

作者： Holmes, VP Linebarger, JM Miller, DJ Vandewart, RL Crowley, CP Sandia Natl Labs Albuquerque NM 87185 USA

ISBN: (纸本)0769510922

We have extended the SI/PDO architecture to allow web access to visualization tools running on MP systems. We make these tools more easily accessible by providing web-based interfaces and by shielding the user from the details of these computing environments. We use a multi-tier architecture, where the Java-based GUI tier runs on a web browser and provides image display and control functions. the visualization tier runs on MP machines. the middle tiers provide custom communication with MP machines, remote file selection, remote launching of services, and load balancing. the system allows for adding and removing of tiers depending upon the situation. this architecture is based on the requirements of our environment: huge data volumes (that cannot be easily moved), use of multiple middleware protocols, MP platform portability, rapid development of the visualization tools, distributed resource management (of MP resources), and the use of existing visualization tools.

关键词： Distributed computer systems

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