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performance characterization of large and long fibre channel arbitrated loops

Performance characterization of large and long fibre channel...

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IEEE symposium on Mass Storage Systems

作者： T.M. Ruwart Laboratory for Computational Science and Engineering University of Minnesota USA

the bandwidth performance of a Fibre Channel Arbitrated Loop (FCAL) is roughly defined to be 100 MegaBytes (100 bytes) per second. Furthermore, FCAL is capable of a theoretical peak of 40,000 I/O operations (transactions) per second. these performance levels, however, are largely not realized by the applications that use Fibre Channel as an interface to disk subsystems. the bandwidth and transaction performance of an Arbitrated Loop is sensitive to both the number of devices on the loop as well as the physical length of the loop. this study focuses on the effects of these two factors on the observed performance of Fibre Channel Arbitrated Loop as the number of nodes is scaled from 2 to 97 devices and as the physical length of the loop is scaled from 50 meters to several kilometers in length. To summarize, this study shows that the performance decreases significantly for very long loops and explains how this can be partially avoided. Also, the loop propagation delay on loops with many devices has only a moderate affect on performance. Finally, the effects of length tend to dominate the effects of population for very long, highly populated loops.

关键词： Optical fiber devices Disk drives Bandwidth Propagation delay Laboratories high performance computing Optical fiber communication Supercomputers Application software System testing

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A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization

A hardware-driven profiling scheme for identifying program h...

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Annual International symposium on computer architecture, ISCA

作者： M.C. Merten A.R. Trick C.N. George J.C. Gyllenhaal W.W. Hwu Center for Reliable and High-Performance Computing Department of Electrical and Computer Engineering University of Illinois Urbana IL USA

this paper presents a novel hardware-based approach for identifying, profiling, and monitoring hot spots in order to support runtime optimization of general-purpose programs. the proposed approach consists of a set of tightly coupled hardware tables and control logic modules that are placed in the retirement stage of a processor pipeline removed from the critical path. the features of the proposed design include rapid detection of program hot spots after changes in execution behavior, runtime-tunable selection criteria for hot spot detection, and negligible overhead during application execution. Experiments using several SPEC95 benchmarks, as well as several large WindowsNT applications, demonstrate the promise of the proposed design.

关键词： Runtime Hardware Optimizing compilers Production systems computerized monitoring Logic Retirement Pipelines performance gain Instruments

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MPI code encapsulating using parallel CORBA object

MPI code encapsulating using parallel CORBA object

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International symposium on high performance Distributed computing

作者： C. Rene T. Priol IRISA/IFSIC Rennes France IRISA/INRIA Rennes France

this paper describes a technique that allows an MPI code to be encapsulated into a component. Our technique is based on an extension to the Common Object Request Broker architecture (CORBA) from the OMG (Object Management Group). the proposed extensions do not modify the CORBA core infrastructure (the Object Request Broker) so that it can fully co-exist with existing CORBA applications. An MPI code is seen as a new kind of CORBA object that hides most of the cumbersome problems when dealing with parallelism. Such technique can be used to connect MPI codes to existing CORBA software infrastructures which are now being developed in the framework of several research and development projects such as JACO3, JULIUS or TENT from DLR. To illustrate the concept of parallel CORBA object, we present a virtual reality application that is made of the coupling of a light simulation application (radiosity) and a visualisation tool using VRML and Java.

关键词： Computational modeling Parallel processing Application software computer simulation Numerical simulation Middleware Distributed processing Concurrent computing Iris Research and development

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Is SC+ILP=RC?

Is SC+ILP=RC?

引用

Annual International symposium on computer architecture, ISCA

作者： C. Guiady B. Falsafi T.N. Vijaykumar Dept. of Electr. & Comput. Eng. Purdue Univ. West Lafayette IN USA School of Electrical & Computer Engineering Purdue University West Lafayette IN USA

Sequential consistency (SC) is the simplest programming interface for shared-memory systems but imposes program order among all memory operations, possibly precluding high performance implementations. Release consistency (RC), however, enables the highest performance implementations but puts the burden on the programmer to specify which memory operations need to be atomic and in program order. this paper shows, for the first time, that SC implementations can perform as well as RC implementations if the hardware provides enough support for speculation. Both SC and RC implementations rely on reordering and overlapping memory operations for high performance. To enforce order when necessary, an RC implementation uses software guarantees, whereas an SC implementation relies on hardware speculation. Our SC implementation, called SC++, closes the performance gap because: (1) the hardware allows not just loads, as some current SC implementations do, but also stores to bypass each other speculatively to hide remote latencies, (2) the hardware provides large speculative state for not just processor, as previously proposed, but also memory to allow out-of-order memory operations, (3) the support for hardware speculation does not add excessive overheads to processor pipeline critical paths, and (4) well-behaved applications incur infrequent rollbacks of speculative execution. Using simulation, we show that SC++ achieves an RC implementation's performance in all the six applications we studied.

关键词： Hardware Programming profession Delay high performance computing Out of order computer interfaces World Wide Web Pipelines Computational modeling Microprocessors

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DUNES: a performance-oriented system support environment for dependency maintenance in workstation networks

DUNES: a performance-oriented system support environment for...

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International symposium on high performance Distributed computing

作者： J. Cruz Kihong Park Network Systems Laboratory Department of Computer Sciences Purdue University West Lafayette IN USA

With the proliferation of workstation clusters connected by high-speed networks, providing efficient system support for concurrent applications engaging in nontrivial interaction has become an important problem. Two principal barriers to harnessing parallelism are: efficient mechanisms that achieve transparent dependency maintenance while preserving semantic correctness; and scheduling algorithms that match coupled processes to distributed resources while explicitly incorporating their communication costs. this paper describes a set of performance features, their properties, and implementation in a system support environment called DUNES that achieves transparent dependency maintenance-IPC, file access, memory access, process creation/termination, process relationships-under dynamic load balancing. the two principal performance features are push/pull-based active and passive end-point caching and communication-sensitive load balancing. Collectively, they mitigate the overhead introduced by the transparent dependency maintenance mechanisms. Communication-sensitive load balancing, in addition, affects the scheduling of distributed resources to application processes where both communication and computation costs are explicitly taken into account. the DUNES architecture endows commodity operating systems with distributed operating system functionality while achieving transparency with respect to their existing application base. DUNES also preserves semantic correctness with respect to single processor semantics.

关键词： Load management Operating systems Workstations high-speed networks Parallel processing Scheduling algorithm Costs Processor scheduling Distributed computing Computational efficiency

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Dodo: a user-level system for exploiting idle memory in workstation clusters

Dodo: a user-level system for exploiting idle memory in work...

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International symposium on high performance Distributed computing

作者： S. Koussih A. Acharya S. Setia Department of Computer Science George Mason University Fairfax VA USA Department of Computer Science University of California Santa Barbara CA USA

In this paper, we present the design and implementation of Dodo, an efficient user-level system for harvesting idle memory in off-the-shelf clusters of workstations. Dodo enables data-intensive applications to use remote memory in a cluster as an intermediate cache between local memory and disk. It requires no modifications to the operating system and/or processor firmware and is hence portable to multiple platforms. Further, the memory recruitment policy used by Dodo is designed to minimize any delays experienced by the owner of desktop machines whose memory is harvested by Dodo. Our implementation of Dodo is operational and currently runs on Linux 2.0.35. For communication, Dodo can use either UDP/IP or U-Net, the low-latency user-level network architecture developed by von Eicken et al. (1995). We evaluated the performance improvements that can be achieved by using Dodo for two real applications and three synthetic benchmarks. Our results show that speedups obtained for an application are highly dependent on its I/O access pattern and data set sizes. Significant speedups (between 2 and 3) were obtained for applications whose working sets are larger than the local memory on a workstation but smaller than aggregate memory available on the cluster and for applications that can benefit from the zero-seek nature of remote memory.

关键词： Workstations Memory management computer science Operating systems Aggregates SDRAM Costs Application software Microprogramming Delay

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Parallel Dispatch Queue: a queue-based programming abstraction to parallelize fine-grain communication protocols

Parallel Dispatch Queue: a queue-based programming abstracti...

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IEEE symposium on high-performance computer architecture

作者： B. Falsafi D.A. Wood School of Electrical & Computer Engineering Purdue University West Lafayette IN USA Computer Sciences Department University of Wisconsin Madison Madison WI USA

this paper proposes a novel queue-based programming abstraction, Parallel Dispatch Queue (PDQ), that enables efficient parallel execution of fine-grain software communication protocols. Parallel systems often use fine-grain software handlers to integrate a network message into computation. Executing such handlers in parallel requires access synchronization around resources. Much as a monitor construct in a concurrent language protects accesses to a set of data structures, PDQ allows messages to include a synchronization key protecting handler accesses to a group of protocol resources. By simply synchronizing messages in a queue prior to dispatch, PDQ not only eliminates the overhead of acquiring/releasing synchronization primitives but also prevents busy-waiting within handlers. In this paper, we study PDQ's impact on software protocol performance in the context of fine-grain distributed shared memory (DSM) on an SMP cluster. Simulation results running shared-memory applications indicate that: (i) parallel software protocol execution using PDQ significantly improves performance in fine-grain DSM, (ii) tight integration of PDQ and embedded processors into a single custom device can offer performance competitive or better than an all-hardware DSM, and (iii) PDQ best benefits cost-effective systems that use idle SMP processors (rather than custom embedded processors) to execute protocols. On a cluster of 4 16-way SMPs, a PDQ-based parallel protocol running on idle SMP processors improves application performance by a factor of 2.6 over a system running a serial protocol on a single dedicated processor.

关键词： Parallel programming Access protocols Protection Software performance computer networks Concurrent computing Monitoring Data structures Application software Embedded software

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A framework for scheduling and context allocation in reconfigurable computing

A framework for scheduling and context allocation in reconfi...

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International symposium on System Synthesis

作者： R. Maestre M. Fernandez R. Hermida N. Bagherzadeh Departamento de Arquitectura de Computadores y Automática Universidad Complutense de Madrid Madrid Spain Department of Electrical and Computer Engineering University of California Irvine CA USA

Reconfigurable computing is emerging as a viable design alternative to implement a wide range of computationally intensive applications. the scheduling problem becomes a really critical issue in achieving the high performance that these kind of applications demand. the paper describes the different aspects regarding the scheduling problem in a reconfigurable architecture. We also propose a general strategy in order to perform at compilation time a scheduling that includes all possible optimizations regarding context (configuration) and data transfers. In particular, we focus especially on the methodology and mechanisms to solve the context scheduling. Some experimental results are presented to validate our assumptions. Finally, the problem of data transfers is formulated, to be addressed in future work.

关键词： Processor scheduling Postal services computer applications Application software Identity-based encryption Roads Circuits Digital signal processing Multimedia computing Partitioning algorithms

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Low-cost access time model for serpentine tape drives

Low-cost access time model for serpentine tape drives

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IEEE symposium on Mass Storage Systems

作者： O. Sandsta R. Midtstraum Dept. of Comput. & Inf. Sci. Norwegian Univ. of Sci. & Technol. Trondheim Norway Department of Computer and Information Science Norwegian University of Science and Technology Trondheim Norway

When a serpentine tape drive is used as a slow random access device, the I/O performance can be substantially improved by clever re-ordering of the I/O requests. this kind of re-ordering relies on a scheduling algorithm and a model of the access time. In this paper, we propose a low-cost access time model for serpentine tape drives, which is not a trivial task due to the complex data layout of serpentine tape. this model provides a way to estimate the physical positions on the tape for any logical data block, provides cost functions to estimate the seek time between two physical tape positions, and computes the transfer time of a data request. Our experiments show that the mapping from logical address to physical position has to be instrumented once for each tape cartridge. Algorithms are given to do this at a low cost. the accuracy of the model is assessed by measurements on rape drives and by use in scheduling of I/O requests. Experiments show that the model estimates are good enough to facilitate efficient scheduling of I/O requests.

关键词： Processor scheduling Magnetosphere Drives Cost function Information science Scheduling algorithm Physics computing Instruments Modems Piecewise linear techniques

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Series approximation methods for divide and square root in the Power3/sup TM/ processor

Series approximation methods for divide and square root in t...

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computer Arithmetic (ARIth)

作者： R.C. Agarwal F.G. Gustavson M.S. Schmookler Research Division IBM Corporation Yorktown NY USA Server Development IBM Corporation Austin TX USA

the Power3 processor is a 64-bit implementation of the PowerPC/sup TM/ architecture and is the successor to the Power2/sup TM/ processor for workstations and servers which require high performance floating point capability. the previous processors used Newton-Raphson algorithms for their implementations of divide and square root. the Power3 processor has a longer pipeline latency, which would substantially increase the latency for these instructions. Instead, new algorithms based on power series approximations were developed which provide significantly better performance than the Newton-Raphson algorithm for this processor. this paper describes the algorithms, and then shows how both the series based algorithms and the Newton-Raphson algorithms are affected by pipeline length. For the Power3, the power series algorithms reduce the divide latency by over 20% and the square root latency by 35%.

关键词： Approximation methods Delay Pipelines Frequency Hardware Table lookup Silicon Reduced instruction set computing Microprocessor chips Algorithm design and analysis

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