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10 Workshops Held in Conjunction with the 12th International Parallel Processing symposium and 9th symposium on Parallel and Distributed Processing, IPPS/SPDP 1998

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10 Workshops held in conjunction with 12th International Parallel symposium and 9th symposium on Parallel and Distributed Processing, IPPS/SPDP 1998

ISBN: (纸本)3540643591

the proceedings contain 118 papers. the special focus in this conference is on Parallel and Distributed Processing. the topics include: Dynamic reconfiguration of a PMMLA for high-throughput applications;a parallel algorithm for minimum cost path computation on polymorphic processor array;a performance modeling and analysis environment for reconfigurable computers;an integrated partitioning and synthesis system for dynamically reconfigurabte multi-FPGA architectures;temporal partioning for partially-reconfigurable-field-programmable gate;a java development and runtime environment for reconfigurable computing;synthesizing reconfigurable sequential machines using tabular models;evaluation of a low-power reconfigurable DSP architecture;a reconfigurable hardware-monitor for communication analysis in distributed real-time systems;a mathematical benefit analysis of context switching reconfigurable computing;a configurable computing approach towards real-time target tracking;hardware reconfigurable neural networks;a simulator for the reconfigurable mesh architecture;processor architectures for circuit emulation;an empirical comparison of runtime systems for conservative parallel simulation;synchronizing operations on multiple objects;migration and rollback transparency for arbitrary distributed applications in workstation clusters;a topology based approach to coordinated multicast operations;a parallel evolutionary algorithm for the vehicle routing problem with heterogeneous fleet;artificial neural networks on reconfigurable meshes;a molecular quasi-random model of computations applied to evaluate collective intelligence;replicated shared object model for edge detection with spiral architecture and scheduling tasks of a parallel program in two-processor systems with use of cellular automata.

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the DASH Prototype: Implementation and performance 98

The DASH Prototype: Implementation and Performance

引用

25th International symposium on computer architecture, ISCA 1998

作者： Lenoski, Daniel Laudon, James Joe, Truman Nakahira, David Stevens, Luis Gupta, Anoop Hennessy, John Computer Systems Laboratory Stanford University CA94305 United States

ISBN: (纸本)9781581130584

the fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. While paper studies and software sirnulators are useful for understanding many high-level design tradeoffs, prototypes are essential to ensure that no critical details are overlooked. A prototype provides convincing evidence of the feasibility of the design allows one to accurately estimate both the hardware and the complexity cost of various features. and provides a platform for studying real workloads. A 16-processor prototype of the DASH multiprocessor has been operational for the last six months. In this paper, the hardware overhead of directory-based cache coherence in the prototype is examined. We also discuss the performance of the system. and the speedups obtained by parallel applications running on the prototype. Using a sophisticated harclwere performance monitor, we characterize the effectiveness of coherent caches and the relationship between an application's reference behavior and its speedup. © 1998 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： Cache memory

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HPSm, a high performance Restricted Data Flow architecture Having Minimal Functionality 98

HPSm, a High Performance Restricted Data Flow Architecture H...

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25th International symposium on computer architecture, ISCA 1998

作者： Hwu, Wen-Mei Patt, Yale N. Computer Science Division University of California Berkeley BerkeleyCA94720 United States

ISBN: (纸本)9781581130584

Our recent work in microarchitecture has identified a new model of execution, restricted data Bow, in which data flow techniques are used to coordinate out-of-order execution of sequential instruction streams. We believe that the restricted data flow model has great potential for implementing very high performance computing engines. this paper defines a minimal functionality variant of our model, which we are calling HPSm. the instruction set, data path, timing and control of HPSm are all described. A simulator for HPSm has been written, and some of the Berkeley RISC benchmarks have been executed on the simulator. We report the measurements obtained from these benchmarks, along with the measurements obtained for the Berkeley RISC II. the resulb are encouraging. © 1998 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： Data flow analysis

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IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors 98

IMPACT: An Architectural Framework for Multiple-Instruction-...

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25th International symposium on computer architecture, ISCA 1998

作者： Chang, Pohua P. Mahlke, Scott A. Chen, William Y. Warter, Nancy J. Hwu, Wen-Mei W. Center for Reliable and High-Performance Computing Universrty of Illinois UrbanaIL61801 United States

ISBN: (纸本)9781581130584

the performance of multiple-instruction-issue processors can be severely limited by the compiler's ability to generate efficient code for concurrent hardware. In the Ihf- PACT project, we have developed IMPACT-I, a highly optimizing C compiler Lo exploit instruction level concurrency. the optimization capabiiities of the IMPACT-I C: compiler are summarized in this paper. Using the IMPACT-I C compiler, we ran experiments to analyze the performance of multiple-instruction-issue processors executing some important non-numerical programs. the multiple-instruction-issue procuurors achieve solid speedup over high-performance single-instruction-issue processors. We ran experiments to characterize the following archirectural design issues: code scheduling model, instruction issue rate. memory load latency, and function unit resource limitations. Based on the experimental results, we propo5e the IMPACT Architectural Framework, a set of architectural features that best support the IMPACT-I C compiler to generate efficiettt code for multiple-instructionissue processors. By supporting these architectural features, multiple-instruction-issue implementations of existing and new architectures receive immediat.e compilation support from the IMPACT-I C compiler. © 1998 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： Program compilers

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Proceedings - 11th Brazilian symposium on Integrated Circuit Design, SBCCI 1998

Proceedings - 11th Brazilian Symposium on Integrated Circuit...

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11th Brazilian symposium on Integrated Circuit Design, SBCCI 1998

ISBN: (纸本)0818687045

the proceedings contain 52 papers. the topics discussed include: reconfigurable hardware for tomographic processing;microelectronics education using WWW and CAD tools;implementation of an edge detection algorithm in a reconfigurable computing system;automatic synthesis of hashing function circuits using evolutionary techniques;synthesis tools and design environment for dynamically reconfigurable FPGAs;generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault model;exploring concurrency in data path functional units BIST plan optimization: a study-case;integrated CMOS linear dosimeters;a physical layer controller for wireless infrared networks;a temporal logic for data-flow VHDL;formal verification of VHDL - the model checker CV;formalization of finite state machines with data path for the verification of high-level synthesis;VHDL models for high level synthesis of fuzzy logic controllers;a CO-synthesis approach based on symbolic reachability analysis;synthesis of CMOS operational amplifiers through genetic algorithms;MorphoSys: a reconfigurable architecture for multimedia applications;designing the dispatch stage of a superscalar microprocessor;a high-performance switching element for a multistage interconnection network;and a two-level pipelined implementation of the IDEA cryptographic algorithm.

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New techniques for deterministic test pattern generation

New techniques for deterministic test pattern generation

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VLSI Test symposium

作者： I. Hamzaoglu J. H. Patel Center for Reliable & High Performance Computing University of Illinois Urbana IL USA

this paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. these techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. this is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an ATPG system for combinational circuits, called ATOM. the performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance.

关键词： Test pattern generators Circuit testing Circuit faults Object oriented modeling System testing Combinational circuits Very large scale integration Automatic test pattern generation Computational efficiency Signal generators

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A FPGA based Forth microprocessor

A FPGA based Forth microprocessor

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IEEE symposium on FPGAs for Custom computing Machines

作者： P.H.W. Leong P.K. Tsang T.K. Lee Department of Computer Science and Engineering Chinese University of Hong Kong New Territories Hong Kong China

Systems which employ a microprocessor together with an application specific FPGA based coprocessor are common today. these applications can reduce power consumption and system costs by incorporating the microprocessor in the FPGA. For such applications, a microprocessor which has good performance, occupies a minimal amount of FPGA resources, has a good high level language software development environment and good code density is desirable. In this paper a 16 bit FPGA based microprocessor, called MSL16, optimised for such applications is described. MSL16 utilises a stack architecture with each instruction occupying only 4 bits, leading to a small instruction set, simple datapath and control, and high code density. MSL16 was specifically designed to efficiently execute the programming language "Forth". the Forth language has the desirable features of portability and high code density, and it is well suited to control, DSP, real-time and embedded applications.

关键词： Field programmable gate arrays Microprocessors Application software Coprocessors Energy consumption Costs high level languages Programming computer architecture computer languages

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Integrated predicated and speculative execution in the IMPACT EPIC architecture

Integrated predicated and speculative execution in the IMPAC...

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Annual International symposium on computer architecture, ISCA

作者： D.I. August D.A. Connors S.A. Mahlke J.W. Sias K.M. Crozier Ben-Chung Cheng P.R. Eaton Q.B. Olaniran W.-M. W. Hwu Center for Reliable and High Performance Computing University of Illinois Urbana-Champaign IL USA Hewlett Packard Laboratories Hewlett Packard Company Palo Alto CA USA

Explicitly Parallel Instruction computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques which enable the compiler to represent control speculation, data dependence speculation, and predication have individually been shown to be very effective. However these techniques have not been studied in combination with each other. this paper presents the IMPACT EPIC architecture to address the issues involved in designing processors based on these EPIC concepts. In particular we focus on new execution and recovery models in which microarchitectural support for predicated execution is also used to enable efficient recovery from exceptions caused by speculatively executed instructions. this paper demonstrates that a coherent framework to integrate the three techniques can be elegantly designed to achieve much better performance than each individual technique could alone provide.

关键词： computer architecture Costs Hardware Microprocessors Parallel processing Registers computer aided instruction Laboratories Electronic switching systems Process design

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Design choices in the SHRIMP system: an empirical study

Design choices in the SHRIMP system: an empirical study

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Annual International symposium on computer architecture, ISCA

作者： M.A. Blumrich R.D. Alpert Yuqun Chen D.W. Clark S.M. Damianakis C. Dubnicki E.W. Felten L. Iftode K. Li M. Martonosi R.A. Shillner Department of Computer Science Princeton University Princeton NJ USA

the SHRIMP cluster-computing system has progressed to a point of relative maturity; a variety of applications are running on a 16-node system. We have enough experience to understand what we did right and wrong in designing and building the system. In this paper we discuss some of the lessons we learned about computer architecture, and about the challenges involved in building a significant working system in an academic research environment. We evaluate significant design choices by modifying the network interface firmware and the system software in order to empirically compare our design to other approaches.

关键词： Network interfaces Application software computer architecture Protection computer science Hardware Software performance Electrical capacitance tomography Ear Environmental economics

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Options for dynamic address translation in COMAs

Options for dynamic address translation in COMAs

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Annual International symposium on computer architecture, ISCA

作者： Xiaogang Qiu M. Dubois Department of Electrical Engineering-Systems University of Southern California Los Angeles CA USA

In modern processors, the dynamic translation of virtual addresses to support virtual memory is done before or in parallel with the first-level cache access. As processor technology improves at a rapid pace and the working sets of new applications grow insatiably the latency and bandwidth demands on the TLB (Translation Lookaside Buffer) are getting more and more difficult to meet. the situation is worse in multiprocessor systems, which run larger applications and are plagued by the TLB consistency problem. We evaluate and compare five options for virtual address translation in the context of COMAs (Cache Only Memory architectures). the dynamic address translation mechanism can be located after the cache access provided the cache is virtual. In a particular design, which we call V-COMA for Virtual COMA, the physical address concept and the traditional TLB are eliminated. While still supporting virtual memory, V-COMA reduces the address translation overhead to a minimum. V-COMA scales well and works better in systems with large number of processors. As a machine running on virtual addresses, V-COMA provides a simple and consistent hardware model to the operating system and the compiler, in which further optimization opportunities are possible.

关键词： Concurrent computing computer architecture computer languages Memory management high performance computing Writing performance evaluation Computational modeling computer simulation Predictive models

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