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A Vision Based Method for Real-Time Respiration Rate Estimation Using a Recursive Fourier Analysis

A Vision Based Method for Real-Time Respiration Rate Estimat...

引用

IEEE symposium on Bioinformatics and Bioengineering (BIBE)

作者： Avishek Chatterjee A. P. Prathosh Pragathi Praveena Vidyadhar Upadhya Xerox Research Centre India Bengaluru India Xerox Res. Centre India Bangalore India Indian Institute of Science Bengaluru India

In this paper, we propose a simple yet effective, computer vision based method for estimating respiration rate in real-time from the thoraco-abdominal video of a subject being monitored. the periodic motion of the chest wall of the subject is captured through the optical flow in the video sequence. the frequency of the chest wall motion is estimated by performing a Fourier analysis on the time sequence of the optical flow vectors. We present how to perform the Fourier analysis recursively leveraging the sequential nature of a video to speed-up our method. Unlike other methods, our method does not require a selection of region of interest because our method aggregates out-of-phase optical flows by factoring out the their relative phase differences. Unlike many existing methods, our method does not require to be reinitialized if the subject changes the posture during the observation. Our method works with different postures and different views (frontal, side, etc.) of the subject. Our method is very simple to implement. We evaluate our method against an impedance pneumograph and demonstrate the high accuracy of our method on thoracoabdominal videos of many subjects wearing a wide variety of clothing.

关键词： Optical filters Estimation Face Monitoring Optical sensors Optical computing computer vision

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A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files

A Compiler Back-End for Reconfigurable, Mixed-ISA Processors...

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IEEE International symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Timo Stripf Ralf Koenig Patrick Rieder Juergen Becker Karlsruhe Institute of Technology Karlsruhe Germany

Reconfigurable tile-based architectures can dynamically interconnect several tiles in order to establish processor instances with varying resource, performance, and energy characteristics at run time. these flexible processor instances offer a new degree of freedom for adapting to changing applications' requirements while optimizing resource and energy consumption. Our solution for dynamic interconnection of tiles requires a flexible Run-Time Scalable Issue-Width (RSIW) Instruction Set architecture (ISA) that changes dependent on the configuration. In order to enable high-level programmability of our architecture in C/C++ a novel compiler back-end is needed. In this paper we address this necessity by presenting a novel LLVM compiler back-end targeting the reconfigurable RSIW ISA and supporting mixed-ISA software development. RSIW is comparable to clustered-VLIW ISAs since it expresses parallel operations within the ISA and explicitly uses clustered register files. therefore, we extended our architecture description language based RISC LLVM back-end by representations of parallel operations as well as compilation passes for clustering and scheduling of parallel operations as well as mixed-ISA code generation. Based on the novel back-end we compare the performance characteristics of several applications compiled for and simulated on different configurations. Additionally, we demonstrate resource-aware reconfiguration by a mixed-ISA application scenario.

关键词： Registers computer architecture Resource management Hazards Reduced instruction set computing Clustering algorithms

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Sub-Nyquist rate wideband spectrum sensing over TV white space for M2M communications

Sub-Nyquist rate wideband spectrum sensing over TV white spa...

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IEEE International symposium on World of Wireless Mobile and Multimedia Networks (WoWMoM)

作者： Yuan Ma Yue Gao Clive G. Parini Queen Mary University of London School of Electronic Engineering and Computer Science London United Kingdom

Secondary operation in TV White Space (TVWS) calls for fast and accurate spectrum sensing over a wide bandwidth, which challenges the traditional spectrum sensing methods operating at or above Nyquist rate. Sub-Nyquist sampling has attracted significant interests for wideband spectrum sensing, while existing algorithms can only work for sparse spectrum with high computation and hardware complexity. In this paper, we propose a novel sub-Nyquist wideband sensing algorithm that can work for the non-sparse spectrum without sampling at full bandwidth through the use of multiple low-speed Analog-to-Digital Converters (ADCs) based on sparse Fast Fourier Transform (sFFT). the proposed permutation and filtering algorithm achieves the wideband sensing regardless of signal sparsity with low hardware complexity. In contrast to existing sub-Nyquist approaches, the proposed wideband sensing algorithm subsamples the wideband signal, and then directly estimates its frequency spectrum. the mathematical model of the proposed sub-Nyquist wideband sensing algorithm is derived and verified by numerical analysis over TVWS signals. the proposed algorithm shows considerable detection performance on wideband signals as well as reduces the runtime and implementation complexity in comparison with conventional wideband sensing algorithm.

关键词： Wideband TV Complexity theory Frequency conversion

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Research on User Interface Transformation Method Based On MDA

Research on User Interface Transformation Method Based On MD...

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2017 16th International symposium on Distributed computing and Applications to Business,Engineering and Science（DCABES 2017）

作者： Gao Miao Liu Hongxing Lin Juncai Xie Songyu School of Computer Science and Technology Wuhan University of Technology

the user interface development method based on model driven architecture can effectively solve the problem that different platform-specific user interfaces have to be developed for the same application when the application needs to run on different *** method firstly designs the platform-independent model(PIM) of the user interface,then transforms the PIM into a variety of mainstream platform-specific model(PSM) automatically or semi-automatically,and finally transforms the PSM to a platform specific *** user interface transformation method from PIM to PSM is presented in this ***,a user interface PSM meta-model is ***,the mapping rules of PIM elements to PSM elements are defined in the meta-model level,and the transformation algorithm from PIM to PSM is *** verify the effectiveness of the method,we implemented a user interface software development tool which supports the transformation from PIM to PSM based on EMF and GMF.

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DataCat: Attention-based Open Government Data (OGD) Category Recommendation Framework

DataCat: Attention-based Open Government Data (OGD) Category...

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International Joint symposium on Artificial Intelligence and Natural Language Processing (iSAI-NLP)

作者： Natnaree Sornkongdang Nuttapong Sanglerdsinlapachai Chutiporn Anutariya Asian Institute of Technology Thailand National Electronics and Computer Technology Center Thailand

ISBN: (纸本)9781665409483

A data category recommendation framework for thailand’s open government data portal (thOGD) is proposed to assist data providers when publishing and registering a new dataset into the portal’s data catalog. However, existing approaches such as a multi-label classification problem, have not adopted the semantic features of data categories sufficiently. Deep learning model for Natural Language Processing has recently demonstrated to achieve high potential in learning the different degrees of semantic feature abstraction because all layers of multi-head attention blocks are provided with different fragments of metadata descriptions and corresponding tags. To obtain a robust recommendation result, this paper proposes DataCat: a Category Recommendation Framework using the attention-based framework through the thOGD portal. Within this framework, the integrated multi-layers with particular semantic information are directly attached to the output layer of a network to enhance the effectiveness of information retrieval. the results point out that the attention-based framework has a weighted effect on loss of optimization. the performance when looking at the macro average of precision and F1-score improves by 0.664% and 0.557%, respectively. the micro average of those improves by 0.806%, and 0.698%, respectively.

关键词： Deep learning Publishing Semantics Government Metadata Information retrieval Natural language processing

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Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGPU architectures

Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGP...

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International symposium on Quality Electronic Design

作者： Venkata Yaswanth Raparti Sudeep Pasricha Department of Electrical and Computer Engineering Colorado State University

ISBN: (纸本)9781509012145

the growing parallelism in most of today's applications has led to an increased demand for parallel computing in processors. General Purpose Graphics Processing Units (GPGPUs) have been used extensively to provide the necessary computation for highly parallel applications. GPGPUs generate huge volumes of network traffic between memory controllers (MCs) and cores. As a result, the network-on-chip (NoC) fabric can become a performance bottleneck, especially for memory intensive applications on GPGPUs. Traditional mesh-based NoC topologies are not suitable for GPGPUs as they possess high network latency that leads to congestion at MCs and an increase in application execution time. In this paper, we propose a novel memory-aware circuit overlay NoC that exploits characteristics of traffic in GPGPUs to eliminate router arbitration at each hop. Our experimental results show that our approach yields an improvement of 40-75% in NoC latency, 20-70% in execution time, and 10-65% in overall energy consumption compared to the state-of-the-art.

关键词： Latency execution time Overlay network delay traffic network PARALLEL PROCESSING (computerS) energy consumption Memory Memory architecture MCS gene core Traffic

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P-SOCRATES: A Parallel Software Framework for Time-Critical Many-Core Systems

P-SOCRATES: A Parallel Software Framework for Time-Critical ...

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Euromicro symposium on Digital System Design

作者： Luis Miguel Pinho Eduardo Quiñones Marko Bertogna Andrea Marongiu Jorge Pereira Carlos Claudio Scordino Michele Ramponi ISEP Porto Portugal Barcelona Supercomputing Center Spain University of Modena Italy ETH Zurich Switzerland ATOS Spain Evidence Srl Italy Active Technologies Srl Ferrara Italy

the advent of next-generation many-core embedded platforms has the chance of intercepting a converging need for predictable high-performance coming from both the high-performance computing (HPC) and Embedded computing (EC) domains. On one side, new kinds of HPC applications are being required by markets needing huge amounts of information to be processed within a bounded amount of time. On the other side, EC systems are increasingly concerned with providing higher performance in real-time, challenging the performance capabilities of current architectures. this converging demand, however, raises the problem about how to guarantee timing requirements in presence of parallel execution. this paper presents the approach of project P-SOCRATES for the design of an integrated framework for the execution of workload-intensive applications with real-time requirements on top of next-generation commercial-off-the-shelf (COTS) platforms based on many-core accelerated architectures. the time-criticality and parallelisation challenges are addressed by merging techniques coming from both HPC and EC domains, identifying the main sources of indeterminism and proposing efficient mapping and scheduling algorithms, along with the associated timing and schedulability analysis, to guarantee the real-time and performance requirements of the applications.

关键词： Real-time systems Timing Hardware computer architecture Time factors Computational modeling Embedded computing

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Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless Environments

Mosaic: Harnessing the Micro-Architectural Resources of Serv...

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： Jovan Stojkovic Esha Choukse Enrique Saurez Íñigo Goiri Josep Torrellas University of Illinois at Urbana-Champaign Microsoft Azure Research - Systems

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

With serverless computing, users develop scalable applications using lightweight functions as building blocks, while cloud providers own most of the computing stack, allowing for better resource optimizations. In this paper, we observe that modern server-class processors are inefficiently utilized in serverless environments. Cores perform frequent context switches within function invocations and have a high degree of oversubscription. In such an environment, functions frequently lose their micro-architectural state in stateful hardware structures like caches, TLBs, and branch predictors, causing performance degradation. At the same time, modern processors are dimensioned for the needs of a broad set of applications, rendering them suboptimal for serverless workloads. Based on these insights, we propose Mosaic, an architecture optimized for serverless environments that maintains generality to efficiently support other workloads. Mosaic has two components: (1) MosaicCPU, a processor architecture that efficiently runs both serverless workloads and traditional monolithic applications, and (2) MosaicScheduler, a software stack for serverless systems that maximizes the benefits of MosaicCPU. MosaicCPU slices micro-architectural structures into small chunks and assigns tiles of such chunks to functions. the processor retains the state of functions in their tiles across context switches, thereby improving performance. Furthermore, currently-inactive tiles are set to a low power mode, thereby reducing energy consumption. In addition, MosaicScheduler maximizes efficiency by introducing predictive right-sizing of the per-function tiles, alongside with smart scheduling based on the state of the tiles. Overall, compared to conventional server-class processors, Mosaic improves the throughput of serverless workloads by 225% while using 22% less power.

关键词： Context Schedules Program processors Processor scheduling Full stack Serverless computing computer architecture throughput Rendering (computer graphics) Optimization

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Heterogeneous Multi-Functional Look-Up-Table-based Processing-in-Memory architecture for Deep Learning Acceleration

Heterogeneous Multi-Functional Look-Up-Table-based Processin...

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IEEE International symposium on Quality Electronic Design

作者： Sathwika Bavikadi Purab Ranjan Sutradhar Amlan Ganguly Sai Manoj Pudukotai Dinakarrao Department of Electrical and Computer Engineering George Mason University Fairfax VA USA Department of Computer Engineering Rochester Institute of Technology Rochester NY USA

Emerging applications including deep neural networks (DNNs) and convolutional neural networks (CNNs) employ massive amounts of data to perform computations and data analysis. Such applications often lead to resource constraints and impose large overheads in data movement between memory and compute units. Several architectures such as Processing-in-Memory (PIM) are introduced to alleviate the bandwidth bottlenecks and inefficiency of traditional computing architectures. However, the existing PIM architectures represent a trade-off between power, performance, area, energy efficiency, and programmability. To better achieve the energy-efficiency and flexibility criteria simultaneously in hardware accelerators, we introduce a multi-functional look-up-table (LUT)-based reconfigurable PIM architecture in this work. the proposed architecture is a many-core architecture, each core comprises processing elements (PEs), a stand-alone processor with programmable functional units built using high-speed reconfigurable LUTs. the proposed LUTs can perform various operations, including convolutional, pooling, and activation that are required for CNN acceleration. Additionally, the proposed LUTs are capable of providing multiple outputs relating to different functionalities simultaneously without the need to design different LUTs for different functionalities. this leads to optimized area and power overheads. Furthermore, we also design special-function LUTs, which can provide simultaneous outputs for multiplication and accumulation as well as special activation functions such as hyperbolics and sigmoids. We have evaluated various CNNs such as LeNet, AlexNet, and ResNet18,34,50. Our experimental results have demonstrated that when AlexNet is implemented on the proposed architecture shows a maximum of 200× higher energy efficiency and 1.5× higher throughput than a DRAM-based LUT-based PIM architecture.

关键词： Deep learning Neural networks computer architecture Programming throughput Energy efficiency Real-time systems

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Conjugate gradient sparse solvers: performance-power characteristics 06

Conjugate gradient sparse solvers: performance-power charact...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： K. Malkowski Ingyu Lee P. Raghavan M.J. Irwin Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

ISBN: (纸本)9781424400546

We characterize the performance and power attributes of the conjugate gradient (CG) sparse solver which is widely used in scientific applications. We use cycle-accurate simulations with SimpleScalar and Wattch, on a processor and memory architecture similar to the configuration of a node of the BlueGene/L. We first demonstrate that substantial power savings can be obtained without performance degradation if low power modes of caches can be utilized. We next show that if Dynamic Voltage Scaling (DVS) can be used, power and energy savings are possible, but these are realized only at the expense of performance penalties. We then consider two simple memory subsystem optimizations, namely memory and level-2 cache prefetching. We demonstrate that when DVS and low power modes of caches are used with these optimizations, performance can be improved significantly with reductions in power and energy. For example, execution time is reduced by 23%, power by 55% and energy by 65% in the final configuration at 500 MHz relative to the original at 1 GHz. We also use our codes and the CG NAS benchmark code to demonstrate that performance and power profiles can vary significantly depending on matrix properties and the level of code tuning. these results indicate that architectural evaluations can benefit if traditional benchmarks are augmented with codes more representative of tuned scientific applications.

关键词： Computational modeling Character generation Voltage control Application software Prefetching Degradation Dynamic voltage scaling high performance computing computer science Power engineering and energy

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