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A new token passing distributed mutual exclusion algorithm

A new token passing distributed mutual exclusion algorithm

引用

International Conference on Distributed computing Systems

作者： S. Banerjee P.K. Chrysanthis Telecommunications Program University of Pittsburgh Pittsburgh PA USA

Eliminating interference between concurrently executing activities through mutual exclusion is one of the most fundamental problems in computer systems. the problem of mutual exclusion in a distributed system is especially interesting owing to the lack of global knowledge in the presence of variable communication delays. In this paper, a new token-based distributed mutual exclusion algorithm is proposed. the algorithm incurs approximately three messages at high loads, irrespective of the number of nodes N in the system. At low loads, it requires approximately N messages. the paper also addresses failure recovery issues, such as token loss.

关键词： Delay Communication system control Interference elimination Concurrent computing Telecommunication computing Control systems Taxonomy System recovery performance analysis Analytical models

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Conservative garbage collection on distributed shared memory systems

Conservative garbage collection on distributed shared memory...

引用

International Conference on Distributed computing Systems

作者： Weimin Yu A. Cox Department of Computer Science Rice University Houston TX USA

In this paper we present the design and implementation of a conservative garbage collection algorithm for distributed shared memory (DSM) applications that use weakly-typed languages like C or C++, and evaluate its performance. In the absence of language support to identify references, our algorithm constructed a conservative approximation of the set of cross-node references based on local information only. It was also designed to tolerate memory inconsistency on DSM systems that use relaxed consistency protocols. these techniques enabled every node to perform garbage collections without communicating with others, effectively avoiding the high cost of cross-node communication in networks of workstations. We measured the performance of our garbage collector against explicit programmer management using three application programs. In two out of the three programs the performance of the GC version is within 15% of the explicit version. the results showed that the garbage collector has two effects on application programs. On one hand, it tends to reduce memory locality, increasing the communication cost; on the other hand, it may eliminate synchronization and memory accesses that would be incurred if memory were managed by the programmer reducing the communication cost.

关键词： Memory management Programming profession Algorithm design and analysis Costs Workstations computer science Automatic logic units Application software Approximation algorithms Protocols

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An adaptive job allocation method for multicomputer systems

An adaptive job allocation method for multicomputer systems

引用

International Conference on Distributed computing Systems

作者： Chung-Yen Chang P. Mohaptra Department of Electrical and Computer Engineering Iowa State University Ames IA USA Iowa State University Ames IA US Dept. of Electr. Eng. & Comput. Eng. Iowa State Univ. Ames IA USA

the fragmentation problem in multicomputer systems reduces the system utilization and prohibits the systems from performing at their full capacity. In this paper, we propose a generic job allocation method for multicomputer systems based on job size reduction. We reduce the subsystem size requirement adaptively according to the availability of processors. the fragmentation problem is greatly alleviated by this approach. To ensure that the benefit of reducing fragmentation is not outweighed by the penalty of executing jobs on less number of processors, we restrict the number of times the size of a job can be reduced; hence the name restricted size reduction (RSR). Extensive simulations are conducted to validate the RSR method for hypercubes and mesh-based systems with different allocation algorithms. It is observed in both mesh and hypercube that by using the RSR method a simple algorithm can provide better performance than the more sophisticated allocation algorithms. We have also compared RSR method with the limit allocation that is based on a similar idea. Our method outperforms the limit allocation and provides better fairness to different size jobs. the performance gain, fairness, and low complexity makes the RSR method highly attractive.

关键词： Topology Hypercubes performance gain Availability high performance computing Scheduling algorithm Processor scheduling System performance

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Preliminary insights on shared memory PIC code performance on the Convex Exemplar SPP1000

Preliminary insights on shared memory PIC code performance o...

引用

Frontiers of Massively Parallel Computation

作者： P. MacNeice C.M. Mobarry J. Crawford T.L. Sterling Goddard Space Flight Center Hughes STX Greenbelt MD USA Goddard Space Flight Center NASA USA USRA California Institute of Technology USA

We implement a 3D Electrostatic Particle in Cell (PIC) code on the HP-Convex Exemplar SPP1000. Our principal goals are to identify the best PIC algorithm for this architecture and capture its performance, and to explore whether the architecture and system software achieve an efficient and scalable shared memory programming environment. We show that PIC codes can achieve good performance on the Exemplar. However to achieve this performance great care is required in minimizing long latencies to remote memory and in maximizing cache reuse. Combined, these two requirements for avoiding performance degradation due to latency resulted in a complex programming task and diminished significantly many advantages that the shared memory hardware provided towards ease-of-use. Our best performing code avoided stressing the cache coherency hardware. Best performance was achieved by storing the particle data in 'processor local' memory blocks, and by intermittent sorting of the particle data to improve processor cache reuse.

关键词： Space technology computer architecture Electrostatics Plasma simulation high performance computing Concurrent computing NASA Software algorithms System software Programming environments

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Modeling and analysis of task migration in shared-memory multiprocessor computer systems

Modeling and analysis of task migration in shared-memory mul...

引用

International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： R.D. Nelson M.S. Squillante OTA Limited Partnership Purchase NY USA IBM Research Division IBM Thomas J. Watson Research Center Yorktown Heights NY USA

In this paper we study a tradeoff between keeping the system workload balanced and scheduling tasks where they run most efficiently in shared-memory multiprocessor commercial environments. We formulate a general model of receiver-initiated task migration and derive a mathematical analysis of the model. Our results yield insights and information that can be used to design and develop adaptive scheduling policies for high-performance computing and telecommunication systems.

关键词： Processor scheduling Mathematical model Mathematical analysis System performance Adaptive scheduling Telecommunication computing computer architecture Costs Multiprocessing systems

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the core Legion object model 96

The core Legion object model

引用

International symposium on high performance Distributed computing

作者： M. Lewis A. Grimshaw Department of Computer Science University of Virginia Charlottesville VA USA University of Virginia Charlottesville VA US Dept. of Comput. Sci. Virginia Univ. Charlottesville VA USA

ISBN: (纸本)9780818675829

the Legion project at the University of Virginia is an architecture for designing and building system services that provide the illusion of a single virtual machine to users, a virtual machine that provides secure shared object and shared name spaces, application adjustable fault tolerance, improved response time, and greater throughput. Legion targets wide area assemblies of workstations, supercomputers, and parallel supercomputers. Legion tackles problems not solved by existing workstation based parallel processing tools; the system will enable fault tolerance, wide area parallel processing, interoperability, heterogeneity, a single global name space, protection, security, efficient scheduling, and comprehensive resource management. the paper describes the core Legion object model, which specifies the composition and functionality of Legion's core objects-those objects that cooperate to create, locate, manage, and remove objects in the Legion system. the object model facilitates a flexible extensible implementation, provides a single global name space, grants site autonomy to participating organizations, and scales to millions of sites and trillions of objects.

关键词： Virtual machining Fault tolerant systems Workstations Supercomputers Parallel processing Buildings Delay throughput Assembly Protection

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Reducing the cost for non-blocking in atomic commitment

Reducing the cost for non-blocking in atomic commitment

引用

International Conference on Distributed computing Systems

作者： R. Guerraoui M. Larrea A. Schiper Dé partement dInformatique Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

Non-blocking atomic commitment protocols enable a decision (commit or abort) to be reached at every correct participant, despite the failure of others. the cost for non-blocking implies however (1) a high number of messages and communication steps required to reach commit, and (2) a complicated termination protocol needed in the case of failure suspicions. In this paper, we present a non-blocking protocol, called MDSPC (Modular and Decentralized three Phase Commit), which enables to trade resiliency against efficiency. As conveyed by our performance measures, MDSPC is faster than existing non-blocking protocols, and in the case of a broadcast network and a reasonable resiliency rate (e.g. 2 or 3) is almost as efficient as the classical (blocking) 2PC. the termination protocol of MDSPC is encapsulated inside a majority consensus protocol. this modularity leads to a simple structure of MDSPC and enables a precise characterization of its liveness in an asynchronous system with an unreliable failure detector.

关键词： Costs Protocols Broadcasting computer crashes Delay Detectors Contracts Nominations and elections

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Hierarchical processors-and-memory architecture for high performance computing

Hierarchical processors-and-memory architecture for high per...

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Frontiers of Massively Parallel Computation

作者： Z.B. Miled R. Eigenmann J.A.B. Fortes V. Taylor School of ECE Purdue University West Lafayette IN USA Department of EECS Northwestern University Evanston IL USA

this paper outlines a cost-effective multiprocessor architecture that takes into consideration the importance of hardware and software costs as well as delivered performance in the context of real applications. the proposed architecture, HPAM, is organized as a hierarchy of processors-and-memory subsystems. Each subsystem contains a homogeneous parallel machine. Across the levels of the hierarchy, processor speeds and interconnection technology vary. the HPAM design is driven by several considerations: the observed characteristics of real applications, cost-efficiency considerations and the need for ease-of-usage. Rationales and the results of a preliminary study that motivated the design of this architecture are presented. these results include benchmark data that expose the advantages of HPAM over other architectures. Technology trends that support the desirability and viability of the proposed machine organization are also presented. Two classes of applications that demand 100 Teraops computation rates and that will drive future HPAM work are discussed. Furthermore a flexible software environment is proposed for this architecture, which facilitates several programming scenarios: automatic program translation, library based programming and performance-guided coding by expert programmers.

关键词： computer architecture Software performance Application software Automatic programming Hardware Costs Parallel machines Drives Software libraries Programming profession

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Simulation of heterogeneous networks of workstations

Simulation of heterogeneous networks of workstations

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International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Zhichen Xu Computer Sciences Department University of Wisconsin Madison Madison WI USA

ISBN: (纸本)0818672358

A network of workstations (NOW) has become an important distributed platform for large-scale scientific computations. A practical NOW system is heterogeneous and nondedicated, where computing power varies among the workstations and multiple jobs may interact with each other during execution. I present the design and implementation of a simulation system for a nondedicated heterogeneous NOW. this simulator provides many options to users to specify and quantify system architectures, network heterogeneity and time-sharing factors, such as speeds of different processors, memory organizations, network topology, communication structures, and workload distributions. the simulator also supports execution of message-passing parallel programs written in C and the PVM library. the software structure of the simulator is well-modularized and highly extensible, which makes it easy to integrate other existing processor, memory and network simulators.

关键词： Workstations Computational modeling Distributed computing computer networks Time sharing computer systems computer architecture Network topology Software libraries high performance computing Scheduling

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A PC based digital pulse processor

A PC based digital pulse processor

引用

IEEE symposium on Nuclear Science (NSS/MIC)

作者： J. Basilio Simoes J. Landeck J.M.R. Cardoso C.F.M. Loureiro J.L. Malaquias C.M.B.A. Correia Physics Department University of Coimbra Coimbra Portugal

this is the second of two papers concerning the architecture, circuitry design and performance of a pulse processing station. this multifunction system, hosted on a personal computer's ISA bus, incorporates a high performance pulse height analyser, a multichannel scaler and a digital pulse processor. this paper focus on this last operation mode. the digital pulse processor is mainly based on a floating point digital signal processor, TMS320C31, on a 100 MSPS dash ADC, AD9012, and on a trigger and pulse locator mechanism based on a 16-bit counter synchronized with the sample clock. the preamplifier output is directly sampled and digitized and the incoming pulses are processed in real-time with reduced dead time. the implementation of the pulse processor is discussed and some preliminary results obtained with a HPGe detector are presented. the system is fully controlled by a Windows 95/NT user friendly software package built around the client-server model. It enables remote data assessment and system configuration in a network environment.

关键词： computer architecture Pulse circuits high performance computing Instruction sets performance analysis Digital signal processors Counting circuits Synchronization Clocks Preamplifiers

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