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Modeling and analysis of task migration in shared-memory multiprocessor computer systems

Modeling and analysis of task migration in shared-memory mul...

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International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： R.D. Nelson M.S. Squillante OTA Limited Partnership Purchase NY USA IBM Research Division IBM Thomas J. Watson Research Center Yorktown Heights NY USA

In this paper we study a tradeoff between keeping the system workload balanced and scheduling tasks where they run most efficiently in shared-memory multiprocessor commercial environments. We formulate a general model of receiver-initiated task migration and derive a mathematical analysis of the model. Our results yield insights and information that can be used to design and develop adaptive scheduling policies for high-performance computing and telecommunication systems.

关键词： Processor scheduling Mathematical model Mathematical analysis System performance Adaptive scheduling Telecommunication computing computer architecture Costs Multiprocessing systems

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the core Legion object model 96

The core Legion object model

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International symposium on high performance Distributed computing

作者： M. Lewis A. Grimshaw Department of Computer Science University of Virginia Charlottesville VA USA University of Virginia Charlottesville VA US Dept. of Comput. Sci. Virginia Univ. Charlottesville VA USA

ISBN: (纸本)9780818675829

the Legion project at the University of Virginia is an architecture for designing and building system services that provide the illusion of a single virtual machine to users, a virtual machine that provides secure shared object and shared name spaces, application adjustable fault tolerance, improved response time, and greater throughput. Legion targets wide area assemblies of workstations, supercomputers, and parallel supercomputers. Legion tackles problems not solved by existing workstation based parallel processing tools; the system will enable fault tolerance, wide area parallel processing, interoperability, heterogeneity, a single global name space, protection, security, efficient scheduling, and comprehensive resource management. the paper describes the core Legion object model, which specifies the composition and functionality of Legion's core objects-those objects that cooperate to create, locate, manage, and remove objects in the Legion system. the object model facilitates a flexible extensible implementation, provides a single global name space, grants site autonomy to participating organizations, and scales to millions of sites and trillions of objects.

关键词： Virtual machining Fault tolerant systems Workstations Supercomputers Parallel processing Buildings Delay throughput Assembly Protection

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Reducing the cost for non-blocking in atomic commitment

Reducing the cost for non-blocking in atomic commitment

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International Conference on Distributed computing Systems

作者： R. Guerraoui M. Larrea A. Schiper Dé partement dInformatique Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

Non-blocking atomic commitment protocols enable a decision (commit or abort) to be reached at every correct participant, despite the failure of others. the cost for non-blocking implies however (1) a high number of messages and communication steps required to reach commit, and (2) a complicated termination protocol needed in the case of failure suspicions. In this paper, we present a non-blocking protocol, called MDSPC (Modular and Decentralized three Phase Commit), which enables to trade resiliency against efficiency. As conveyed by our performance measures, MDSPC is faster than existing non-blocking protocols, and in the case of a broadcast network and a reasonable resiliency rate (e.g. 2 or 3) is almost as efficient as the classical (blocking) 2PC. the termination protocol of MDSPC is encapsulated inside a majority consensus protocol. this modularity leads to a simple structure of MDSPC and enables a precise characterization of its liveness in an asynchronous system with an unreliable failure detector.

关键词： Costs Protocols Broadcasting computer crashes Delay Detectors Contracts Nominations and elections

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Hierarchical processors-and-memory architecture for high performance computing

Hierarchical processors-and-memory architecture for high per...

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Frontiers of Massively Parallel Computation

作者： Z.B. Miled R. Eigenmann J.A.B. Fortes V. Taylor School of ECE Purdue University West Lafayette IN USA Department of EECS Northwestern University Evanston IL USA

this paper outlines a cost-effective multiprocessor architecture that takes into consideration the importance of hardware and software costs as well as delivered performance in the context of real applications. the proposed architecture, HPAM, is organized as a hierarchy of processors-and-memory subsystems. Each subsystem contains a homogeneous parallel machine. Across the levels of the hierarchy, processor speeds and interconnection technology vary. the HPAM design is driven by several considerations: the observed characteristics of real applications, cost-efficiency considerations and the need for ease-of-usage. Rationales and the results of a preliminary study that motivated the design of this architecture are presented. these results include benchmark data that expose the advantages of HPAM over other architectures. Technology trends that support the desirability and viability of the proposed machine organization are also presented. Two classes of applications that demand 100 Teraops computation rates and that will drive future HPAM work are discussed. Furthermore a flexible software environment is proposed for this architecture, which facilitates several programming scenarios: automatic program translation, library based programming and performance-guided coding by expert programmers.

关键词： computer architecture Software performance Application software Automatic programming Hardware Costs Parallel machines Drives Software libraries Programming profession

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Simulation of heterogeneous networks of workstations

Simulation of heterogeneous networks of workstations

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International symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Zhichen Xu Computer Sciences Department University of Wisconsin Madison Madison WI USA

ISBN: (纸本)0818672358

A network of workstations (NOW) has become an important distributed platform for large-scale scientific computations. A practical NOW system is heterogeneous and nondedicated, where computing power varies among the workstations and multiple jobs may interact with each other during execution. I present the design and implementation of a simulation system for a nondedicated heterogeneous NOW. this simulator provides many options to users to specify and quantify system architectures, network heterogeneity and time-sharing factors, such as speeds of different processors, memory organizations, network topology, communication structures, and workload distributions. the simulator also supports execution of message-passing parallel programs written in C and the PVM library. the software structure of the simulator is well-modularized and highly extensible, which makes it easy to integrate other existing processor, memory and network simulators.

关键词： Workstations Computational modeling Distributed computing computer networks Time sharing computer systems computer architecture Network topology Software libraries high performance computing Scheduling

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A PC based digital pulse processor

A PC based digital pulse processor

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IEEE symposium on Nuclear Science (NSS/MIC)

作者： J. Basilio Simoes J. Landeck J.M.R. Cardoso C.F.M. Loureiro J.L. Malaquias C.M.B.A. Correia Physics Department University of Coimbra Coimbra Portugal

this is the second of two papers concerning the architecture, circuitry design and performance of a pulse processing station. this multifunction system, hosted on a personal computer's ISA bus, incorporates a high performance pulse height analyser, a multichannel scaler and a digital pulse processor. this paper focus on this last operation mode. the digital pulse processor is mainly based on a floating point digital signal processor, TMS320C31, on a 100 MSPS dash ADC, AD9012, and on a trigger and pulse locator mechanism based on a 16-bit counter synchronized with the sample clock. the preamplifier output is directly sampled and digitized and the incoming pulses are processed in real-time with reduced dead time. the implementation of the pulse processor is discussed and some preliminary results obtained with a HPGe detector are presented. the system is fully controlled by a Windows 95/NT user friendly software package built around the client-server model. It enables remote data assessment and system configuration in a network environment.

关键词： computer architecture Pulse circuits high performance computing Instruction sets performance analysis Digital signal processors Counting circuits Synchronization Clocks Preamplifiers

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Architectural simulation system for M.f.a.s.t

Architectural simulation system for M.f.a.s.t

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Annual symposium on Simulation

作者： C.H.L. Moller G.G. Pechanek Microelectronics Division IBM Research Triangle Park NC USA

the paper discusses the simulation system used to verify the architecture of the Mwave folded array signal transform (M.f.a.s.t.) processor, a single chip scalable very long instruction word (VLIW) processor array being developed by IBM Microelectronics. M.f.a.s.t. simulation, at this stage of development of the architecture, is at a very high abstract level and is intended to meet the requirements of being implementation independent and permit investigation of the architecture itself, as opposed to simply verifying the congruence of the architecture and an implementation of it. the M.f.a.s.t. simulator uses a collection of functional models, implemented in C, to represent the M.f.a.s.t. architecture. the models, each reflecting the behaviour of a component of the architecture, run as independent processes and communicate among themselves using a socket mechanism. this paper discusses the merits and mechanics of this approach, and the reasons it was adopted. Two large applications and many small test cases have been written for the M.f.a.s.t. architecture and run on the M.f.a.s.t simulator. While it is difficult, for reasons that are discussed, to make easily interpretable statements about the performance of the simulator, data from these examples indicate that the simulator will emulate the execution, under average conditions, of approximately 3000 execution-unit operations per second.

关键词： Parallel processing Computational modeling VLIW Microelectronics Testing Digital signal processing Video compression computer aided instruction Concurrent computing computer architecture

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Dynamic scheduling strategies for shared-memory multiprocessors

Dynamic scheduling strategies for shared-memory multiprocess...

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International Conference on Distributed computing Systems

作者： B. Hamidzadeh D.J. Lilja Department of Computer Science University of Science and Technology (HKUST) Hong Kong China Department of Electrical Engineering University of Minnesota Minneapolis MN USA

Efficiently scheduling parallel tasks on to the processors of a shared-memory multiprocessor is critical to achieving high performance. Given perfect information at compile-time, a static scheduling strategy can produce an assignment of tasks to processors that ideally balances the load among the processors while minimizing the run-time scheduling overhead and the average memory referencing delay. Since perfect information is seldom available, however, dynamic scheduling strategies distribute the task assignment function to the processors by having idle processors allocate work to themselves from a shared queue. While this approach can improve the load balancing compared to static scheduling, the time required to access the shared work queue adds directly to the overall execution time. To overlap the time required to dynamically schedule tasks with the execution of the tasks, we examine a class of self-adjusting dynamic scheduling (SADS) algorithms that centralizes the assignment of tasks to processors. these algorithms dedicate a single processor of the multiprocessor to perform a novel on-line branch-and-bound technique that dynamically computes partial schedules based on the loads of the other processors and the memory locality (affinity) of the tasks and the processors. Our simulation results show that this centralized scheduling outperforms self-scheduling algorithms even when using only a small number of processors.

关键词： Dynamic scheduling Processor scheduling Optimal scheduling Scheduling algorithm Heuristic algorithms Runtime Multiprocessing systems Delay effects computer science Load management

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Achieving a balanced low-cost architecture for mass storage management through multiple fast Ethernet channels on the Beowulf parallel workstation

Achieving a balanced low-cost architecture for mass storage ...

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International symposium on Parallel Processing

作者： T. Sterling D.J. Becker M.R. Berry D. Savarese C. Reschke Center of Excellence in Space Data and Information Sciences NASA Goddard Space Flight Center Greenbelt MD USA Department of Computer Science University of Maryland College Park MD USA Department of Electrical Engineering and Computer Science George Washington University Washington D.C. DC USA

A network of workstations (NOW) seeks to leverage commercial workstation technology to produce high-performance computing systems at costs appreciably lower than parallel computers specifically designed for that purpose. the capabilities of technologies emerging from the PC commodity mass market are rapidly evolving to converge with those of workstations while at significantly lower cost. A new operating point in the price-performance design space of parallel system architecture may be derived through parallelism of PC subsystems. the "Pile-of-PCs" (PopC) approach is being explored through the Beowulf parallel workstation, developed to provide order-of-magnitude increases in disk capacity and bandwidth for a single-user environment at costs commensurate with conventional high-end workstations. this paper explores a critical aspect of the architecture trade-off space for Beowulf associated with the balance of parallel disk throughput and internal network bandwidth. the findings presented demonstrate that the parallel channels of a commodity 100 Mbps Ethernet are both necessary and sufficient to support the data rates of multiple concurrent file transfers on a 16-processor Beowulf parallel workstation.

关键词： Workstations Costs computer architecture computer networks Concurrent computing Space technology Bandwidth Parallel processing throughput Ethernet networks

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A low-complexity parallel system for gracious scalable performance. Case study for near PetaFLOPS computing

A low-complexity parallel system for gracious scalable perfo...

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Frontiers of Massively Parallel Computation

作者： S.G. Ziavras H. Grebel A. Chronopoulos Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ USA New Jersey Institute of Technology Newark NJ US Department of Computer Science Wayne State University Detroit MI USA

this paper presents a "point design" for an MIMD distributed shared-memory parallel computer capable of achieving gracious 100 TeraFLOPS performance with technology that will definitely become feasible/viable in less than a decade. Its scalability guarantees a lifetime extending well into the next century. the design takes advantage of free-space optical technologies, with simple guided-wave concepts, to produce a 1-D building block (BB) that implements efficiently a large, fully-connected system of processors. Designing fully-connected, large systems of electronic processors could be an immediate impact of optics on massively-parallel processing. A 2-D structure is proposed for the complete system, where the aforementioned 1-D BB is extended into two dimensions. this architecture behaves like a 2-D generalized hypercube, which is characterized by outstanding performance and extremely high wiring complexity that prohibits its electronic implementation. With readily available technology, a mesh of clear plastic bars in our design facilitate bit-parallel transmissions that utilize wavelength-division multiplexing and follow dedicated optical paths. Each processor is mounted on a card. Each card contains eight processors interconnected locally via an electronic crossbar. Taking advantage of higher-speed optical technologies all eight processors share the same interface to the optical medium. Encouraging, preliminary results prove that our conservative design could have a tremendous, positive impact on massively-parallel computing in the near future.

关键词： Optical design Optical interconnections Concurrent computing Distributed computing Scalability Process design Two dimensional displays Hypercubes Ultraviolet sources Wiring

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