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DeepWeed: A Dynamically Adaptive Lightweight Deep Learning Model for Efficient Weed Classification

DeepWeed: A Dynamically Adaptive Lightweight Deep Learning M...

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Innovation in Technology (ASIANCON), Asian Conference on

作者： Akshatha Prabhu Niranjan M Suraksha S Rai Department of Computer Science Amrita School of Computing Amrita Vishwa Vidyapeetham Mysuru India

ISBN: (数字)9798350354218

ISBN: (纸本)9798350354225

this work introduces DeepWeed, a lightweight deep-learning model inspired by the VGG16 architecture for image-based weed classification. Leveraging transfer learning and L2 regularization, DeepWeed aims to achieve high accuracy while maintaining computational efficiency. Our study evaluated the model’s performance on a dataset of five weed species. While an initial accuracy of 73.6% was achieved without data augmentation and L2 regularization, incorporating these techniques significantly improved, reaching an accuracy of 92.4 %. this increase highlights the effectiveness of data augmentation and L2 regularization in enhancing model performance. DeepWeed’s combination of high accuracy and computational efficiency suggests its potential as a practical tool for weed classification in agricultural applications, potentially contributing to improved farm management and reduced environmental impact.

关键词： Adaptation models Visualization Accuracy Computational modeling Transfer learning computer architecture Data augmentation Data models Computational efficiency Robots

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Artificial intelligence model for transformer fault diagnosis using a constructed database

Artificial intelligence model for transformer fault diagnosi...

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the 16th IET International Conference on AC and DC Power Transmission (ACDC 2020)

作者： L. Wang T. Littler X. Liu Queen’s University Belfast School of Electronics Electrical Engineering and Computer Science Belfast UK

high capital investment in critical assets, in particular power transformers requires application of incisive diagnostics to determine performance and identify potential issues which may impact long-term operation and maintenance. Asset failure and replacement represent a worst-case scenario which can be avoided. this paper proposes a model for accurate transformer fault diagnosis using artificial intelligence (AI) methods. In recent years, AI models have evolved for fault classification using Dissolved Gas Analysis (DGA) data. In common practice, most DGA data are collated but less often labelled, thus restricting the development of diagnostic models with different learning approaches. To overcome this and related limitations, this paper proposes a new hybrid DGA method for unlabelled data to extract information to build a diagnostic database. the method uses the Rogers Ratio and Duval Triangle Methods to identify early and premature fault onset. the method also supports common utility asset practices to reduce transformer management costs by minimising damage from unnecessary invasive maintenance. the paper provides a comparative study of artificial neural network (ANN), support vector machine (SVM), K-Nearest Neighbour (KNN) and decision tree models using the constructed database. Comparative results indicate a high level of diagnostic precision with approximately 99% accuracy for classification using a KNN-based model.

关键词： power engineering computing fault diagnosis power transformers artificial intelligence power system faults pattern classification data analysis database management systems

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On improving performance and energy profiles of sparse scientific applications 06

On improving performance and energy profiles of sparse scien...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： K. Malkowski Ingyu Lee P. Raghavan M.J. Irwin Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

ISBN: (纸本)9781424400546

In many scientific applications, the majority of the execution time is spent within a few basic sparse kernels such as sparse matrix vector multiplication (SMV). Such sparse kernels can utilize only a fraction of the available processing speed because of their relatively large number of data accesses per floating point operation, and limited data locality and data re-use. Algorithmic changes and tuning of codes through blocking and loop unrolling schemes can improve performance but such tuned versions are typically not available in benchmark suites such as the SPEC CFP 2000. In this paper, we consider sparse SMV kernels with different levels of tuning that are representative of this application space. We emulate certain memory subsystem optimizations using SimpleScalar and Wattch to evaluate improvements in performance and energy metrics. We also characterize how such an evaluation can be affected by the interplay between code tuning and memory subsystem optimizations. Our results indicate that the optimizations reduce execution time by over 40%, and the energy by over 85%, when used with power control modes of CPUs and caches. Furthermore, the relative impact of the same set of memory subsystem optimizations can vary significantly depending on the level of code tuning. Consequently, it may be appropriate to augment traditional benchmarks by tuned kernels typical of high performance sparse scientific codes to enable comprehensive evaluations of future systems.

关键词： Kernel Sparse matrices Application software computer architecture Computational modeling Power control Scientific computing Microprocessors computer science Power engineering and energy

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GLOBAL DETERMINISTIC AND STOCHASTIC OPTIMIZATION IN A SERVICE ORIENTED architecture 17

GLOBAL DETERMINISTIC AND STOCHASTIC OPTIMIZATION IN A SERVIC...

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Simulation Multiconference

作者： Chaitra Raghunath Tyler H. Chang Mohamed Jrad Rakesh K. Kapania Layne T. Watson Raymond M. Kolonay Dept. of Computer Science Virginia Polytechnic Institute & State University Dept. of Aerospace & Ocean Eng. Virginia Polytechnic Institute & State University Dept. of Computer Science Dept. of Mathematics Dept. of Aerospace & Ocean Eng. Virginia Polytechnic Institute & State University AFRL/RQVC

ISBN: (纸本)9781510838222

Service ORiented computing EnviRonment (SORCER) is a Java-based network-centric computing platform. SORCER provides a service oriented architecture, which enables the implementation of parallel algorithms in a dynamic distributed computing environment. SORCER is often used for multidisciplinary aircraft design analysis and optimization. However, the current approach often assigns intense optimization algorithms to run entirely on single overloaded nodes, rather than evenly distributing the workload. the goal of this work is to provide lower-level optimization algorithms as integrated SORCER services and study the overhead of doing so. VTDIRECT95, a Fortran 95 implementation of D. R. Jones' algorithm DIRECT, is a highly parallelizable derivative-free deterministic global optimization algorithm. QNSTOP is a parallel quasi-Newton algorithm for stochastic optimization problems. the potential benefit of integrating VTDIRECT95 and QNSTOP into the SORCER framework is to provide dynamic load balancing among computational resources at the optimization level, resulting in a dynamically scalable process.

关键词： Service-oriented computing Deterministic global optimization Stochastic optimization Multi-disciplinary design architecture Legal Services Optimization algorithms Service-oriented architecture Building construction Parallel algorithms network-centric computing multidisciplinary information Load balancing QNA

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Applied informatics: A paradigm shift in artificial embryonic systems development

Applied informatics: A paradigm shift in artificial embryoni...

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International symposium on Computational Intelligence and Informatics

作者： Szász Csaba Department of Electrical Machines and Drives Technical University of Cluj Cluj Romania

As it is well known, the synthesis of sophisticated cellular biology processes in artificial silicon structures is quoted as one of today's most highly ranked scientific challenges. However, the failure of most approaches which try to faithfully model cellular biology represents a major impediment which inhibits rapid progress in artificial biological structures development. In other words, the main obstacle seems to be the impossibility to full comprehend biological cell processes evolution and growth in their entirety and especially because of the lack of a precise and authentically models being to reproduce with high fidelity cellular and embryonic phenomena's. In an attempt to devise a model which more closely mimics cellular biology, this paper discusses an original artificial organism model, developed upon a two-layer coarse-fine-grid network approach. the strength of this approach is that it endeavors to capture the complexity of both the cellular networks as well as that of the biological cell itself, by implementing the internal biological phenomena of an organism into a two different network topology hardware layer. In essence, this model not only keeps the full advantages of previously created models that enable the implementation of similar self-replicating or self-repairing, abilities akin to those expressed by its cellular equivalents in nature, but there (according to the nature of cell biology) the inherent need of artificial cell structures to fulfill the entire role of a biological cell in the network is also expressed. At this stage of the research, the main goal it was to demonstrate that the chosen configuration operates correctly and supports the modeling assumptions. Not least of all, such architectures are suitable to deliver useful information about a wide range of imitated cellular processes in a short time and could become a helpful framework for researchers to confirm theoretical principles and experimental work quickly, with the full adv

关键词： Biological system modeling computer architecture Hardware Biological cells Microprocessors Complexity theory

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Multi-ALM: Run-time Multi-Level Reconfigurable Approximate Logarithmic Multiplier

Multi-ALM: Run-time Multi-Level Reconfigurable Approximate L...

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IEEE International symposium on Quality Electronic Design

作者： Maliha Tasnim Chinmay Raje Sheldon X.-D. Tan Electrical and Computer Engineering University of California at Riverside Riverside CA USA

ISBN: (数字)9798350309270

ISBN: (纸本)9798350309287

this paper presents a novel multi-level approximate logarithmic multiplier (ALM) named multi-ALM that offers dynamic run-time re-configurability for various precision, performance, and power requirements. While previous research on ALM designs has focused primarily on trade-offs between performance, energy, and accuracy during design time, our work addresses the critical need for dynamic re-configurability at run-time to enable efficient power, performance, and quality management at the architecture and algorithm levels. the proposed multi-ALM is based on an innovative iterative formulation of logarithmic multiplication, resulting in a Taylor series-like formula. this formulation facilitates straightforward trade-offs between multiplication accuracy and power consumption. We demonstrate that traditional ALMs can be considered level 1 ALMs within the multi-ALM framework. Furthermore, we introduce a new four-level ALM MAC array architecture design that enables run-time reconfigurable MAC (Multiply-Accumulate) computing with customizable accuracy and performance settings. this architecture empowers system designers to adapt the ALM functionality on-the-fly, tailoring it to the specific requirements of different applications and scenarios. Numerical results show that 8-bit two-level multi-ALM can achieve up to $17.22\times, 2.78\times $, and $1.37\times $ improvement in mean error, peak error, and power consumption respectively over the baseline $ALM$, while the area increases by $1.40\times $. 16-bit two-level multi-ALM can achieve up to $ 17.5\times$ and $ 2.75\times$ improvement in mean error and peak error over $ALM$. Furthermore, we evaluate the proposed multi-ALM design in several multiplication and accumulation (MAC) applications and discrete cosine transformation (DCT) application. the result shows that, multi-ALM can effectively trade-off performance such as throughput per unit of resource consumption to provide better accuracy of MAC computation, and quality o

关键词： Image segmentation Power demand Heuristic algorithms computer architecture throughput Hardware Iterative methods

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A Case Study on At-Speed Testing for a Gigahertz Microprocessor

A Case Study on At-Speed Testing for a Gigahertz Microproces...

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Da Wang Rui Li Yu Hu Huawei Li Xiaowei Li Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics Company Limited Shanghai China

this paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertz microprocessor with multi-clock domains. the presented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compression structure to reduce test data volume. It is difficult and time-consuming to generate at-speed tests for a design with embedded memories and multi-clock domains. the proposed test pattern generation scheme can gain transition fault coverage of approximately 83% for this high-performance microprocessor, and the test power consumption is well controlled.

关键词： Microprocessors Circuit testing Clocks Logic testing System testing Electronic equipment testing Test pattern generators Costs Circuit faults Energy consumption

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Ultrasound therapy system and ablation results utilizing miniature imaging/therapy arrays

Ultrasound therapy system and ablation results utilizing min...

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IEEE symposium (IUS) Ultrasonics

作者： P.G. Barthe M.H. Slayton P.M. Jaeger I.R.S. Makin L.A. Gallagher T.D. Mast M.M. Runk W. Faid Guided Therapy Systems Mesa AZ USA Ethicon Endo-Surgery Cincinnati OH USA

Array-based imaging and therapy systems have several advantages over single element approaches, and it was previously shown that the imaging and therapy functionality may be combined into dual-mode arrays. In this work, minimally invasive, miniature (2.2 mm /spl times/ 50 mm aperture, 3.3 mm diameter) dual-mode linear arrays have been developed into probes with high acoustic power output (100 W, and >120 W/cm/sup 2/ at the source), high transmit efficiency (>65% typical), and good imaging performance (3.4 MHz center frequency, 50% fractional bandwidth, >100 mm deep field of view). these therapy / imaging probes have been integrated into a flexible intense ultrasound surgery platform which also includes conventional diagnostic imaging probes. A system architecture has been developed which includes a 64-channel therapy driver with software selection of array aperture and phasing (1/16th wavelength), frequency (0.5-8 MHz), drive amplitude (5 W/channel, nominal), mechanical rotational steering (/spl plusmn/180 degrees), and temporal sequencing/switching of imaging, and therapy modes. the array-based imaging/therapy system has produced encouraging results in preclinical studies of bulk tissue ablation, imaging and treatment monitoring of liver in vitro and in vivo, examples of which are presented. the system can be applied to ablation of other soft tissue pathologies, e.g. kidney, heart, uterus, brain, GI, etc.

关键词： Ultrasonic imaging Medical treatment Acoustic imaging Probes Apertures Frequency Minimally invasive surgery Acoustic arrays Bandwidth computer architecture

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Short-Read Mapping by a Systolic Custom FPGA Computation

Short-Read Mapping by a Systolic Custom FPGA Computation

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： thomas B. Preuber Oliver Knodel Rainer G. Spallek Department of Computer Science Technische Universität Dresden Dresden Germany

the mapping of reads, i.e. short DNA base pair strings, to large genome databases has become a critical operation for genetic analysis and diagnosis. Although this mapping operation is a simple string search tolerant of some character mismatches, it is yet extremely challenging due to the tremendous size of the searched genome databases. It is the heavy use of search heuristics such as BLAST, Maq and Bowtie, which makes the economic deployment of read mappers possible. While these heuristics achieve feasible computation times, they also sacrifice the accuracy of the mapping results, which is itself a high value for reliable diagnostics. the traditional software implementations are unable to exploit the tremendous parallelism, which is available in the mapping of thousands and millions of reads. Merely a handful of concurrent control flows, and thus searches, can be performed efficiently on contemporary multicores. Even GPU assistance only enables a few dozens of parallel searches. this paper proposes a systolic custom computation on FPGA, which implements the read mapping on a massively parallel architecture. It implements a true search and guarantees to find all read mappings under a configurable threshold of base pair mismatches. the highly regular design from compact string matchers enables the implementation of thousands of parallel search engines on a single FPGA device. the presented map per platform combines highest computational performance with an excellent result accuracy. Its performance is more than twice as high as that of a recently published comparable FPGA map per. Already when implemented on a contemporary mid-size FPGA, it meets the search speed of software heuristics, which only detect little more than half of the valid read mappings. the map per easily scales to large FPGA devices, which can, thus, implement accurate high-performance volume mappers. Accurate mapping is made available in application domains that could only afford fuzzy heuristics

关键词： Databases Field programmable gate arrays Genomics Bioinformatics Concurrent computing Clocks Table lookup

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Integrated predicated and speculative execution in the IMPACT EPIC architecture 98

Integrated predicated and speculative execution in the IMPAC...

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Proceedings of the 25th annual international symposium on computer architecture

作者： David I. August Daniel A. Connors Scott A. Mahlke John W. Sias Kevin M. Crozier Ben-Chung Cheng Patrick R. Eaton Qudus B. Olaniran Wen-mei W. Hwu Center for Reliable and High-Performance Computing University of Illinois Urbana-Champaign IL Hewlett-Packard Laboratories Hewlett-Packard Palo Alto CA

ISBN: (纸本)9780818684913

Explicitly Parallel Instruction computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques which enable the compiler to represent control speculation, data dependence speculation, and predication have individually been shown to be very effective. However, these techniques have not been studied in combination with each other. this paper presents the IMPACT EPIC architecture to address the issues involved in designing processors based on these EPIC concepts. In particular, we focus on new execution and recovery models in which microarchitectural support for predicated execution is also used to enable efficient recovery from exceptions caused by speculatively executed instructions. this paper demonstrates that a coherent framework to integrate the three techniques can be elegantly designed to achieve much better performance than each individual technique could alone provide.

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