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Parallel fuzzy inference system for large volumes of remote sensing data

Parallel fuzzy inference system for large volumes of remote ...

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IEEE International symposium on Industrial Electronics (ISIE)

作者： Sang Gu Lee Department of Computer Engineering Hannam University South Korea

ISBN: (纸本)0780370902

In the pattern recognition on the large volume of satellite images, the inference time is much increased. In the remote sensing data having 4 wavebands, 778 training patterns are learned. Each land cover pattern is classified by using 159900 patterns including trained patterns. In the fuzzy classification, 778 fuzzy rules are generated. Each fuzzy rule has 4 fuzzy variables in the condition part. therefore, high performance parallel fuzzy inference architecture is needed. In this paper, we propose a novel parallel fuzzy inference system on a T3E parallel computer. In this, fuzzy rules are distributed and executed simultaneously. the ONE-To-ALL algorithm is used to broadcast the fuzzy input to the all nodes. the results of the MIN/MAX operations are transferred to the output processor by the ALL-TO-ONE algorithm. By parallel processing of the fuzzy rules, the parallel fuzzy inference algorithm extracts match parallelism and achieves a good speed factor. this system can be used in a large expert system that has many inference variables in the condition and the consequent part.

关键词： Fuzzy systems Remote sensing Fuzzy control computer architecture Concurrent computing Parallel processing Control systems Inference algorithms Expert systems Database systems

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Research on User Interface Transformation Method Based On MDA

Research on User Interface Transformation Method Based On MD...

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2017 16th International symposium on Distributed computing and Applications to Business,Engineering and Science（DCABES 2017）

作者： Gao Miao Liu Hongxing Lin Juncai Xie Songyu School of Computer Science and Technology Wuhan University of Technology

the user interface development method based on model driven architecture can effectively solve the problem that different platform-specific user interfaces have to be developed for the same application when the application needs to run on different *** method firstly designs the platform-independent model(PIM) of the user interface,then transforms the PIM into a variety of mainstream platform-specific model(PSM) automatically or semi-automatically,and finally transforms the PSM to a platform specific *** user interface transformation method from PIM to PSM is presented in this ***,a user interface PSM meta-model is ***,the mapping rules of PIM elements to PSM elements are defined in the meta-model level,and the transformation algorithm from PIM to PSM is *** verify the effectiveness of the method,we implemented a user interface software development tool which supports the transformation from PIM to PSM based on EMF and GMF.

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Cross Architectural Power Modelling

Cross Architectural Power Modelling

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IEEE/ACM International symposium on Cluster computing and the Grid (CCGRID)

作者： Kai Chen Peter Kilpatrick Dimitrios S. Nikolopoulos Blesson Varghese Queen’s University Belfast UK Virginia Tech USA

ISBN: (数字)9781728160955

ISBN: (纸本)9781728196497

Existing power modelling research focuses on the model rather than the process for developing models. An automated power modelling process that can be deployed on different processors for developing power models with high accuracy is developed. For this, (i) an automated hardware performance counter selection method that selects counters best correlated to power on both ARM and Intel processors, (ii) a noise filter based on clustering that can reduce the mean error in power models, and (iii) a two stage power model that surmounts challenges in using existing power models across multiple architectures are proposed and developed. the key results are: (i) the automated hardware performance counter selection method achieves comparable selection to the manual method reported in the literature, (ii) the noise filter reduces the mean error in power models by up to 55%, and (iii) the two stage power model can predict dynamic power with less than 8% error on both ARM and Intel processors, which is an improvement over classic models.

关键词： Hardware Program processors Computational modeling Power measurement computer architecture Mathematical model Benchmark testing

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Power and thermal Modeling of In-3D-Memory computing

Power and Thermal Modeling of In-3D-Memory Computing

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International symposium on Devices, Circuits and Systems (ISDCS)

作者： Jun-Han Han Robert E. West Karina Torres-Castro Nathan Swami Samira Khan Mircea Stan University of Virginia Charlottesville USA

ISBN: (数字)9781665414784

ISBN: (纸本)9781665447508

In-memory computing is an efficient big-data processing method that allows for performance scalability. Although 3D-memory is an established technology to integrate in-memory computing due to the 3D-stacked logic and memory layers, there are thermal issues and power budgets that restrict the integration of this concept in a 3D-stacked memory. In this paper, we investigate the power and thermal behavior of the in-3D-memory computing device based on thermal circuit modeling. When the logic layers consume 1 W/cm 2 in each layer, the maximum power available in the logic layer is 11.4 W/cm 2 and 7.3 W/cm 2 for the 4 and 16-layer stack. For high-rise stacked memory, passive heat sinks cannot sustain the operating temperature below 85 C. In this work, the validity of the proposed simulation results is compared with a conventional simulator.

关键词： Heating systems Computational modeling computer architecture Parallel processing Integrated circuit modeling Microfluidics Load modeling

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A Reversible-Logic based architecture for Artificial Neural Network

A Reversible-Logic based Architecture for Artificial Neural ...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Bappaditya Dey Kasem Khalil Ashok Kumar Magdy Bayoumi The Center for Advanced Computer Studies

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

high-performance computing beyond sub-10 nm advanced node technology allows us to explore and use complex 2.5D/3D SOC design architecture. Node scaling, heterogeneous integration, and complex design enable us to think beyond Moore's law but, at the same time, limit the scope with concerns of excessive power dissipation. the field of quantum computation and reversible logic functions has been researched in recent years in the context of low power VLSI circuit designs and nanotechnology. Reversible computation exhibits significantly reduced power dissipation in digital circuits. In this paper, we propose a novel design of Artificial Neural Network (ANN) using reversible logic gates. A thorough search of the relevant literature yielded only a few related articles. To the best of our knowledge, our proposed approach is the first attempt to implement a complete feedforward neural network circuit using only reversible logic gates. the comparative analysis demonstrates that our proposed approach has achieved an approximately 16% reduction in overall power dissipation compared to existing approaches. the proposed approach also has better scalability than the classical design approach.

关键词： Logic gates Hardware Neurons computer architecture Power dissipation Biological neural networks

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Automatic Sliding Window Operation Optimization for FPGA-Based

Automatic Sliding Window Operation Optimization for FPGA-Bas...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Haiqian Yu Miriam Leeser Department of Electrical and Computer Engineering Northeastern University Boston MA USA

FPGA-based computing boards are frequently used as hardware accelerators for image processing algorithms based on sliding window operations (SWOs). SWOs are both computationally intensive and data intensive and benefit from hardware acceleration with FPGAs, especially for delay sensitive applications. the current design process requires that, for each specific application using SWOs with different size of window, image, etc.; a detail design must be completed before a realistic estimate of the achievable speedup can be obtained. We present an automated tool, sliding window operation optimization (SWOOP), that generates the estimate of speedup for a high performance design before detailed implementation is complete. the achievable speedup is determined by the area of the FPGA, or, more often, the memory bandwidth to the processing elements. the memory bandwidth to each processing element is a combination of bandwidth to the FPGA and the efficient use of on-chip RAM as a data cache. SWOOP uses analytic techniques to automatically determine the number of parallel processing elements to implement on the FPGA, the assignment of input and output data to on-board memory, and the organization of data in on-chip memory to most effectively keep the processing elements busy. the result is a block layout of the final design, its memory architecture, and a measure of the achievable speedup. the results, compared to manual designs, show that the estimates obtained usinq SWOOP are very accurate

关键词： Field programmable gate arrays Random access memory Bandwidth Hardware Image processing Acceleration Delay Process design Design optimization Read-write memory

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Optimizing CRM Platforms with Distributed Cloud architectures for Scalable performance and Security

Optimizing CRM Platforms with Distributed Cloud Architecture...

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Innovative Approaches in Smart Technologies (ISAS), International symposium on

作者： Marian Ileana Pavel Petrov Vassil Milev Interdisciplinary Doctoral School National University of Science and Technology POLITEHNICA Bucharest Pitesti University Center Pitesti Romania Department of Computer Systems and Technologies St. Cyril and St. Methodius University of Veliko Tarnovo Veliko Tarnovo Bulgaria

ISBN: (数字)9798331540104

ISBN: (纸本)9798331540111

In today’s increasingly dynamic business environment, optimizing Customer Relationship Management (CRM) platforms is essential to increase operational efficiency and provide the best possible user experience. the paper presents an approach that aims to improve the performance and security of CRM platforms by integrating Distributed Cloud architectures. the proposed solution leverages the scalability offered by cloud solutions to ensure high availability and low response time while addressing data security challenges through decentralized frameworks. Key metrics are evaluated to improve user performance. By decentralizing data and using robust encryption mechanisms, a high level of security and compliance with data protection regulations is ensured. the analysis suggests that this type of architecture provides a modern solution and a scalable and secure foundation for CRM platforms, thus supporting digitization and business growth in an increasingly digitally interconnected world.

关键词： Cloud computing Costs Scalability Systems operation Customer relationship management Organizations User experience Regulation Reliability Protection

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FP-AMG: FPGA-Based Acceleration Framework for Algebraic Multigrid Solvers

FP-AMG: FPGA-Based Acceleration Framework for Algebraic Mult...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Pouya Haghi Tong Geng Anqi Guo Tianqi Wang Martin Herbordt Department of Electrical and Computer Engineering Boston University Boston MA USA Department of Physics University of Science and Technology of China Hefei China

ISBN: (数字)9781728158037

ISBN: (纸本)9781728158044

Partial Differential Equations (PDEs) are fundamental to many real-world scientific computing applications and so their optimization has undergone decades of study. Algebraic multigrid (AMG) is one of the most well-known solvers, being widely adopted in high performance computing (HPC) due to its good scalability. Acceleration of AMG is known to be very challenging, due to the following reasons: (1) irregular computation patterns, (2) random memory access, and (3) a large number of kernels with various computation types. To the best of our knowledge, there is no prior work on FPGA-based acceleration of AMG. To tackle these challenges, we propose an efficient FPGA-based reconfigurable framework, called FP-AMG, for high-performance AMG calculation. In order to obtain full pipeline utilization, we propose a novel and scalable architecture that can be reused for all kernels in AMG. Given that AMG is strictly memory-bound, we propose algorithmic and architectural optimizations to ensure nearly ideal use of memory bandwidth. the efficiency of FP-AMG is evaluated with six well-known benchmarks on two FPGA devices: one with and one without high bandwidth memory (HBM). the experimental results are compared with a highly optimized Intel Xeon E5-2680-V4 implementation of the state-of-the-art HYPRE library. Our experiments show that FP-AMG can achieve average speedups of 2.5× and 6.6×, for FPGAs without and with HBM, respectively.

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Improved Parallel Randomized Quasi Monte Carlo Algorithm of Asian Option Pricing on MIC architecture

Improved Parallel Randomized Quasi Monte Carlo Algorithm of ...

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13th International symposium on Distributed computing and Applications to Business,Engineering & Science（DCABES 2014）

作者： PengHui Yao YongHong Hu ZhongHua Lu YanGang Wang Jue Wang Super-computing Center Computer Network Information Center Chinese Academy of Sciences University of Chinese Academy of Sciences School of Statistics and Mathematics Central University of Finance and Economics

high-dimensional Option pricing, which plays an important role in complex financial activities, presents a great computational challenge in practice. Randomized Quasi Monte Carlo(RQMC) algorithm is of practical significance for forecasting option prices or other finance derivatives. In this paper, we present an improved parallel RQMC algorithm to forecast Asian option prices using Many Integrated Core(MIC) architecture. the improved algorithm employs novel data structure, independent random generator, vectorization technology, and data alignment. Numerical experiments were conducted on MIC architecture and the parallel performance was then analyzed. A speedup of 1.37 was achieved on MIC over CPU. Efficiency of 70.85% was achieved by using 64 OpenM P threads of a MIC card. An average speedup of 3.38 can be obtained by mixing the CPU and MIC computation in comparison with a single core of the CPU. Ample evidences proved the RQMC algorithm can benefit enormously from MIC architecture.

关键词： Quasi Monte Carlo Algorithm Asian Option Pricing MIC architecture Parallel Simulation

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Secure communication through jammers jointly optimized in geography and time 15

Secure communication through jammers jointly optimized in ge...

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16th ACM International symposium on Mobile Ad Hoc Networking and computing, MobiHoc 2015

作者： Allouche, Yair Cassuto, Yuval Efrat, Alon Segal, Michael Arkin, Esther M. Grebla, Guy Mitchell, Joseph S. B. Sankararaman, Swaminathan Dept. of Communication Systems Engineering Ben-Gurion University Beer-Sheva Israel Dept. Electrical Engineering Technion – Israel Institute of Technology Haifa32000 Israel Dept. of Computer Science University of Arizona TucsonAZ85721 United States Dept. Applied Mathematics and Statistics Stony Brook University Stony BrookNY11794 United States Dept. Electrical Engineering Columbia University New YorkNY10027 United States Dept. of Applied Mathematics and Statistics Stony Brook University Stony BrookNY11794 United States Akamai Technologies CambridgeMA02142 United States

ISBN: (纸本)9781450334891

Security-sensitive applications, such as patient health monitoring and credit card transactions, are increasingly utilizing wireless communication systems, RFIDs, wireless sensor networks, and other wireless communication systems. the use of interference-emitting jammers to protect these sensitive communications has been recently explored in the literature, and has shown high potential. In this paper we consider optimization problems relating to the temporal distributions of jammers’ activity, and the suitable coding regimes used for communication. Solving the joint problem optimally enables comprehensive security in space, at a low power consumption and low communication overhead. the joint optimization of jamming in space and time is driven by a new framework that uses the bit-error probability as a measure of communication quality. Under this framework, we show how to guarantee information-theoretic security within a geographic region, and with increased flexibility to tailor the coding regime to the problem’s geometry. We present efficient algorithms for different settings, and provide simulations for various scenarios using the bit-error probability functions. these simulations demonstrate the efficiency of the scheme. We believe that our scheme can lead to practical, economical and scalable solutions for providing another layer of protection of sensitive data, in cases where encryption schemes are limited or impractical. Copyright © 2015 ACM.

关键词： Sensitive data

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