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arXiv 2024年

作者： Dowran, Mohammadjavad Kilic, Ufuk Lamichhane, Suvechhya Erickson, Adam Barker, Joshua Schubert, Mathias Liou, Sy-Hwang Argyropoulos, Christos Laraoui, Abdelghani Department of Mechanical & Materials Engineering University of Nebraska-Lincoln 900 N 16th Street W342 NH. LincolnNE68588 United States Department of Electrical and Computer Engineering University of Nebraska-Lincoln 844 N. 16th Street LincolnNE68588 United States Department of Physics and Astronomy The Nebraska Center for Materials and Nanoscience University of Nebraska-Lincoln 855 N 16th Street LincolnNE68588 United States Department of Electrical Engineering The Pennsylvania State University 203 Electrical Engineering East University ParkPA16802 United States

Efficient and compact single photon emission platforms operating at room temperature with ultrafast speed and high brightness will be fundamental components of the emerging quantum communications and computing fields. However, so far, it is very challenging to design practical deterministic single photon emitters based on nanoscale solid-state materials that meet the fast emission rate and strong brightness demands. Here, a solution is provided to this longstanding problem by using metallic nanocavities integrated with hexagonal boron nitride (hBN) flakes with defects acting as nanoscale single photon emitters (SPEs) at room temperature. the presented hybrid nanophotonic structure creates a rapid speedup and large enhancement in single photon emission at room temperature. Hence, the nonclassical light emission performance is substantially improved compared to plain hBN flakes and hBN on gold-layered structures without nanocavity. Extensive theoretical calculations are also performed to accurately model the new hybrid nanophotonic system and prove that the incorporation of plasmonic nanocavity is key to efficient SPE performance. the proposed quantum nanocavity single photon source is expected to be an element of paramount importance to the envisioned room-temperature integrated quantum photonic networks. Copyright © 2024, the Authors. All rights reserved.

关键词： Photons

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Design and Analysis of Metastable-Hardened and Soft-Error Tolerant high-performance, Low-Power Flip-Flops

Design and Analysis of Metastable-Hardened and Soft-Error To...

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International symposium on Quality Electronic Design

作者： David Li David Rennie Pierce Chuang David Nairn Manoj Sachdev Department of Electrical and Computer Engineering University of Waterloo

ISBN: (纸本)9781612849133

In this paper, detailed analysis is given on the design of metastable-hardened and soft-error tolerant flip-flops while maintaining the basic characteristics of low-power and high-performance. We also propose two new flip-flop designs: pre-discharge soft-error tolerant flip-flop (PDFF-SE) and sense-amplifier transmission-gate soft-error tolerant flip-flop (SATG-SE). Following our main design approach, both PDFF-SE and SATG-SE use a cross-coupled inverter on the critical path in the master-stage to achieve good metastability while generating differential signals to facilitate the usage of the Quatro cell in the slave-stage to protect against soft-errors. PDFF-SE is designed to achieve very high performance with good metastability while SATG-SE is a low-power design also with good metastability. We also introduce two new design metrics, namely the metastability-delay-product (MDP) and the metastability-power-delay-product (MPDP), to analyze the design tradeoffs between metastability, power, and performance. Simulation results in 65nm CMOS technology have shown that both proposed designs achieve significant reduction in MDP and MPDP when compared to other flip-flop architectures analyzed in this work. Monte Carlo simulation results also show that these flip-flops are very robust and reliable against process variations and mismatches.

关键词： computer architecture Microprocessors Inverters Delay Mathematical model Power demand Transistors

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FPGA-Based Reduction Techniques for Efficient Deep Neural Network Deployment

FPGA-Based Reduction Techniques for Efficient Deep Neural Ne...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Adam Page Tinoosh Mohsenin Department of Computer Science & Electrical Engineering University of Maryland Baltimore

ISBN: (纸本)9781509023578

Deep neural networks have been shown to outperform prior state-of-the-art solutions that often relied heavily on hand-engineered feature extraction techniques coupled with simple classification algorithms. In particular, deep max-pooling convolutional neural networks (MPCNN) have been shown to dominate on several popular public benchmarks. Unfortunately, the benefits of deep networks have yet to be exploited in embedded, resource-bound settings that have strict power and area budgets. GPUs have been shown to improve throughput and energy-efficiency over CPUs due to their parallel architecture. In a similar fashion, FPGAs can improve performance while allowing more fine control over implementation. In order to meet power, area, and latency constraints, it is necessary to develop network reduction strategies in addition to optimal mapping. this work looks at two specific reduction techniques including limited precision for both fixed-point and floating-point formats, and performing weight matrix truncation using singular value decomposition. An FPGA-based framework is also proposed and used to deploy the trained networks. To demonstrate, a handful of public computer vision datasets including MNIST, CIFAR-10, and SVHN are fully implemented on a low-power Xilinx Artix-7 FPGA. Experimental results show that all networks are able to achieve a classification throughput of 16 img/sec and consume less than 700 mW when running at 200 MHz. In addition, the reduced networks are able to, on average, reduce power and area utilization by 37% and 44%, respectively, while only incurring less than 0.20% decrease in accuracy.

关键词： Matrix decomposition Sparse matrices Neural networks computer vision Complexity theory Singular value decomposition Field programmable gate arrays

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DTIFS: A Novel Computational Approach for Predicting Drug-Target Interactions from Drug Structure and Protein Sequence 16th

DTIFS: A Novel Computational Approach for Predicting Drug-Ta...

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16th International Conference on Intelligent computing, ICIC 2020

作者： Yan, Xin You, Zhu-Hong Wang, Lei Li, Li-Ping Zheng, Kai Wang, Mei-Neng School of Computer Science and Technology China University of Mining and Technology Xuzhou China College of Information Science and Engineering Zaozhuang University Zaozhuang China Xinjiang Technical Institute of Physics and Chemistry Chinese Academy of Sciences Ürümqi China School of Mathematics and Computer Science Yichun University Yichun336000 China

ISBN: (纸本)9783030608019

Identification and prediction of Drug-Target Interactions (DTIs) is the basis for screening drug candidates, which plays a vital role in the development of innovative drugs. However, due to the time-consuming and high cost constraints of biological experimental methods, traditional drug target identification technologies are often difficult to develop on a large scale. therefore, in silico methods are urgently needed to predict drug-target interactions in a genome-wide manner. In this article, we design a novel in silico approach, named DTIFS to predict the DTIs by combining Feature weighted Rotation Forest (FwRF) classifier with protein amino acids information. this model has two outstanding advantages: a) using the fusion data of protein sequence and drug molecular fingerprint, which can fully carry information;b) using the classifier with feature selection ability, which can effectively remove noise information and improve prediction performance. More specifically, we first use Position-Specific Score Matrix (PSSM) to numerically convert protein sequences and utilize Pseudo Position-Specific Score Matrix (PsePSSM) to extract their features. then a unified digital descriptor is formed by combining molecular fingerprints representing drug information. Finally, the FwRF is applied to implement on Enzyme, Ion Channel, GPCR, and Nuclear Receptor datasets. the results of the 5-fold CV experiment show that the prediction accuracy of this approach reaches 91.68%, 88.11%, 84.72% and 78.33% on four benchmark datasets, respectively. To further validate the performance of the DTIFS, we compare it with other excellent methods and Support Vector Machine (SVM) model. the experimental results of cross-validation indicated that DTIFS is feasible in predicting the relationship among drugs and target, and can provide help for the discovery of new candidate drugs. © 2020, Springer Nature Switzerland AG.

关键词： Feature Selection

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Energy Efficient Algorithms based on VM Consolidation for Cloud computing: Comparisons and Evaluations

Energy Efficient Algorithms based on VM Consolidation for Cl...

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IEEE/ACM International symposium on Cluster computing and the Grid (CCGRID)

作者： Qiheng Zhou Minxian Xu Sukhpal Singh Gill Chengxi Gao Wenhong Tian Chengzhong Xu Rajkumar Buyya Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences China School of Electronic Engineering and Computer Science Queen Mary University of London UK School of Software and Information Engineering University of Electronic Science and Technology of China China School of Computing and Information Systems University of Melbourne Australia

ISBN: (数字)9781728160955

ISBN: (纸本)9781728196497

Cloud computing paradigm has revolutionized IT industry and be able to offer computing as the fifth utility. With the pay-as-you-go model, cloud computing enables to offer the resources dynamically for customers anytime. Drawing the attention from both academia and industry, cloud computing is viewed as one of the backbones of the modern economy. However, the high energy consumption of cloud data centers contributes to high operational costs and carbon emission to the environment. therefore, Green cloud computing is required to ensure energy efficiency and sustainability, which can be achieved via energy efficient techniques. One of the dominant approaches is to apply energy efficient algorithms to optimize resource usage and energy consumption. Currently, various virtual machine consolidation-based energy efficient algorithms have been proposed to reduce the energy of cloud computing environment. However, most of them are not compared comprehensively under the same scenario, and their performance is not evaluated with the same experimental settings. this makes users hard to select the appropriate algorithm for their objectives. To provide insights for existing energy efficient algorithms and help researchers to choose the most suitable algorithm, in this paper, we compare several state-of-the-art energy efficient algorithms in depth from multiple perspectives, including architecture, modelling and metrics. In addition, we also implement and evaluate these algorithms with the same experimental settings in CloudSim toolkit. the experimental results show the performance comparison of these algorithms with comprehensive results. Finally, detailed discussions of these algorithms are provided.

关键词： Cloud computing Data centers Energy consumption Heuristic algorithms Computational modeling Scheduling Monitoring

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high performance IP Lookup on FPGA with Combined Length-Infix Pipelined Search

High Performance IP Lookup on FPGA with Combined Length-Infi...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Yi-Hua E. Yang Oguzhan Erdem Viktor K. Prasanna Ming Hsieh Department of Electrical Engineering University of Southern California USA Department of Electrical and Electronics Engineering Middle East Technical University Turkey

We propose a combined length-infix pipelined search (CLIPS) architecture for high-performance IP lookup on FPGA. By performing binary search in prefix length, CLIPS can find the longest prefix match in (log L-c) phases, where L is the IP address length (32 for IPv4) and c>;0 is a small design constant (c=2 in our prototype design). Each CLIPS phase matches one or more input infixes of the same length against a regular data structure. Various CLIPS phases can be optimized individually: (1) 16 bits of the IP address are used to direct-access a 288-kbit on-chip BRAM in phase 1, (2) 8 additional bits of the IP address are used to search a 1.5-million-entry pipelined dynamic search forest for a match in phase 2, (3) 1 to 8 additional bits of the IP address are used by a 2-stage Tree Bitmap for storing another 1 to 8 million routing prefixes in the tail phase. Post place-and-route results show that our CLIPS prototype, utilizing 28 Mbits on-chip BRAM and 4 external SRAM channels, sustains 312 MPPS IPv4 lookup (or 160 Gbps routing though put with 64-byte packets) against 9.5 million prefixes on state-of-the-art FPGA.

关键词： Routing IP networks Field programmable gate arrays throughput Prototypes Random access memory Memory management

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An environment for importance sampling based on stochastic activity networks

An environment for importance sampling based on stochastic a...

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Reliable Distributed Systems

作者： W.D. Obal W.H. Sanders Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

Model-based evaluation of reliable distributed and parallel systems is difficult due to the complexity of these systems and the nature of the dependability measures of interest. the complexity creates problems for analytical model solution techniques, and the fact that reliability and availability measures are based on rare events makes traditional simulation methods inefficient. Importance sampling is a well-known technique for improving the efficiency of rare event simulations. However, finding an importance sampling strategy that works well in general is a difficult problem. the best strategy for importance sampling depends on the characteristics of the system and the dependability measure of interest. this fact motivated the development of an environment for importance sampling that would support the wide variety of model characteristics and interesting measures. the environment is based on stochastic activity networks, and importance sampling strategies are specified using the new concept of the importance sampling governor. the governor supports dynamic importance sampling strategies by allowing the stochastic elements of the model to be redefined based on the evolution of the simulation. the utility of the new environment is demonstrated by evaluating the unreliability of a highly dependable fault-tolerant unit used in the well-known MARS architecture. the model is non-Markovian, with Weibull distributed failure times and uniformly distributed repair times.< >

关键词： Monte Carlo methods Stochastic processes Analytical models Discrete event simulation Availability Sampling methods Stochastic systems computer network reliability computer networks Concurrent computing

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A functional language architecture that supports fine-grain parallelism (extended abstract) 87

A functional language architecture that supports fine-grain ...

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Proceedings of the 15th annual conference on computer Science

作者： J. A. Davis Computer System Research Group Department of Electrical and Computer Engineering Iowa State University Ames Iowa

ISBN: (纸本)9780897912181

this abstract introduces a research project at Iowa State University whose goal is to produce a high-speed computing system by combining a multiprocessor configuration with a software paradigm based on the functional programming language SASL. the underlying architecture will evaluate combinatory code produced by the SASL compiler by graph reduction, in a manner similar to that of other proposed SKIM combinator machines. Fine-grain parallelism is supported by concurrently evaluating the body and parameters of functions, by “unrolling” recursive algorithms when possible, and by application of high-level user-defined data shaping operations, such as “map.” A simple dynamic load balancing scheme is used to evenly distribute the work of reducing the graph over all *** current design, under construction, is a tightly-coupled 16 processor system. Each processor has a private program memory that contains a complete copy of the program graph. the rules that specify and control the parallel reduction of the graph guarantee that the correct value will eventually be returned to the processor assigned to the root of the graph, and that inconsistencies in copies at various processors due to local reductions are of no concern. the data memory is global, but is physically organized so that a segment of the memory is located next to each processor. We expect that once the data is distributed through the graph during reduction, there will be some degree of locality of reference that will ease bus traffic. the typical bus bandwidth limitations that degrade performance in a fine-grain architecture are mitigated somewhat by employing a locally-developed high-speed (up to 100Mb/s per channel) “party line” serial bus for data references and interprocessor messages. the bus design allows for parallel data transfers, and can exchange processor load information in broadcast mode in one bus *** have chosen to base the design of the architecture on the functional language SASL

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GRIDCC: Real-time workflow system

Proceedings of the 2nd Workshop on Workflows in Support of L...

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Proceedings of the 2nd Workshop on Workflows in Support of Large-scale Science, WORKS'07 2007年 3-12页

作者： McGough, Andrew Stephen Akram, Asif Guo, Li Krznaric, Marko Dickens, Luke Colling, David Martyniak, Janusz Powell, Roger Kyberd, Paul Kotsokalis, Constantinos London e-Science Centre Imperial College London London United Kingdom High Energy Physics Group Imperial College London London United Kingdom Brunel University School of Engineering and Design Uxbridge United Kingdom Greek Research and Technology Network Athens Greece

ISBN: (纸本)1595937153

the Grid is a concept which allows the sharing of resources between distributed communities, allowing each to progress towards potentially different goals. As adoption of the Grid increases so are the activities that people wish to conduct through it. the GRIDCC project is a European Union funded project addressing the issues of integrating instruments into the Grid. this increases the requirement of workflows and Quality of Service upon these workflows as many of these instruments have real-time requirements. In thispaper we present the workflow management service within the GRIDCC project which is tasked with optimising the workflows and ensuring that they meet the pre-defined QoS requirements specified upon them. Copyright 2007 ACM.

关键词： Information systems

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Modi Script Recognition Using Convolutional Neural Networks and VGG16: A Deep Learning Approach for Historical Script Analysis

Modi Script Recognition Using Convolutional Neural Networks ...

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International Conference on computing Communication Control and Automation (ICCUBEA)

作者： Prathmesh Sainath Chidrawar Vidhya Dhamdhere Dept. of Computer Engineering G H Raisoni College of Engineering and Management Pune India

Recognizing historical scripts is a challenging task that requires specialized techniques due to the unique characteristics and variations present in these scripts. the Modi script, a historic script used to write the Marathi language in India, is presented in this research as a deep learning solution for the recognition of the script utilizing convolutional neural networks (CNNs) and the VGG16 architecture. the proposed approach consists of several steps. First, a diverse dataset of Modi script samples is collected, encompassing various characters, words, and sentences written in the script. the dataset is preprocessed to ensure consistency and enhance the model's robustness, including resizing, grayscale conversion, normalization, and data augmentation techniques. After that, the dataset is partitioned into three sets: training, validation, and testing. the VGG16 architecture is employed as the base model for feature extraction, leveraging its ability to learn low-level and high-level features from images. By obtaining handwritten examples from the IEEE Dataport collection, the dataset (training images) for the characters is updated. the model is trained using the training dataset, and hyperparameter tuning is performed using the validation set to optimize its performance. the testing dataset is used to measure the trained model's performance in identifying the Modi script by assessing metrics including accuracy, precision, recall, and F1 score. the performance of the model is assessed, and any updates or modifications that are required to increase the model's accuracy are implemented. the developed model can be deployed for prediction on unseen Modi script images, enabling the recognition of characters or words within the script. this approach provides a promising solution for historical script analysis and contributes to the preservation and understanding of the Modi script's cultural and linguistic heritage.

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