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An IPSec-aware TCP PEP for integrated mobile satellite networks

An IPSec-aware TCP PEP for integrated mobile satellite netwo...

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IEEE International symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： G. Ciccarese M. De Blas L. Patrono P. Marra G. Tomasicchio Dep. of Innovation Engineering University of Lecce Lecce Italy Universita del Salento Lecce Puglia IT Dept. of Innovation Eng. Lecce Univ. Italy Business Multimedia Unit Alenia Spazio Rome Italy

Mobile computing and security in Internet have become two of the most important challenges in the information technology world. Among wireless technologies which support user mobility, satellites will play a very important role. Unfortunately, TCP does not perform well on satellite channels because of the related high delay-bandwidth product, high bit error rate (BER) and burst errors mainly due to shadowing. In order to obtain improvements in TCP performance, an approach local to the satellite link could be adopted. In fact, recently, some studies showed the effectiveness of the use of a reliable data link protocol that is well suited to mobile geo-stationary satellite channel characteristics. However, the resultant more variable end-to-end delay causes, as a side effect, a new problem: the competition between retransmission mechanisms at transport layer and data link layer. the introduction of a suitable performance enhancing proxy (PEP) on the satellite gateway has proved to be a viable technique to face the problem. However, the compatibility with the usage of network layer security mechanisms, such as IPSec, should be pursued. this paper just deals with the definition of an IPSec-aware TCP PEP, called secure PEP (SPEP), that is completely transparent to IPSec architecture. the performances of SPEP have been validated in the context of Web application by using network simulator tool. the simulation results, in terms of Web-page download mean time, have shown that the proposed solution provides substantial improvements in TCP performance.

关键词： Satellites Bit error rate Mobile computing Information security Internet Information technology Communication system security Delay computer errors Shadow mapping

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Machine Learning for Predictive Resource Scaling of Microservices on Kubernetes Platforms 23

Machine Learning for Predictive Resource Scaling of Microser...

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Proceedings of the IEEE/ACM 16th International Conference on Utility and Cloud computing

作者： Adam Rubak Javid Taheri Department of Mathematics and Computer Science Karlstad University Karlstad Sweden

ISBN: (纸本)9798400702341

Resource scaling is the process of adjusting the amount of resources allocated to a system or a service according to the changing demand. For microservices, resource scaling can be done at different levels, such as the container, the pod, or the cluster. However, the current approaches for resource scaling are not good enough because they rely on reactive or rule-based methods that do not account for the dynamic and complex nature of microservices. these methods often lead to over-provisioning or under-provisioning of resources, both affecting the quality of service and the cost efficiency. To address these issues, this work focuses on testing multiple machine learning approaches to optimize the pod dimensioning problem for Kubernetes platforms through predicting resource requirements for an upscaled number of users. the proposed approach aims to address the limitations of the standard Horizontal Pod Autoscaler (HPA), which often results in resource wastage or suboptimal performance. the results were promising and demonstrated high precision and performance of multiple ML models to accurately forecast future resource needs.

关键词： kubernetes horizontal pod autoscaler ML

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Optimization Techniques for Scheduling IoT tasks in Fog-based Environments

Optimization Techniques for Scheduling IoT tasks in Fog-base...

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International symposium on high Capacity Optical Networks and Enabling Technologies, HONET

作者： Rija Tariq Hareem Ashraf Maira Sohail Hasan Ali Khattak School of Electrical Engineering and Computer Science National University of Sciences and Technology (NUST) Islamabad Pakistan

ISBN: (纸本)9781665461986

Cloud computing has been around us for a while now, and everywhere we look around, data surrounds us. Data is transferred over a network and computed over some cloud platform. the concept of the fog layer has also been around, and there have been multiple implementations of how these two sets of layers can work together and implement an excellent and optimized structure. Numerous factors are involved in creating an architecture like that, including time, energy, network bandwidth, etc. Every solution presented tries to cater to most of these factors and gives the best possible outcome. But there has been a trade-off always. Such architecture has been here for many years. these solutions and many new ones are implemented to find a common optimal point. Such solutions can be divided into categories like bio-inspired algorithms, evolution-based algorithms, etc. there can also be a division based on these algorithms' heuristic and metaheuristic nature. this paper focuses on all these techniques and compares the objectives and limitations of previous implementations. this paper also pointed out majorly used algorithms repeatedly seen during this research and simulated on the same set of parameters to determine which solution presents a more efficient performance.

关键词： Cloud computing Costs Processor scheduling Smart cities Heuristic algorithms Metaheuristics computer architecture

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performance and Analysis of Approximate Multipliers using Modified Dual-Stage 5:2 Compressors

Performance and Analysis of Approximate Multipliers using Mo...

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Intelligent Technologies (CONIT), International Conference on

作者： B. Srikanth A.Siva Jahnavi Shruti Tiwari Beejarapu Vamshi Department of ECE Vardhaman College of Engineering Rangareddy Telangana

ISBN: (数字)9798350349900

ISBN: (纸本)9798350349917

this paper presents a modified approach to approximate multiplier design utilizing dual-stage 5:2 compressors. Multipliers are fundamental components in digital signal processing and computing systems, often demanding a trade-off between accuracy and resource utilization. Approximate computing offers a promising paradigm to mitigate this trade-off by exploiting inherent error resilience in certain applications. Our proposed de-sign leverages dual-stage 5:2 compressors, a specialized architecture optimized for efficient and high-performance multiplication operations. By introducing controlled approximation techniques, we achieve significant improvements in power efficiency and area utilization compared to traditional multiplier designs by 36.37% and 34%. We provide comprehensive simulation results demonstrating the effectiveness of our approach across various benchmarks, highlighting substantial gains in performance while maintaining acceptable levels of accuracy. this work contributes to advancing the state-of-the-art in approximate multiplier design, offering valuable insights for designing energy-efficient and resource-aware computing systems. So that a total of two different 4:2 approximate compressors are analyzed and one 5:2 compressor proposed. the proposed compressors are utilized to implement 8*8 and 16*16 Dadda multiplier. the analysis is further extended to project the application of the implemented design in error resilient applications like image smoothing and image multiplication.

关键词： Accuracy Smoothing methods Error analysis Simulation computer architecture Compressors Topology

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Designing with extreme parallelism 08

Designing with extreme parallelism

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Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays

作者： Guy Lemieux Tarek El-Ghazawi University of British Columbia Vancouver BC Canada George Washington University Washington WA

ISBN: (纸本)9781595939340

Modern FPGAs can implement large, custom compute engines that are designed to exploit extreme amounts of parallel computation. through parallelism, these systems achieve orders of magnitude higher performance than the fastest microprocessors. Building such custom compute engines with existing hardware design languages is too difficult and time-consuming. For this to become mainstream technology, the task of designing such parallel systems must be as simple as possible. thus, high-level languages are needed which can specify a custom compute engine or be compiled to run on predesigned parallel systems. In this workshop, we will examine several approaches for specifying extremely parallel computations in high-level languages. these can be used to build parallel systems in FPGAs, or they can be used to specify parallel computations in other competing architectures. By examining several different approaches, one gains insight into the best approach for solving a given problem. Ideally, this will also inspire new approaches for designing with extreme parallelism

关键词： custom compute engine high-level electronic design FPGA hardware description language parallel processing reconfigurable computing

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GRAPE-MPs: Implementation of an SIMD for Quadruple/Hexuple/Octuple-Precision Arithmetic Operation on a Structured ASIC and an FPGA

GRAPE-MPs: Implementation of an SIMD for Quadruple/Hexuple/O...

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IEEE International symposium on Embedded Multicore Socs (MCSoC)

作者： Naohito Nakasato Hiroshi Daisaka Toshiyuki Fukushige Atsushi Kawai Junichiro Makino Tadashi Ishikawa Fukuko Yuasa University of Aizu Aizu-Wakamatsu Fukushima Japan Hitotsubashi University K & F Computing Research Tokyo Institute of Technology High Energy Accelerator Research Organization

We describe the design and performance of the GRAPE-MPs, a series of SIMD accelerator boards for quadruple/hexuple/octuple-precision arithmetic operations. Basic design of GRAPE-MPs is that it consists of a number of processing elements (PE) and memory components which handle data with quadruple/hexuple/octuple-precision. A GRAPE-MPs processor is implemented on a structured ASIC chip and an FPGA chip. GRAPE-MP (quadruple-precision) uses a structured ASIC chip from eASIC corp., which has 6 PE and operates with 100MHz clock cycle. the theoretical peak quadruple-precision performance of the single board is 1.2 Gflops and the achieved performance for the Feynman loop integrals is about 0.5 Gflops. GRAPE-MP4/6/8 (quadruple/hexuple/octuple-precision) uses an FPGA chip from Aletra corporation. For example, in the current implementation, MP8 has 10 PE with 70MHz operation clock cycle. We also present the performance results with the multiple GRAPE-MPs boards. the achieved performance of four MP8 boards is about 1.6 Gflops. It is roughly 90 times faster than the performance of a single core of a CPU with comparable precision. We show that our hardware based approach to evaluate the Feynman loop integrals in high precision arithmetic operations is highly effective.

关键词： Pipelines Field programmable gate arrays Process control computer architecture Registers Application specific integrated circuits Clocks

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high-performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product

High-Performance Deep-Learning Coprocessor Integrated into x...

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Annual International symposium on computer architecture, ISCA

作者： Glenn Henry Parviz Palangpour Michael thomson J Scott Gardner Bryce Arden Jim Donahue Kimble Houck Jonathan Johnson Kyle O’Brien Scott Petersen Benjamin Seroussi Tyler Walker Centaur Technology Advantage Engineering LLC

ISBN: (数字)9781728146614

ISBN: (纸本)9781728146621

Demand for high performance deep learning (DL) inference in software applications is growing rapidly. DL workloads run on myriad platforms, including general purpose processors (CPU), system-on-chip (SoC) with accelerators, graphics processing units (GPU), and neural processing unit (NPU) addin cards. DL software engineers typically must choose between relatively slow general hardware (e.g., CPUs, SoCs) or relatively expensive, large, power-hungry hardware (e.g., GPUs, NPUs). this paper describes Centaur Technology's Ncore, the industry's first high-performance DL coprocessor technology integrated into an x86 SoC with server-class CPUs. Ncore's 4096 byte-wide SIMD architecture supports INT8, UINT8, INT16, and BF16 datatypes, with 20 tera-operations-per-second compute capability. Ncore shares the SoC ring bus for low-latency communication and work sharing with eight 64-bit x86 cores, offering flexible support for new and evolving models. the x86 SoC platform can further scale out performance via multiple sockets, systems, or third-party PCIe accelerators. Ncore's software stack automatically converts quantized models for Ncore consumption and leverages existing DL frameworks. In MLPerf's Inference v0.5 closed division benchmarks, Ncore achieves 1218 IPS throughput and 1.05ms latency on ResNet-50v1.5 and achieves lowest latency of all Mobilenet-V1 submissions (329μs). Ncore yields 23x speedup over other x86 vendor percore throughput, while freeing its own x86 cores for other work. Ncore is the only integrated solution among the memory intensive neural machine translation (NMT) submissions.

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Utilizing many-core accelerators for halo and center finding within a cosmology simulation

Utilizing many-core accelerators for halo and center finding...

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IEEE symposium on Large Data Analysis and Visualization (LDAV)

作者： Christopher Sewell Li-ta Lo Katrin Heitmann Salman Habib James Ahrens Los Alamos National Laboratory Argonne National Laboratory

Efficiently finding and computing statistics about “halos” (regions of high density) are essential analysis steps for N-body cosmology simulations. However, in state-of-the-art simulation codes, these analysis operators do not currently take advantage of the shared-memory data-parallelism available on multi-core and many-core architectures. the Hybrid / Hardware Accelerated Cosmology Code (HACC) is designed as an MPI+X code, but the analysis operators are parallelized only among MPI ranks, because of the difficulty in porting different X implementations (e.g., OpenMP, CUDA) across all architectures on which it is run. In this paper, we present portable data-parallel algorithms for several variations of halo finding and halo center finding algorithms. these are implemented with the PISTON component of the VTK-m framework, which uses Nvidia's thrust library to construct data-parallel algorithms that allow a single implementation to be compiled to multiple backends to target a variety of multi-core and many-core architectures. Finally, we compare the performance of our halo and center finding algorithms against the original HACC implementations on the Moonlight, Stampede, and Titan supercomputers. the portability of thrust allowed the same code to run efficiently on each of these architectures. On Titan, the performance improvements using our code have enabled halo analysis to be performed on a very large data set (81923 particles across 16,384 nodes of Titan) for which analysis using only the existing CPU algorithms was not feasible.

关键词： Algorithm design and analysis computer architecture Computational modeling Graphics processing units Analytical models Acceleration Pistons

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Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

Are Coarse-Grained Overlays Ready for General Purpose Applic...

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IEEE International symposium on Dependable, Autonomic and Secure computing (DASC)

作者： Abhishek Kumar Jain Douglas L. Maskell Suhaib A. Fahmy School of Computer Engineering Nanyang Technological University Singapore School of Engineering University of Warwick United Kingdom

Combining processors with hardware accelerators has become a norm with systems-on-chip (SoCs) ever present in modern compute devices. Heterogeneous programmable system on chip platforms sometimes referred to as hybrid FPGAs, tightly couple general purpose processors with high performance reconfigurable fabrics, providing a more flexible alternative. We can now think of a software application with hardware accelerated portions that are reconfigured at runtime. While such ideas have been explored in the past, modern hybrid FPGAs are the first commercial platforms to enable this move to a more software oriented view, where reconfiguration enables hardware resources to be shared by multiple tasks in a bigger application. However, while the rapidly increasing logic density and more capable hard resources found in modern hybrid FPGA devices should make them widely deployable, they remain constrained within specialist application domains. this is due to both design productivity issues and a lack of suitable hardware abstraction to eliminate the need for working with platform-specific details, as server and desktop virtualization has done in a more general sense. To allow mainstream adoption of FPGA based accelerators in general purpose computing, there is a need to virtualize FPGAs and make them more accessible to application developers who are accustomed to software API abstractions and fast development cycles. In this paper, we discuss the role of overlay architectures in enabling general purpose FPGA application acceleration.

关键词： Field programmable gate arrays Hardware Fabrics Program processors computer architecture Acceleration

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performance Analysis of Convolutional Neural Network Models

Performance Analysis of Convolutional Neural Network Models

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International Conference on Advanced computer Control, ICACC

作者： S Kala Debdeep Paul Babita R Jose Jimson Mathew S Nalesh Cochin University of Science And Technology Kerala India - 682 022 Department of Electrical Engineering IIT Patna India Department of Computer Science and Engineering IIT Patna India Department of Electronics Cochin University of Science And Technology Kerala India - 682 022

Deep Neural Networks (DNNs) have become a promising solution for numerous machine learning tasks, which include object detection, classification, weather forecasting, video surveillance and safety management. Convolutional Neural Network (CNN) is a class of DNN, which can achieve state-of-art accuracy and high performance for most of the computer vision tasks. Training of CNNs is computationally intensive and may take multiple days for completion. In this work we have performed the feed forward path implementation and training of AlexNet, VGG-16 and ResNet models on Nvidia GeForce GTX 1080 Ti GPU with 3584 CUDA Cores, 1582 MHz, 11GB GDDR5X, using Caffe framework. Inference and training of these models are also performed on Nvidia Jetson TX2 hardware platform. We also present a detailed analysis of graphics processing unit (GPU) and general purpose processor (GPP) implementations of AlexNet, VGG-16 and ResNet-50 network models. A hardware architecture for performing convolution operations in feed forward path of CNN has also been implemented in Virtex-7 XC7VX690T FPGA, with throughput of 184 GFLOPS for AlexNet, 172 GFLOPS for VGG-16 and 197 GFLOPS for ResNet-50 model.

关键词： convolutional neural nets graphics processing units learning (artificial intelligence)

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