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A Neural Network-Based Intelligent Decision-Making in the Air-Offensive Campaign with Simulation

A Neural Network-Based Intelligent Decision-Making in the Ai...

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International Conference on Computational Intelligence and Security

作者： Gang Hu Chuhan Zhou Xiaojie Zhang Han Zhang Zhihua Song Zhongliang Zhou Equipment Management and UAV Engineering College Air Force Engineering University Xi'an China

Combat units in joint operations have huge decision space and many uncertain factors. Generally speaking, most of the traditional decision-making methods are based on rules, and it is impossible to establish a reliable mapping relationship between decision space and combat results. To promote the research of intelligent decision making in joint operations, the Equipment Development Department of the Central Military Commission held a challenge called `strategic plans on the computer, joint intelligent win'. In this challenge, the forces and the performance equipment are fixed at both the sides of the attack and defense. this setup helps the intelligent deci-sion-making agents to identify the scenarios which score high and have good learning scope in decision making. In the study, we propose an air offensive operations decision-making agent based on a neural network. To perform testing and analysis, we have used the neural network dataset available at a decision space. the decision space comprises of different decision-making rules and rando disturbances. the proposed model shows better results as compared to traditional rule-based operations and military expert decision-based operations in the test set.

关键词： Training Military computing Atmospheric modeling Decision making Neural networks Manuals Security

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Multi-task Downloading for P2P-VoD: An Empirical Perspective

Multi-task Downloading for P2P-VoD: An Empirical Perspective

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Tieying Zhang Zhenhua Li Xueqi Cheng Xianghui Sun Institute of Computing Technology Chinese Academy and Sciences China Department of Computer Science and Technology Peking University China China Telecom Group Corporation China

For current P2P-VoD systems, three fundamental problems exit in user experience: exceedingly large startup delay, long jump latency, and poor playback continuity. these problems primarily stem from lack of media data. In this paper, we propose Multi-Task Downloading with Bandwidth Control (MTD(BC)), an efficient and practical mechanism to prefetch media data. In MTD, a user can download multiple videos in parallel with its current viewing, which significantly decreases video switching delays. However, MTD brings a serious problem: downloading "other" tasks could impede the playback performance of the current viewing, especially in low-bandwidth network. this problem is solved through our design of bandwidth control. To our knowledge, we are the first to propose MTD with bandwidth control for P2P-VoD and conduct empirical evaluations in the real-world system. the running results show that MTD(BC) achieves better streaming quality than the traditional method. In particular, our mechanism reduces 75% of startup delay and 36% of jump latency in low-bandwidth network with high system scalability.

关键词： Bandwidth Videos Delay Upper bound Servers Bit rate Media

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MANET-oriented SDN: Motivations, Challenges, and a Solution Prototype

MANET-oriented SDN: Motivations, Challenges, and a Solution ...

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IEEE International symposium on World of Wireless Mobile and Multimedia Networks (WoWMoM)

作者： Paolo Bellavista Alessandro Dolci Carlo Giannelli Department of Computer Science and Engineering University of Bologna Italy Department of Mathematics and Computer Science University of Ferrara Italy

ISBN: (纸本)9781538647264

Software Defined Networking (SDN), with its clear distinction of control and data planes, as well with its simple paradigm of logically centralized controller with global visibility of the whole targeted network status, is gaining momentum in different scenarios. However, its effective exploitation in Mobile Ad hoc Networks (MANETs) is still an open research issue, mainly due to the peculiar dynamicity of the related environments (e.g., in the case of spontaneous MANETs) and to the need to exploit locality considerations to achieve efficient solutions. Here we originally present an architecture and an associated prototype for SDN-based quality management of selected traffic flows, which advance the state-of-the-art in the field by i) allowing high flexibility via deployment of new flow management policies at provisioning time, ii) properly handling node join/leave events, and, most relevant, iii) determining MANET “islands”, usually managed by separated SDN controllers that can seldom interact to federate their management decisions. In addition to design/implementation insights and to the availability of the prototype code, this paper provides the community with a significant and novel contribution in terms of first experimental performance results, which show the feasibility and the effectiveness of the proposed approach.

关键词： Ad hoc networks Mobile computing Quality of service Receivers Prototypes Routing Knowledge engineering

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the Birth, Evolution and Future of the Microprocessor

The Birth, Evolution and Future of the Microprocessor

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International Conference on computer and Information Technology (CIT)

作者： M. Shima CTO Visual Technology Inc. USA

Summary form only given. the world's first microprocessor, the 4004, was co-developed by Busicom, a Japanese manufacturer of calculators, and Intel, a U.S. manufacturer of semiconductors. During the development of a general-purpose LSI for not only desktop calculators but also other business machines, originally based on a decimal computer with a stored program method, a basic architecture of 4004 was developed in August 1969; a concrete plan for the 4004 system was finalized in December 1969; and the first microprocessor was successfully developed in March 1971. Microprocessors, which became the "technology to open up a new era", brought two outstanding impacts, "power of intelligence" and "power of computing". First, microprocessors opened up a new "era of programming" through replacing with software, the hardwired logic based on IC's of the former "era of logic". At the same time, microprocessors allowed young engineers access to "power of computing" for the creative development of personal computers and computer games, which in turn led to growth in the software industry, and paved the way to the development of high-performance microprocessors. Development engineers involved in creative development can be likened to explorers who go into unmapped territory without a compass, having hope for success and fear of failure. Also, an engineer must be armed with the firm belief that his mission is nothing but development, and must be determined to go his own way, never following another's tracks. In this paper, the birth, evolution and future of microprocessor are described. 4004 performance was only 0.06 MIPS with 2,238 transistors and 750 KHz operating frequency. Microprocessors evolved from 4 bit to 64 bit microprocessors, introducing computer technologies such as pipeline, super-pipeline, super-scalar, VLIW, cache memory, and virtual memory system. Now, it is possible to integrate 16 sets of microprocessor with 64GB of memory on the board. In 20th century, micropro

关键词： Microprocessors Power engineering computing Logic programming Semiconductor device manufacture Calculators Power engineering and energy Large scale integration computer architecture Concrete Microcomputers

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Loop level speculation in a task based programming model

Loop level speculation in a task based programming model

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International Conference on high performance computing

作者： Rahulkumar Gayatri Rosa. M Badia Eduard Aygaude Barcelona Supercomputing Center Barcelona Spain

Uncountable loops (such as while loops in C) and if-conditions are some of the most common constructs in programming. While-loops are widely used to determine the convergence in linear algebra algorithms or goal finding problems from graph algorithms, to name a few. In general while-loops are used whenever the loop iteration space, the number of iterations a loop executes is unknown. Usually in while-loops, the execution of the next iteration is decided inside the current loop iteration (i.e. the execution of iteration i depends on the values computed in iteration i-1). this precludes their parallel execution in today's ubiquitous multi-core architectures. In this paper a technique to speculatively create parallel tasks from the next iterations before the current one completes is proposed. If consecutive loop-iterations are only control dependent, then multiple iterations can be executed simultaneously; later in the execution path, the runtime system will decide to either commit the results of such speculatively executed iterations or undo the changes made by them. Data dependences within or between non-speculative and speculative work are honored to guarantee correctness. the proposed technique is implemented in SMPSs, a task-based dataflow programming model for shared-memory multiprocessor architectures. the approach is evaluated on a set of applications from graph algorithms and linear algebra. Results are promising with an average increase in the speedup of 1.2x with 16 threads when compared to non speculative execution of the applications. the increase in the speedup is significant, since the performance gain is achieved over an already parallelized version of the benchmarks.

关键词： Runtime Synchronization Cascading style sheets Parallel processing computer architecture Instruction sets Programming

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A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization 99

A hardware-driven profiling scheme for identifying program h...

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Proceedings of the 26th annual international symposium on computer architecture

作者： Matthew C. Merten Andrew R. Trick Christopher N. George John C. Gyllenhaal Wen-mei W. Hwu Center for Reliable and High-Performance Computing Department of Electrical and Computer Engineering University of Illinois Urbana IL

ISBN: (纸本)9780769501703

this paper presents a novel hardware-based approach for identifying, profiling, and monitoring hot spots in order to support runtime optimization of general purpose programs. the proposed approach consists of a set of tightly coupled hardware tables and control logic modules that are placed in the retirement stage of a processor pipeline removed from the critical path. the features of the proposed design include rapid detection of program hot spots after changes in execution behavior, runtime-tunable selection criteria for hot spot detection, and negligible overhead during application execution. Experiments using several SPEC95 benchmarks, as well as several large WindowsNT applications, demonstrate the promise of the proposed design.

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Implementation Study of FFT on Multi-lane Vector Processors

Implementation Study of FFT on Multi-lane Vector Processors

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Euromicro symposium on Digital System Design

作者： Bogdan Spinean Georgi Gaydadjiev Computer Engineering Laboratory TU Delft Netherlands

In this paper we extend a custom FFT vector architecture by adding multiple lane capabilities and study its hardware implementation. We use the six step algorithm to segment a long transform of size N = Z × L into L smaller transforms of size Z. We split the data into pairs of vector registers (for the real and imaginary part), containing Z elements. A vector register pair with its corresponding functional unit form a single lane replicated L times. While smaller transforms proceed iteratively all of them are computed in parallel. the shorter FFT transforms along the X dimension are computed using previously proposed vector permutations while the transforms along the Y dimension are performed using a simple butterfly network that handles inter-lane communication. All data patterns required by the FFT computation are generated implicitly in hardware by a simple control unit. No data transposition is required and the twiddle factors are stored locally inside the functional units. We validated our design through simulation and ASIC synthesis targeting 90nm technology. We compare three possible configurations for computing a 256 point FFT, all running at 217 MHz with Z × L equal to: a) 32 × 8, b) 16 × 16 and c) 8 × 32. Configuration a) is the smallest and the slowest; configuration b) requires 1.43 times fewer cycles and requires 1.64 more area while configuration c) requires 1.76 times fewer cycles and is 3.16 times larger. Unlike other high performance FFT implementations, our design offers the possibility to trade-off execution speed for two types of resources: vector register size and number of lanes. Another important contribution is the possibility to execute 2D FFT without any modifications or adaptations.

关键词： Vectors Registers computer architecture Discrete Fourier transforms Indexes Vector processors

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Study on Fast Human Activity Recognition Based on Optimized Feature Selection

Study on Fast Human Activity Recognition Based on Optimized ...

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2017 16th International symposium on Distributed computing and Applications to Business,Engineering and Science（DCABES 2017）

作者： Hanyuan Xu Zhibin Huang Jue Wang Zilu Kang School of Computer Science Beijing University of Posts and Telecommunications Institute of Internet of Things Technology China Electronic Technology Group Corporation Information Engineering Research Center

Sensor-based human activity recognition has attracted much scholarly attention due to its merit of wide ***,because of such hardware limitations as battery capacity and computing power,most current generation of wearable devices cannot yet benefit from those activity recognition methods based on deep learning theory and high dimension features since implementing these methods are time-consuming and need a relatively large amount of calculation.A solution,therefore,is proposed for this situation,which aims to reduce computational complexity by reducing the feature dimension through analyzing the linear correlation between the *** on the support vector machine model of single-layer fully connected network,the training and recognition time are significantly reduced while the recognition accuracy is still *** experiment is based on the public dataset in the UCI Machine Learning Repository,and it uses Caffe,a deep learning framework,to structure the support vector machine *** the experiment,when the feature dimension is reduced from 561 to 130,the training time can be reduced by 70% while the recognition accuracy is kept at a promising 91%.

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Design of a chip set for a parallel computer based on the crossbar interconnection principle

Design of a chip set for a parallel computer based on the cr...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： M.L. Bos CINTEC-Instituto Politecnico Nacional Mexicali Mexico

Frequently found implementations of the parallel random access machine (PRAM) include the common-bus multiprocessor as well as shared-memory machines based on several types of switching networks. the performance of the common-bus multiprocessor decreases as the total number of required data exchanges among processors, for a given computation, grows. the same applies to switching networks but, because of the higher number of available data paths, to a lesser degree. In this sense, the advantages of the crossbar network as compared to other switching networks are well known. However, the high number of switching elements required by this network has been a limitation on its use in practical machines. In this paper, a variation of the crossbar network based on m(m-l) switching elements, where m is the number of processors, is discussed. the architecture of the machine is described, and the design of the chip set of the machine, based on field-programmable gate arrays (FPGA's), is presented. A brief description of the functions implemented in each device is given, followed by a detailed discussion of the switching elements, and, in particular, of the access priority arbitration function implemented in the device. performance estimations of an 8-processor machine are presented and compared with a common-bus multiprocessor design using similar technology. It is concluded that the crossbar network represents a technologically viable alternative to other implementations of limited parallelism.

关键词： Concurrent computing Cache memory Network topology Tellurium Phase change random access memory Field programmable gate arrays Parallel processing Data communication Costs Multiprocessor interconnection networks

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the design and analysis of a cache architecture for texture mapping 97

The design and analysis of a cache architecture for texture ...

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Proceedings of the 24th annual international symposium on computer architecture

作者： Ziyad S. Hakura Anoop Gupta Computer Systems Laboratory Stanford University Stanford CA

ISBN: (纸本)9780897919012

the effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. Despite a recent surge in interest in three-dimensional graphics from computer architects, high-quality high-speed texture mapping has so far been confined to costly hardware systems that use brute-force techniques to achieve high performance. One obstacle faced by designers of texture mapping systems is the requirement of extremely high bandwidth to texture memory. high bandwidth is necessary since there are typically tens to hundreds of millions of accesses to texture memory per second. In addition, to achieve the high clock rates required in graphics pipelines, low-latency access to texture memory is needed. In this paper, we propose the use of texture image caches to alleviate the above bottlenecks, and evaluate various tradeoffs that arise in such *** find that the factors important to cache behavior are (i) the representation of texture images in memory, (ii) the rasterization order on screen and (iii) the cache organization. through a detailed investigation of these issues, we explore the best way to exploit locality of reference and determine whether this technique is robust with respect to different scenes and different amounts of texture. Overall, we observe that there is a significant amount of temporal and spatial locality and that the working set sizes are relatively small (at most 16KB) across all cases that we studied. Consequently, the memory bandwidth requirements of a texture cache system are substantially lower (at least three times and as much as fifteen times) than the memory bandwidth requirements of a system which achieves equivalent performance but does not utilize a cache. these results are very encouraging and indicate that caching is a promising approach to designing memory systems for texture mapping.

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