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检索条件"任意字段=16th Symposium on Computer Architecture and High Performance Computing"

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Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors

Algorithm Parallelism Estimation for Constraining Instructio...

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Euromicro symposium on Digital System Design

作者： Roel Jordans Rosilde Corvino Lech Józwiak Department of Electrical Engineering Eindhoven University of Technology Eindhoven Netherlands

Customization of a (generic) processor to a particular application makes it possible to achieve high performance within a tight energy budget. Most of the published research works on processor customization extend a simple base processor with custom instructions. Only few works have considered a full instruction-set customization for complex highly parallel Very Long Instruction Word (VLIW) architectures. this paper discusses the parallelism estimation for a full instruction-set synthesis for VLIW processors and evaluates four methods to compute the maximum parallelism of a given application. We explain important reasons for computing and using such parallelism bounds, discuss the implementation of several methods, and our experimental research performed to evaluate the efficiency of each method.

关键词： VLIW Program processors Estimation computer architecture Processor scheduling Schedules

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A 16-context optically reconfigurable gate array

A 16-context optically reconfigurable gate array

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IEEE International Conference on Application-specific Systems, architectures and Processors

作者： Mao Nakajima Minoru Watanabe Electrical and Electronic Engineering Shizuoka University

ISBN: (纸本)9781424445523

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of processors. Dynamic reconfiguration has two important prerequisites: fast reconfiguration and numerous reconfiguration contexts. Unfortunately, fast reconfigurations and numerous contexts share a tradeoff relation on current VLSIs. therefore, optically reconfigurable gate arrays were developed to resolve this dilemma. Optically reconfigurable gate arrays can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, optically reconfigurable gate arrays can realize rapid reconfiguration using large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. this paper presents the fastest 317-657ns reconfiguration demonstration of a 16-context optically reconfigurable gate array architecture.

关键词： Optical arrays Holography Holographic optical components Very large scale integration high speed optical techniques computer aided instruction Clocks computer architecture Reduced instruction set computing Circuits

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Memory and Interconnect Optimizations for Peta-Scale Deep Learning Systems

Memory and Interconnect Optimizations for Peta-Scale Deep Le...

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International Conference on high performance computing

作者： Swagath Venkataramani Vijayalakshmi Srinivasan Jungwook Choi Philip Heidelberger Leland Chang Kailash Gopalakrishnan IBM T. J. Watson Research Center NY USA

ISBN: (纸本)9781728145365

Hardware accelerators are a promising solution to the stringent computational requirements of Deep Neural Networks (DNNs). Ranging from low-power IP cores to server class systems, various accelerator architectures with high TOPS/W peak processing efficiencies and flexibility to execute different DNN topologies have been proposed. Prior efforts improve core utilization through better data-flows and computation sequencing, but little effort has thus far been devoted to systematically programming DNN accelerators to extract best possible system utilization, particularly for DNN training, which can be parallelized across peta-scale systems. In this work, we address the hitherto open challenge of systematically mapping computations onto Peta-scale accelerator systems, comprising many (thousands of) processing cores spanning many chips, while maximizing overall system performance. We achieve this by characterizing the design space of possible mapping configurations, building a detailed performance model that incorporates every computation and data-transfer involved in DNN training, and using a design space exploration tool called DEEPSPATIALMATRIX to identify the performance optimal configuration. We highlight 4 key optimizations built within DEEPSPATIALMATRIX - hybrid data-model parallelism, inter-layer memory reuse, time-step pipelining, and dynamic spatial minibatching - each of which improve system utilization by carefully managing the available memory capacity and interconnect bandwidth to balance the compute vs. communication costs. On a 8-peta-FLOP accelerator system, we demonstrate 1.36×-32× improvement in training performance through our design space exploration and optimizations across image recognition (VGG16, ResNet50) and machine translation (GNMT) DNN models.

关键词： Parallel processing Training Optimization Computational modeling computer architecture Convolution Data models

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Tarantula: a vector extension to the alpha architecture

Tarantula: a vector extension to the alpha architecture

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Annual International symposium on computer architecture, ISCA

作者： R. Espasa F. Ardanaz J. Emer S. Felix J. Gago R. Gramunt I. Hernandez T. Juan G. Lowney M. Mattina A. Seznec Compaq–UPC Microprocessor Lab Universitat Politècnica Catalunya Barcelona Spain Alpha Development Group Compaq Computer Corporation Shrewsbury MA Compaq UPC Microprocessor Laboratory Universitat Poliltècnica de Catalunya Barcelona Spain Alpha Development Group Compaq Computer Corporation Shrewsbury MA USA

Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor. Tarantula adds to the EV8 core a vector unit capable of 32 double-precision flops per cycle. the vector unit fetches data directly from a 16 MByte second level cache with a peak bandwidth of sixty four 64-bit values per cycle. the whole chip is backed by a memory controller capable of delivering over 64 GBytes/s of raw bandwidth. Tarantula extends the Alpha ISA with new vector instructions that operate on new architectural state. Salient features of the architecture and implementation are: (1) it fully integrates into a virtual-memory cache-coherent system without changes to its coherency protocol, (2) provides high bandwidth for non-unit stride memory accesses, (3) supports gather/scatter instructions efficiently, (4) fully integrates with the EV8 core with a narrow, streamlined interface, rather than acting as a co-processor (5) can achieve a peak of 104 operations per cycle, and (6) achieves excellent "real-computation" per transistor and per watt ratios. Our detailed simulations show that Tarantula achieves an average speedup of 5X over EV8, out of a peak speedup in terms of flops of 8X. Furthermore, performance on gather/scatter intensive benchmarks such as Radix Sort is also remarkable: a speedup of almost 3X over EV8 and 15 sustained operations per cycle. Several benchmarks exceed 20 operations per cycle.

关键词： Bandwidth Instruction sets Scattering Communication system control computer architecture Bioinformatics CMOS technology Microprocessors Access protocols Coprocessors

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the ULTRAVIS System

The ULTRAVIS System

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IEEE symposium on Volume Visualization, VV

作者： Gunter Knittel Visual Computing Department Hewlett Packard Laboratories USA

this paper describes architecture and implementation of the ULTRAVIS system, a pure software solution for versatile and fast volume rendering. It provides perspective raycasting, tri-linear interpolation, on-the-fly classification using look-up tables, gradient shading (both diffuse and specular reflection), four light sources, and alpha blending. For high frame rates, early ray termination and empty space skipping are implemented. Furthermore, subsampling during motion is provided. the system accepts raw data sets of 8-bit voxels as well as pre-segmented data sets containing up to 16 different materials. For gradient shading, the gradients are precomputed and included in 32-bit voxels. Additionally, the system supports volume animation, i.e., the display of a sequence of data sets. the system was specifically designed for Pentium III CPUs, and makes extensive use of MMX and Streaming SIMD instructions. It is a multi-threaded application and thus takes advantage of multiprocessor platforms. Time-critical portions of the code have been hand-optimized in assembler. As a result, the system can achieve interactive to real-time performance. ULTRAVIS runs on the Windows NT 4.0 operating system on standard PCs.

关键词： computer architecture Software systems Interpolation Optical reflection Light sources Raw materials Animation Displays Time factors Assembly

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A way-halting cache for low-energy high-performance systems

A way-halting cache for low-energy high-performance systems

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International symposium on Low Power Electronics and Design (ISLPED)

作者： Chuanjun Zhang F. Vahid Jun Yang W. Najjar Department of Electrical Engineering University of California Riverside USA Department of Computer Science and Engineering University of California Riverside USA

Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. the look-up in the hall tag array is done in parallel with, and is no slower than, the set-index decoding. the hall tag array pre-determines which tags cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has an additional feature of using static logic only, rather than dynamic logic used in highly associative caches. We provide data from experiments on 17 benchmarks drawn from MediaBench and Spec 2000, based on our layouts in 0.18 micron CMOS technology, On average, 55% savings of memory-access related energy were obtained over a conventional four-way set-associative cache. We show that energy savings are greater than previous methods, and nearly twice that of highly-associative caches, while imposing no performance overhead and only 2% cache area overhead.

关键词： Logic arrays Energy consumption CMOS logic circuits computer science Power engineering and energy Embedded computing Microprocessors Decoding Costs Permission

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Evaluation of Convolutional Neural Networks for COVID-19 Classification on Chest X-Rays 10th

Evaluation of Convolutional Neural Networks for COVID-19 C...

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10th Brazilian Conference on Intelligent Systems, BRACIS 2021

作者： Zeiser, Felipe André Costa, Cristiano André da Ramos, Gabriel de Oliveira Bohn, Henrique Santos, Ismael Righi, Rodrigo da Rosa Graduate Program in Applied Computing Universidade do Vale do Rio dos Sinos São Leopoldo Brazil

ISBN: (纸本)9783030916985

Early identification of patients with COVID-19 is essential to enable adequate treatment and to reduce the burden on the health system. the gold standard for COVID-19 detection is the use of RT-PCR tests. However, due to the high demand for tests, these can take days or even weeks in some regions of Brazil. thus, an alternative for detecting COVID-19 is the analysis of Digital Chest X-rays (XR). Changes due to COVID-19 can be detected in XR, even in asymptomatic patients. In this context, models based on deep learning have great potential to be used as support systems for diagnosis or as screening tools. In this paper, we propose the evaluation of convolutional neural networks to identify pneumonia due to COVID-19 in XR. the proposed methodology consists of a preprocessing step of the XR, data augmentation, and classification by the convolutional architectures DenseNet121, InceptionResNetV2, InceptionV3, MovileNetV2, ResNet50, and VGG16 pre-trained with the ImageNet dataset. the obtained results for our methodology demonstrate that the VGG16 architecture presented a superior performance in the classification of XR, with an Accuracy of 85.11 %, Sensitivity of 85.25 %, Specificity of 85.16 %, F1-score of 85.03 %, and an AUC of 0.9758. © 2021, Springer Nature Switzerland AG.

关键词： COVID-19

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Structuring the execution of OpenMP applications for multicore architectures

Structuring the execution of OpenMP applications for multico...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： François Broquedis Olivier Aumage Brice Goglin Samuel thibault Pierre-Andr Wacrenier Raymond Namyst INRIA LaBRI Université Bordeaux Talence France

ISBN: (纸本)9781424464425

the now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user friendliness of shared memory on the one side, and memory access scalability and efficiency on the other side. However, to get high performance out of such machines requires a dynamic mapping of application tasks and data onto the underlying architecture. Moreover, depending on the application behavior, this mapping should favor cache affinity, memory bandwidth, computation synchrony, or a combination of these. the great challenge is then to perform this hardware-dependent mapping in a portable, abstract way. To meet this need, we propose a new, hierarchical approach to the execution of OpenMP threads onto multicore machines. Our ForestGOMP runtime system dynamically generates structured trees out of OpenMP programs. It collects relationship information about threads and data as well. this information is used together with scheduling hints and hardware counter feedback by the scheduler to select the most appropriate threads and data distribution. ForestGOMP features a highlevel platform for developing and tuning portable threads schedulers. We present several applications for which we developed specific scheduling policies that achieve excellent speedups on 16-core machines.

关键词： Multicore processing Application software computer architecture Concurrent computing Human computer interaction Scalability Bandwidth Hardware Counting circuits

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Active Flash: Out-of-core data analytics on flash storage

Active Flash: Out-of-core data analytics on flash storage

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IEEE/NASA Goddard Conference on Mass Storage Systems and Technologies, (MSST)

作者： Simona Boboila Youngjae Kim Sudharshan S. Vazhkudai Peter Desnoyers Galen M. Shipman Northeastern University USA Oak Ridge National Laboratory USA

Next generation science will increasingly come to rely on the ability to perform efficient, on-the-fly analytics of data generated by high-performance computing (HPC) simulations, modeling complex physical phenomena. Scientific computing workflows are stymied by the traditional chaining of simulation and data analysis, creating multiple rounds of redundant reads and writes to the storage system, which grows in cost with the ever-increasing gap between compute and storage speeds in HPC clusters. Recent HPC acquisitions have introduced compute node-local flash storage as a means to alleviate this I/O bottleneck. We propose a novel approach, Active Flash, to expedite data analysis pipelines by migrating to the location of the data, the flash device itself. We argue that Active Flash has the potential to enable true out-of-core data analytics by freeing up both the compute core and the associated main memory. By performing analysis locally, dependence on limited bandwidth to a central storage system is reduced, while allowing this analysis to proceed in parallel with the main application. In addition, offloading work from the host to the more power-efficient controller reduces peak system power usage, which is already in the megawatt range and poses a major barrier to HPC system scalability. We propose an architecture for Active Flash, explore energy and performance trade-offs in moving computation from host to storage, demonstrate the ability of appropriate embedded controllers to perform data analysis and reduction tasks at speeds sufficient for this application, and present a simulation study of Active Flash scheduling policies. these results show the viability of the Active Flash model, and its capability to potentially have a transformative impact on scientific data analysis.

关键词： Data analysis Computational modeling Data models Analytical models Ash computer architecture Bandwidth

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Asynchronous Multi-task Learning

Asynchronous Multi-task Learning

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IEEE International Conference on Data Mining (ICDM)

作者： Inci M. Baytas Ming Yan Anil K. Jain Jiayu Zhou Department of Computer Science and Engineering Michigan State University MI Department of Mathematics Michigan State University MI

ISBN: (纸本)9781509054749

Many real-world machine learning applications involve several learning tasks which are inter-related. For example, in healthcare domain, we need to learn a predictive model of a certain disease for many hospitals. the models for each hospital may be different because of the inherent differences in the distributions of the patient populations. However, the models are also closely related because of the nature of the learning tasks modeling the same disease. By simultaneously learning all the tasks, multi-task learning (MTL) paradigm performs inductive knowledge transfer among tasks to improve the generalization performance. When datasets for the learning tasks are stored at different locations, it may not always be feasible to transfer the data to provide a data centralized computing environment due to various practical issues such as high data volume and privacy. In this paper, we propose a principled MTL framework for distributed and asynchronous optimization to address the aforementioned challenges. In our framework, gradient update does not wait for collecting the gradient information from all the tasks. therefore, the proposed method is very efficient when the communication delay is too high for some task nodes. We show that many regularized MTL formulations can benefit from this framework, including the low-rank MTL for shared subspace learning. Empirical studies on both synthetic and real-world datasets demonstrate the efficiency and effectiveness of the proposed framework.

关键词： Optimization Hospitals Data models Predictive models Servers Sociology Statistics

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