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A greedy approach to tolerate defect cores for multimedia applications

A greedy approach to tolerate defect cores for multimedia ap...

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Embedded Systems for Real-Time Multimedia (ESTIMedia)

作者： Ke Yue Soumia Ghalim Zheng Li Frank Lockom Shangping Ren Lei Zhang Xiaowei Li Department of CS Illinois Institute of Technology Chicago IL USA Key Laboratory of CSA Institute of Computing Technology Chinese Academy of Sciences (CAS) China

Computation-intensive multimedia applications are emerging on mobile devices. System-on-Chip (SoC) offers high performance at a decreased size for these devices. SoC often integrates tens of cores and uses Network-on-Chip (NoC) as its communication infrastructure. To ensure high yield of manycore processors, core-level redundancy is often used as an effective approach to improve the reliability of manycore chips. However, when defective cores are replaced by redundant ones, the NoC topology changes. As a result, a fine-tuned application based on timing parameters given by one topology may not meet the expected timing behavior under the new one. To address this issue, we first define a metric that can measure the timing resemblance between different NoC topologies. Based on this metric, we develop a greedy algorithm to reconfigure a defect-tolerant manycore platform and form a unified application specific virtual topology on which the timing variations caused by the reconfiguration are minimized. Our simulation results clearly indicate the effectiveness of the developed algorithm.

关键词： Topology Timing Multimedia communication Network topology Greedy algorithms computer architecture

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Pixels to Phrases: Bridging the Gap with Computationally Effective Deep Learning models in Image Captioning

Pixels to Phrases: Bridging the Gap with Computationally Eff...

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International Conference on Advanced computing, ICAC

作者： K Serath Chandra Roshini Poda Ardra Vinod R Arumuga Arun Department of Computer Science and Engineering Amrita School of Computing Coimbatore Amrita Vishwa Vidyapeetham India

Image captioning combines computer vision and natural language processing using deep learning for generating descriptive image captions, transforming how we perceive and interact with visual data, enhancing comprehension, and enabling multimodal communication. this Research aims to use lightweight deep-learning models for image captioning, bridging the gap between visual understanding and caption generation. Models adopt an encoder-decoder architecture, using CNNs (VGG16, InceptionV3, DenseNet, EffcientNet, MobileNet) as encoders for extracting high-level visual features. Complementing the encoder, a recurrent neural network (RNN) such as Long-Short-Term-Memory (LSTM) serves as the decoder, generating captions word by word. the transfer learning technique is incorporated to enhance the image caption generator’s performance. this involves pretraining all the CNN models with the ImageNet dataset, followed by fine-tuning using the Flickr8k dataset specifically for caption generation. By leveraging this approach, the proposed system achieves improved captioning quality and accuracy, showcasing the significance of transfer learning in the domain of image caption generation. In addition to enhancing caption quality, this research work also focuses on reducing the caption generation time and computational complexity of the model. the proposed image generator with MobileNet and LSTM outperformed when compared with other models in all aspects with a better bleu Score of 55.15% and lesser computational complexity of 5.09 million trainable parameters.

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Generic high-Speed Design with Low-Area Implementations of Statistical Operations Based on an FPGA Device

Generic High-Speed Design with Low-Area Implementations of S...

引用

International symposium on Symbolic and Numeric Algorithms for Scientific computing (SYNASC)

作者： Mouhamad Chehaitly Jorge Querol Praveen Vummadisetty Symeon Chatzinotas SnT University of Luxembourg Luxembourg

ISBN: (数字)9798331532833

ISBN: (纸本)9798331532840

Artificial Intelligence has emerged as a transformative technology, revolutionizing numerous industries by enabling advanced automation, predictive analytics, and decision-making capabilities. For that Artificial Intelligence overruns many domains like telecommunication, smart manufacturing industry, autonomous machines, Automated Disease Diagnosis in Medical Imaging, defense, and others. On the other hand, the hardware implementation of Artificial Intelligence comes with certain challenges and constraints, especially in a critical area, which leverages machine learning algorithms and real-time data analysis to optimize production processes and improve overall efficiency. Statistical operations play a crucial role in various machine learning algorithms to understand, process data, or make predictions to optimize models. So, in this work, we developed a high-speed and low-area design and implemented statistical operations for image or signal processing using an FPGA Device. To enhance the performance, we develop different hardware architectures based on different levels of parallelism to process the statistical operations to compute the Mean, Variance, and RMS (Root Mean Square). these generic architectures work in parallel/pipeline architectures with and without memory. the proposed architectures implement an FPGA target (Intel/Altera Agilex 7: AGMH039R47A2E1V) using Altera Quartus prime pro edition version 23.4 and achieve an ultra-high throughput with low-area consumption compared to the state-of-art methods. For 480×640 image size, the mean calculation architecture involves 1498 logic registers, 1912 slice LUT, and just 29kbits memory and it operates at a maximum frequency of 406.5MHz. Additionally, for an 8×8 image size, we need 33 clock cycles to achieve the mean calculation and 33+1 clock cycles to complete the variance calculation, compared to other approaches that require more than 64 clock cycles.

关键词： Industries Machine learning algorithms computer architecture throughput Hardware Real-time systems Artificial intelligence Root mean square Field programmable gate arrays Clocks

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Energy-Efficient Scheduling for Best-Effort Interactive Services to Achieve high Response Quality

Energy-Efficient Scheduling for Best-Effort Interactive Serv...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Zhihui Du Hongyang Sun Yuxiong He Yu He David A. Bader Huazhe Zhang Tsinghua National Laboratory for Information Science and Technology Department of Computer Science and Technology Tsinghua University Beijing China School of Computer Engineering Nanyang Technological University Singapore Microsoft Research Redmonds WA USA College of Computing Georgia Institute of Technology Atlanta GA USA School of Information and Communication Engineering Beijing University of Posts and Telecommunications Beijing China

ISBN: (纸本)9781467360661

high response quality is critical for many best-effort interactive services, and at the same time, reducing energy consumption can directly reduce the operational cost of service providers. In this paper, we study the quality-energy tradeoff for such services by using a composite performance metric that captures their relative importance in practice: Service providers usually grant top priority to quality guarantee and explore energy saving secondly. We consider scheduling on multicore systems with core-level DVFS support and a power budget. Our solution consists of two steps. First, we employ an equal sharing principle for both job and power distribution. Specifically, we present a “Cumulative Round-Robin” policy to distribute the jobs onto the cores, and a “Water-Filling” policy to distribute the power dynamically among the cores. Second, we exploit the concave quality function of many best-effort applications, and develop Online-QE, a myopic optimal online algorithm for scheduling jobs on a single-core system. Combining the two steps together, we present a heuristic online algorithm, called DES (Dynamic Equal Sharing), for scheduling best-effort interactive services on multicore systems. the simulation results based on a web search engine application show that DES takes advantage of the core-level DVFS architecture and exploits the concave quality function of best-effort applications to achieve high service quality with low energy consumption.

关键词： Multicore processing Schedules Heuristic algorithms Optimal scheduling Energy consumption Dynamic scheduling

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SIMD Extensions - A Historical Perspective

SIMD Extensions - A Historical Perspective

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International symposium for Design and Technology of Electronics Packages (SIITME)

作者： Diana Vuţă-Popescu Ionuţ Cătălin Antofi Cătălin Bogdan Ciobanu Csaba Zoltán Kertész Transilvania University of Braşov Romania National Institute of Research and Development in Microtechnologies Bucharest Romania

ISBN: (数字)9798331539511

ISBN: (纸本)9798331539528

this work provides a historical perspective on the Single Instruction Multiple Data (SIMD) instruction set extensions. SIMD extensions are crucial in modern processors for handling large amounts of data and exploiting data-level parallelism. the effectiveness of SIMD optimizations is influenced by several factors, including data size. Modern SIMD extensions support both integer and floating point numbers. Furthermore, sub-word parallelism is exploited, improving performance when processing narrow data types. We provide an overview of the SIMD extensions for SPARC (VIS), x86 (MMX, SSE, AVX, AVX2, AVX-512, AMX), PowerPC (AltiVec), MIPS (MDMX), Arm (Neon, SVE, SVE2, SME) and RISC-V (RVV) architectures. Furthermore, we provide examples of modern processors featuring SIMD extensions for x86, Arm and RISC-V architectures.

关键词： Neon Single instruction multiple data Instruction sets high performance computing Computational modeling computer architecture Machine learning Hardware Optimization Electronics packaging

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On the Development of a Runtime Reconfigurable Multicore System-on-Chip

On the Development of a Runtime Reconfigurable Multicore Sys...

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Euromicro symposium on Digital System Design

作者： Andrea Cazzaniga Gianluca Durelli Christian Pilato Donatella Sciuto Marco D. Santambrogio Dipartimento di Elettronica e Informazione Politecnico di Milano Italy Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology MA USA

Over the last years, several research groups have built reconfigurable systems to obtain high performance at low cost by specializing the computing engine to the computation task. Nowadays, FPGA-based multi-core architectures and reconfigurable computing are widely used for embedded systems, even if the development of complete and efficient solutions on this kind of devices is still quite a complex task. Within this context, what seems to be neglected so far is the combination of a multicore architecture with reconfigurable abilities to vary at runtime not only the hardware components but also the number of the available processors. the variation of the number of processors available on the device can be performed in a dynamic way by using the proposed solution, based on a partial bitstream, characterized by the presence of a reconfigurable system in which both components and component memories can be reconfigured at run-time. this paper presents a study of the viability of making a scalable and flexible multicore System-on-Chip (MPSoC) based on customizable reconfigurable processors, called Multi-Adaptive Reconfigurable Core (MARC), providing the communication infrastructures and the memory management required to create such a complex system-on-chip.

关键词： Multicore processing Runtime Hardware Motion detection System-on-a-chip Software

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TianheStar: Orchestrating SSSP Applications on Tianhe Supercomputer

TianheStar: Orchestrating SSSP Applications on Tianhe Superc...

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IEEE/ACM International symposium on Cluster computing and the Grid (CCGRID)

作者： Xinbiao Gan Qian Tang Feng Xiong Shijie Li Bo Yang Tiejun Li School of Computer National University of Defense Technology

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

computing single-source shortest paths (SSSP) is one of the fundamental problems in graph theory and is also essential for data-intensive applications. As the potential of artificial intelligence (AI) continues to be explored, and with the advent of exascale supercomputing, there is a growing need for an extremely fast graph engine for SSSP applications. Current distributed SSSP engines for large-scale graph applications, unfortunately, often exhibit poor efficiency when running on supercomputers. In this paper, we introduce TianheStar, an ultra-fast SSSP engine designed specifically for graph search on the Tianhe supercomputer. TianheStar effectively minimizes communication costs and establishes a new balance between computation and communication. the key idea of TianheStar is to leverage network topology information for performing topology-aware message aggregation and architecture-aware group communication. these two techniques effectively reduce the number of messages and the average number of communication hops, respectively. We validate TianheStar using Graph500, a widely adopted benchmark for graph search on supercomputers. Extensive evaluation demonstrates that, compared to the state-of-the-art solutions, TianheStar achieves a remarkable performance improvement. We have deployed TianheStar on the latest Tianhe supercomputer and secured the top position in the latest Graph500. We achieved an outstanding performance of 23,021 GTEPS (Giga Traversed Edges Per Second) for SSSP using 4096 nodes. Furthermore, we have delved into real-world graphs representing the USA road networks and conducted computations to determine the shortest paths between vertices. Our experimental results demonstrate that TianheStar can traverse the USA road network, comprising over 58,333,344 edges, in less than 0.1 second on the Tianhe supercomputer. this performance represents a speedup of over a thousand times compared to parallel shortest-path graph computations on the Aziz supercompu

关键词： Cloud computing Costs Network topology Roads high performance computing Benchmark testing Supercomputers Graph theory Artificial intelligence Engines

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Modulo schedule buffers

Modulo schedule buffers

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： M.C. Merten W.-M.W. Hwu Center for Reliable and High Performance Computing University of Illinois Urbana IL USA

As VLIW/EPIC processors are increasingly used in realtime, signal-processing, and embedded applications, the importance of. minimizing code size and reducing power is growing. this paper describes a new architectural mechanism, called the Modulo Schedule Buffers, that provides an elegant interface for the execution of modulo scheduled loops. While the performance is similar to that of kernel-only modulo scheduling, this mechanism has a number of advantages, including minimal code expansion. Rather than generating fully-scheduled kernels, the compiler generates a sequential form of the modulo scheduled loop body. Using the sequential form, the hardware internally synthesizes the prologue, kernel, and epilogue. In addition, while loops can be scheduled with fewer constraints and fewer explicit prologues/epilogues than with existing mechanisms. Because the hardware controls loop execution, the burden of modulo schedule loop control is lifted from the predicate register file, allowing for a less rigorous predication implementation. Finally, hardware control limits the interrupt latency when using the EQ explicit latency model to the execution latency of one iteration, rather than the whole loop invocation.

关键词： Kernel Pipeline processing Processor scheduling Hardware Registers Delay computer architecture VLIW Application software Software maintenance

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FPGA-QHAR: throughput-Optimized for Quantized Two-Stream Human Action Recognition on the Edge

FPGA-QHAR: Throughput-Optimized for Quantized Two-Stream Hum...

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International symposium on high Capacity Optical Networks and Enabling Technologies, HONET

作者： Azzam Alhussain Mingjie Lin College of Engineering and Computer Science University of Central Florida Orlando Florida USA

Accelerating Human Action Recognition (HAR) efficiently for real-time surveillance and robotic systems on edge chips remains a challenging research field, given its high computational and memory requirements. this paper proposed an integrated end-to-end HAR scalable HW/SW accelerator co-design based on an enhanced 8-bit quantized Two-Stream SimpleNet-PyTorch CNN architecture. Our network accelerator was trained on UCF101 and UCF24 datasets and implemented on edge SoC-FPGA. Our development uses partially streaming dataflow architecture to achieve higher throughput versus network design and resource utilization trade-off. We also fused all convolutional, batch-norm, and ReLU operations into a single homogeneous layer and utilized the Lucas-Kanade motion flow method to enable a high parallelism accelerator design and optimized on-chip engine computing. Furthermore, our proposed methodology achieved nearly 81 % prediction accuracy with an approximately 24 FPS real-time inference throughput at 187MHz on ZCU104, which is 1.7x - 1.9x higher than the prior research. Lastly, the designed framework was benchmarked against several hardware chips for higher throughput and performance measurements and is now available as an open-source project on Github for training and implementation on edge platforms.

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A New highly Parallel Non-Hermitian Eigensolver 14

A New Highly Parallel Non-Hermitian Eigensolver

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Simulation Multi-Conference

作者： Ping Tak Peter Tang James Kestyn Eric Polizzi Intel Corporation Santa Clara CA University of Massachusetts Amherst MA

ISBN: (纸本)9781632662163

Calculating portions of eigenvalues and eigenvectors of matrices or matrix pencils has many applications. An approach to this calculation for Hermitian problems based on a density matrix has been proposed in 2009 and a software package called FEAST has been developed. the density-matrix approach allows FEAST's implementation to exploit a key strength of modern computer architectures, namely, multiple levels of parallelism. Consequently, the software package has been well received and subsequently commercialized. A detailed theoretical analysis of Hermitian FEAST has also been established very recently. this paper generalizes the FEAST algorithm and theory, for the first time, to tackle non-Hermitian problems. Fundamentally, the new algorithm is basic subspace iteration or Bauer bi-iteration, except applied with a novel accelerator based on Cauchy integrals. the resulting algorithm retains the multi-level parallelism of Hermitian FEAST, making it a valuable new tool for large-scale computational science and engineering problems on leading-edge computing platforms.

关键词： Software packages Hermitian conjugate Density matrix computer architecture Cauchy parallelism Synclitism matrices instruction-level parallelism

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