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OSIRIS-SR: A Safety Ring for self-healing distributed composite service execution

OSIRIS-SR: A Safety Ring for self-healing distributed compos...

引用

SEAMS International Workshop on Software Engineering for Adaptive and Self-Managing Systems, ICSE

作者： Nenad Stojnić Heiko Schuldt Department of Mathematics and Computer Science University of Basel Switzerland

the advent of service-oriented architectures has strongly facilitated the development and deployment of large-scale distributed applications. the middleware for orchestrating applications that consist of several distributed services has to be inherently distributed as well, in order to provide a high degree of scalability and to avoid any single point of failure. Self-healing execution of composite services requires replicated control metadata and instance data in a way that does not affect adaptivity and elasticity of the middleware. In this paper, we present OSIRIS-SR, a decentralized approach to self-healing composite service execution in a distributed environment. OSIRIS-SR exploits dedicated node monitors, organized in a self-organizing Safety Ring, for the replication of control data. Moreover, OSIRIS-SR leverages virtual stable storage for managing composite service instance data in a robust way. We present the architecture of OSIRIS-SR's Safety Ring and discuss how it provides self-healing composite service execution. the performance evaluation shows that the additional gain in robustness has only marginal effects on the scalability characteristics of the system.

关键词： Peer to peer computing Safety Monitoring Robustness Distributed databases Middleware

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Vacuum packing: extracting hardware-detected program phases for post-link optimization

Vacuum packing: extracting hardware-detected program phases ...

引用

IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： R.D. Barnes E.M. Nystrom M.C. Merten W.W. Hwu Center for Reliable and High-Performance Computing Department of Electical and Computer Engineering University of Illinois Urbana-Champaign USA

this paper presents Vacuum Packing, a new approach to profile-based program optimization. Instead of using traditional aggregate or summarized execution profile weights, this approach uses a transparent hardware profiler to automatically detect execution phases and record branch profile information for each new phase. the code extraction algorithm then produces code packages that are specially formed for their corresponding phases. the algorithm compensates for the incomplete and often incoherent branch profile information that arises due to the nature of hardware profilers. the technique avoids unnecessary code replication by focusing on hot code, making efficient connections between the original code and the new code, linking code packages at select points to facilitate phase transitions, and providing a platform for efficient optimization. We demonstrate that using a concise set of profile information from a hardware profiler, we can generate code packages, specialized for each phase of execution, that capture more than 80% of the average total program execution. We further show that the approach is very effective in extracting code regions that capture the phasing behavior of programs, that the code size increase is moderate, and that the code regions benefit from sample optimizations.

关键词： Data mining Packaging Reliability engineering Aggregates Phase detection Joining processes computer architecture Java Emulation Libraries

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MCC: A Load Balancing and Deadlock Free Interconnect Network for Cache Coherent Chip Multiprocessors

MCC: A Load Balancing and Deadlock Free Interconnect Network...

引用

IEEE International Conference on Computational Science and Engineering, CSE

作者： Liwei Chen Guangfei Zhang Huandong Wang Wenxiang Wang Ling Li Hua Jing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

As the number of cores in chip multiprocessors (CMPs) increases, network-on-chip (NoC) has become a major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlock. We implement MCC on a 16-core CMPs, and evaluate the power and performance using universal workloads. the experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels.

关键词： System recovery System-on-a-chip Program processors Bandwidth Load management throughput Scalability

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Model Compression on Faulty Array-based Neural Network Accelerator

Model Compression on Faulty Array-based Neural Network Accel...

引用

Pacific Rim International symposium on Dependable computing

作者： Krishna Teja Chitty-Venkata Arun K. Somani Iowa State University Ames Iowa

ISBN: (数字)9781728180038

ISBN: (纸本)9781728180045

Due to an increase in the size of Deep Neural Networks (DNNs), special purpose hardware has gained prominence to accelerate the forward pass of the network like Google's Tensor Processing Unit (TPU) and Eyeriss. the heart of these accelerators is a Matrix Multiplication unit, which is based on systolic array architecture. this array processor has a grid-like structure, made of individual Processing Elements (PEs) that can be extended along row and column. A lot of work has been done on the computing array implementation and its reliability concerns in the past. However, their fault tolerance perspective with respect to DNNs is not yet fully understood with a fault model. We, in this paper, first present a fault model i.e., different sequences in which faults can occur on the array. We classify the fault modes into random, row, and column, and study their impact on the accuracy of DNNs followed by overheads of the mitigation strategies. Pruning is a process of removing redundant parameters in the model to decrease the network size for efficient performance. Although several pruning techniques have been developed to reduce the inference time on general-purpose and special-purpose systems, model compression (pruning) under faulty scenario has not yet been explored. In the second part of our work, we co-design a Fault based and Array size based Pruning (FPAP) algorithm with an intent of bypassing the faults and removing the internal redundancy at the same time for efficient inference. We compare our method with recent pruning methods under different fault scenarios and array sizes. We achieve a mean speedup of 4.2x where the baselines achieved 1.6x on ConvNet, NiN, AlexNet, VGG16 over Eyeriss in the case of random faults.

关键词： Hardware computer architecture Arrays Inference algorithms Biological neural networks Transient analysis Redundancy

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DRL Based on Priority Evaluation for Collaborative Perception Task Offloading in Internet of Vehicles

DRL Based on Priority Evaluation for Collaborative Perceptio...

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International Conference on Wireless Communications and Signal Processing (WCSP)

作者： Xiaoge Huang Caiwei Yu Wenjing Li ChengChao Liang Qianbin Chen School of Communications and Information Engineering Chongqing University of Posts and Telecommunications Chongqing China

ISBN: (数字)9798350390643

ISBN: (纸本)9798350390650

With the explosive growth of the Internet of Vehicles (IoVs), autonomous driving has received numerous attention from academia and industry. However, the limited perceivable range of a single connected and automated vehicle (CAV) leads to missing real-time road condition information, which affects driving safety. Meanwhile, due to the complexity of applications and dependencies between tasks, perception tasks require high computing capability and low latency. However, a CAV has limited local computing capability, it is necessary to offload perception tasks to edge for processing. therefore, to improve perception coverage and reduce perception task processing la-tency, we propose a Priority Evaluation and Deep Reinforcement Learning Task Offloading (PDRTO) algorithm. Firstly, a dual layer IoVs architecture for task offloading is constructed to improve the perception coverage of CAVs and achieve safe driving through collaborative perception among CAVs. At the same time, considering task dependency and CAV's mobility, a multi-CAV collaborative perception task graph is proposed to model the optimization problem of minimizing the processing delay of perception subtasks. then, the optimization problem is transformed into a multi-objective mixed integer optimization problem, and solved by the proposed PDRTO algorithm to minimize the processing delay of perception tasks. Finally, the simulation results show that the proposed algorithm outperforms other compared algorithms in improving CAV perception cover-age and reducing perception task latency.

关键词： Wireless communication Simulation Collaboration Signal processing algorithms computer architecture Signal processing Deep reinforcement learning Delays Optimization Internet of Vehicles

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MemTorch: A Simulation Framework for Deep Memristive Cross-Bar architectures

MemTorch: A Simulation Framework for Deep Memristive Cross-B...

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IEEE International symposium on Circuits and Systems (ISCAS)

作者： Corey Lammie Mostafa Rahimi Azghadi College of Science and Engineering James Cook University Queensland 4814 Australia

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Memristive devices arranged in cross-bar architectures have shown great promise to facilitate the acceleration and improve the power efficiency of Deep Learning (DL) systems for deployment in resource-constrained platforms, such as the Internet-of-things (IoT) edge devices. these cross-bar architectures can be used to implement various in-memory computing operations, such as Multiply-Accumulate (MAC) and convolution, which are used extensively in Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs). Currently, there is a lack of an open source, general, high-level simulation platform that can fully integrate any behavioral or experimental memristive device model into cross-bar architectures. this paper presents such a framework named MemTorch, which integrates directly with the well-known PyTorch Machine Learning (ML) library. To demonstrate an example practical use of MemTorch, we use it to simulate the performance degradation that non-ideal devices introduce to a typical Memristive DNN (MDNN) implementing VGG-16 for CIFAR-10. Our open source 1 MemTorch framework can be used by circuit and system designers to conveniently build customized large-scale simulation platforms, as a preliminary step before circuit-level realization.

关键词： performance evaluation Memristors Graphics processing units Python C++ languages computer architecture Mathematical model

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ASNet: Introducing Approximate Hardware to high-Level Synthesis of Neural Networks

ASNet: Introducing Approximate Hardware to High-Level Synthe...

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International symposium on Multiple-Valued Logic

作者： Saman Froehlich Lucas Klemmer Daniel Große Rolf Drechsler DFKI GmbH and Group of Computer Architecture University of Bremen Germany

ISBN: (数字)9781728154060

ISBN: (纸本)9781728154077

Approximate computing is a design paradigm which makes use of error tolerance inherent to many applications in order to trade off accuracy for performance. One classic example for such an application is machine learning with Neural Networks (NNs). Recently, LeFlow, a high-Level Synthesis (HLS) flow for mapping Tensorflow NNs into hardware has been proposed. the main steps of LeFlow are to compile the Tensorflow models into the LLVM Intermediate Representation (IR), perform several transformations and feed the result into a HLS tool. In this work we take HLS-based NN synthesis one step further by integrating hardware approximation. To achieve this goal, we upgrade LeFlow such that (a) the user can specify hardware approximations, and (b) the user can analyze the impact of hardware approximation already at the SW level. Based on the exploration results which satisfy the NN quality expectations, we import the chosen approx. HW components into an extended version of the HLS tool to finally synthesize the NN to Verilog. the experimental evaluation demonstrates the advantages of our proposed ASNet for several NNs. Significant area reductions as well as improvements in operation frequency are achieved.

关键词： Artificial neural networks Tools Hardware design languages Generators Libraries Hardware Complexity theory

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Cryogenic Alternative: CMOS Versus Dynamic-Based Logic

Cryogenic Alternative: CMOS Versus Dynamic-Based Logic

引用

Midwest symposium on Circuits and Systems (MWSCAS)

作者： Ali H. Hassan Puneet Gupta Sudhakar Pamarti Chih-Kong Ken Yang Department of Electrical and Computer Engineering University of California Los Angeles USA

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

Next-generation data-center computing requires high-performance energy-efficient servers. One counterintuitive approach to reduce energy is to lower the temperature of the processing elements even down to cryogenic temperatures of liquid nitrogen. If the processing load is reduced dramatically, the net energy cost is lower even considering the corresponding cooling cost. Operating at such temperatures will require one to utilize optimized devices and new circuit techniques. One technique is scaling down the threshold voltage of transistors which in turn allows the supply voltage to scale. Another technique is to leverage the reduced leakage and to use dynamic-based logic for processing. this paper utilizes a low-temperature low-threshold (LTLVT) model of a 14-nm FinFET device calibrated with measurements for cryogenic computing. A demonstration of a 16-bit NP-CMOS adder is presented for an energy-delay optimization up to 20X at 77K compared to 330K.

关键词： Costs Cooling Liquid nitrogen FinFETs threshold voltage Energy efficiency Logic

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Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only) 05

Accelerating mutual information-based 3D medical image regis...

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Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

作者： Jianchun Li Christos Papachristou Raj Shekhar Case Western Reserve University Cleveland OH University of Maryland Baltimore MD

ISBN: (纸本)9781595930293

Mutual information-based 3D image Registration algorithm is shown to be an accurate, robust and more general registration method for medical image processing. However, its potential application in clinic is jeopardized by its high computational costs. Like many other 3D imaging algorithms, 3D registration needs to process vast amount of image data. the intrinsic computing characteristics of the mutual information-based registration algorithm make it even more difficult to manage and cache the input data. In this paper, we introduce our FPGA-based computing platform and detail its application in accelerating the mutual information-based 3D image registration. this platform is designed to accelerate a series of 3D medical imaging algorithms dominated by local operations. It is a System-on-Chip (SoC) architecture with an intelligent data caching system for efficient data fetching and buffering. A reconfigurable multi-pipeline execution unit in the platform is designed to perform high-speed parallel computation. this unit can be customized according to different algorithm requirements to achieve high performance. the simulation results for accelerating the mutual information based registration with our platform show that a speed-up of about 30 can be achieved when compared to a single-CPU computer. Moreover, the platform can be easily reconfigured to accelerate other 3D medical imaging algorithms.

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A Hybrid Deep Transfer Learning Approach For the Detection Of Vector-Borne Diseases

A Hybrid Deep Transfer Learning Approach For The Detection O...

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International Conference on Contemporary computing and Informatics (IC3I)

作者： Inderpreet Kaur Amanpreet Kaur Sandhu Yogesh Kumar UIC Chandigarh University Gharuan Mohali India Department of CSE School of Technology Pandit Deendayal Energy University Gandhinagar Gujarat India

Vector-borne diseases considerably impact the worldwide population’s health and economic well-being. However, training deep-learning models requires significant time and training data. therefore, a unique hybrid transfer learning approach was proposed for detecting vector-borne diseases (VBD) to solve these issues while retaining high accuracy. In the first phase, malaria and Lyme benchmark datasets were obtained. then VGG16, VGG19, MobileNetV2, and DenseNet 169 were compared to the hybrid model results (MobileNetV2+DenseNet 169). the effectiveness of the hybrid transfer learning method was evaluated using several performance measures, namely precision, loss, accuracy, AUC and RMSE. On the malaria dataset, the proposed model (MobileNetV2+DenseNet 169) achieved the most excellent classification accuracy of 99.9%, and on the Lyme dataset, 99.3%.

关键词： Training Biological system modeling Computational modeling Transfer learning Training data computer architecture Predictive models

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