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Inter-Scanner Harmonization of high Angular Resolution DW-MRI Using Null Space Deep Learning

Inter-Scanner Harmonization of High Angular Resolution DW-MR...

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21st International Conference on Medical Image computing and computer-Assisted Intervention (MICCAI) / 8th Eurographics Workshop on Visual computing for Biology and Medicine (VCBM) / International Workshop on Computational Diffusion MRI (CDMRI)

作者： Nath, Vishwesh Parvathaneni, Prasanna Hansen, Colin B. Hainline, Allison E. Bermudez, Camilo Remedios, Samuel Blaber, Justin A. Schilling, Kurt G. Lyu, Ilwoo Janve, Vaibhav Gao, Yurui Stepniewska, Iwona Rogers, Baxter P. Newton, Allen T. Davis, L. Taylor Luci, Jeff Anderson, Adam W. Landman, Bennett A. Vanderbilt Univ EECS Nashville TN 37203 USA Vanderbilt Univ BME Nashville TN 37203 USA Vanderbilt Univ Biostat Nashville TN 37203 USA Middle Tennessee State Univ CS Murfreesboro TN 37132 USA Vanderbilt Univ Psychol Nashville TN 37203 USA Vanderbilt Univ VUIIS Nashville TN 37232 USA Vanderbilt Univ VUMC Nashville TN 37203 USA Univ Texas Austin BME Austin TX 78712 USA

ISBN: (纸本)9783030058319;9783030058302

Diffusion-weighted magnetic resonance imaging (DW-MRI) allows for non-invasive imaging of the local fiber architecture of the human brain at a millimetric scale. Multiple classical approaches have been proposed to detect both single (e.g., tensors) and multiple (e.g., constrained spherical deconvolution, CSD) fiber population orientations per voxel. However, existing techniques generally exhibit low reproducibility across MRI scanners. Herein, we propose a data-driven technique using a neural network design which exploits two categories of data. First, training data were acquired on three squirrel monkey brains using ex-vivo DW-MRI and histology of the brain. Second, repeated scans of human subjects were acquired on two different scanners to augment the learning of the network proposed. To use these data, we propose a new network architecture, the null space deep network (NSDN), to simultaneously learn on traditional observed/truth pairs (e.g., MRI-histology voxels) along with repeated observations without a known truth (e.g., scan-rescan MRI). the NSDN was tested on twenty percent of the histology voxels that were kept completely blind to the network. NSDN significantly improved absolute performance relative to histology by 3.87% over CSD and 1.42% over a recently proposed deep neural network approach. More-over, it improved reproducibility on the paired data by 21.19% over CSD and 10.09% over a recently proposed deep approach. Finally, NSDN improved generalizability of the model to a third in-vivo human scanner (which was not used in training) by 16.08% over CSD and 10.41% over a recently proposed deep learning approach. this work suggests that data-driven approaches for local fiber reconstruction are more reproducible, informative, precise and offer a novel, practical method for determining these models.

关键词： Diffusion HARDI DW-MRI Null space CSD Harmonization Inter-scanner Deep learning Histology

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Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: the LDPC Decoder Case

Shortening Design Time through Multiplatform Simulations wit...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： G. Falcao M. Owaida D. Novo M. Purnaprajna N. Bellas C.D. Antonopoulos G. Karakonstantis A. Burg P. Ienne Instituto de Telecomunicações Department of Electrical and Computer Engineering University of Coimbra Portugal Department of Computer and Communications Engineering University of Thessaly Greece École Polytechnique Fédérale de Lausanne Switzerland

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bit width and data representation. this is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on Open CL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. Open CL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpen CL (Silicon to Open CL), a tool that automatically converts Open CL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified Open CL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3× faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

关键词： Kernel Parity check codes Field programmable gate arrays Computational modeling Decoding Hardware Algorithm design and analysis

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An Optimal Wireless Transmission Strategy based on Coherent Beamforming and Successive Interference Cancellation for Edge computing

An Optimal Wireless Transmission Strategy based on Coherent ...

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International Conference on Mobile Ad-hoc and Sensor Networks, MSN

作者： Zhehao Li Lei Shi Yi Shi Yuqi Fan Zhenchun Wei Liaoyuan Wu School of Computer Science and Information Engineering HeFei University of Technology Hefei China Ministry of Education Engineering Research Center of Safety Critical Industrial Measurement and Control Technology Hefei China Intelligent Automation Inc. 15400 Calhoun Drive Rockville USA

ISBN: (数字)9781728199160

ISBN: (纸本)9781728192369

In general, edge devices and edge servers in edge computing environment communicate with each other by wireless network, which put forward a high requirement for end-to-end wireless communication performance. In this paper, we propose an optimal strategy by combining the coherent beamforming (CB) technique and the successive interference cancellation (SIC) technique for improving the performance of the edge device communications. CB technique can be used for expanding the transmitter's transmitting range, while SIC technique can be used for improving the receiver's receiving ability. However, when these two techniques are used jointly, interference will occur between transmitters and receivers, which makes the CB-SIC strategy hard to be designed. We first give the mathematical model based on CB-SIC and show it is difficult to solve directly. then, we design a heuristic algorithm called time slot loop allocation (TSLA) algorithm. TSLA is based on greedy strategy to obtain an approximate optimal solution. By using TSLA, the whole scheduling time will be divided into many time slots. In each time slot, we try to make as many edge devices as possible to transmit data to the server. these can increase the overall data throughput. In simulation, we compare CB-SIC wireless network with CB only, SIC only, and traditional multi-hop network. Simulation results show that the TSLA algorithm can improve the end-to-end communication performance in edge computing environment.

关键词： performance evaluation Silicon carbide Heuristic algorithms Wireless networks throughput Servers Edge computing

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Acacia-RDF: An X10-Based Scalable Distributed RDF Graph Database Engine

Acacia-RDF: An X10-Based Scalable Distributed RDF Graph Data...

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IEEE International Conference on Cloud computing, CLOUD

作者： Miyuru Dayarathna Isuru Herath Yasima Dewmini Gayan Mettananda Sameera Nandasiri Sanath Jayasena Toyotaro Suzumura WSO2 Inc. University of Moratuwa Dept of Computer Science & Engineering University of Moratuwa JST CREST The University of Tokyo

Linked data mining has become one of the key questions in high performance graph mining in recent years. However, the existing Resource Description Framework (RDF) database engines are not scalable and are less reliable in heterogeneous clouds. In this paper we describe the design and implementation of Acacia-RDF which is a scalable distributed RDF graph database engine developed with X10 programming language to solve this issue. Acacia-RDF partitions the RDF data sets into subgraphs following vertex cut paradigm. the partitioned data sets are persisted on secondary storage across X10 places. We developed a scalable SPARQL (an RDF query language) processor for Acacia-RDF which operates on top of partitioned RDF data. Furthermore, we designed and implemented a replication based fault tolerance mechanism for Acacia-RDF. We present performance results gathered from Acacia with different scales of LUBM (Lehigh University Benchmark) RDF benchmark data sets. We make a comparison of Acacia-RDF's performance against Neo4j graph database server. From the scalability experiments conducted upto 16 X10 places, we observed that Acacia-RDF scales well with LUBM data sets. Acacia-RDF reported less than ten seconds elapsed times on 16 places for running the first and the third queries of the LUBM benchmark on LUBM 160 universities data set with 3.6 million vertices and 28.5 million edges which was 1.7GB in size. through this work we describe and demonstrate the use of X10 language for development of scalable RDF graph data management systems.

关键词： Resource description framework Distributed databases Engines Fault tolerance Fault tolerant systems Servers computer architecture

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CCSF: Clustered Client Selection Framework for Federated Learning in non-IID Data 23

CCSF: Clustered Client Selection Framework for Federated Lea...

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Proceedings of the IEEE/ACM 16th International Conference on Utility and Cloud computing

作者： Aissa Hadj Mohamed Allan M de Souza Joahannes B D Da Costa Leandro A Villas Julio Cesar Dos Reis UNICAMP Campinas BR Institute of Computing UNICAMP Campinas BR

ISBN: (纸本)9798400702341

Federated Learning (FL) is a distributed approach where numerous devices train a shared global model for Machine Learning (ML) tasks. At every training round, the client devices must share their new local gradients with the central server to update the global model. Hence, FL requires high communication costs in terms of bandwidth and the number of messages exchanged between FL clients and the central server, leading to many issues, such as communication bottlenecks and scaling in the network. Consequently, having all devices participating in every training round is not practical. Moreover, the devices' local datasets are usually not Independent and Identically Distributed (IID), posing additional challenges for training the global model. In this sense, we introduce a Clustered Client Selection Framework (CCSF) to decrease the overall communication costs for training an ML model in the FL environment. CCSF clusters the client devices and employs a biased client selection strategy with two main objectives: (i) reducing the number of devices training at every round; and (ii) the number of rounds required to reach convergence. Our experimental evaluations, conducted on two well-known datasets, MNIST and MotionSense, show that CCSF is highly efficient, where the clients' local datasets can be grouped into homogeneous clusters. In MNIST, CCSF reaches an accuracy score above 60% in less than 50 rounds compared to FedAvg at 50% after 100 rounds. the performance gap is wider in the MotionSense data. CCSF reaches an accuracy score of 70% in a little more than 20 training rounds compared to FedAvg below 30% of accuracy in the first 100 FL rounds.

关键词： federated learning

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MacSim: A MAC-Enabled high-performance Low-Power SIMD architecture

MacSim: A MAC-Enabled High-Performance Low-Power SIMD Archit...

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Euromicro symposium on Digital System Design

作者： Tong Geng Luc Waeijen Maurice Peemen Henk Corporaal Yifan He Eindhoven University of Technology The Netherlands Xiamen University of Technology China

Single-Instruction-Multiple-Data (SIMD) architectures, which exploit data-level parallelism (DLP), are widely used to achieve high-performance and low-power computing. In most of streaming applications, such as CNN-based detection and recognition, color space conversion and various kinds of filters, multiply-accumulate is one of the most important and expensive operations to be executed. In this paper, we propose a high-performance low-power SIMD architecture with advanced multiply accumulator (MAC) support (MacSim) to improve the computational efficiency. In addition, a smart loop tiling scheme is proposed. To support this tiling even further, the MAC unit is equipped with multiple accumulator registers. According to the Design Space Exploration (DSE) of the proposed MAC unit, a MAC instance with four accumulator registers (MAC4reg) is selected as a good choice for target kernels. In this paper, a 64-PE 16-bit (processing element) SIMD instance without MAC support is taken as the baseline. For a head-to-head comparison, a 64-PE 16-bit SIMD with MAC4reg (MacSim4) and the baseline SIMD are all implemented in HDL and synthesized with a TSMC 40nm low-power library. Five streaming application kernels are mapped to both architectures. Our experimental results show with MAC4reg the runtime and energy consumption are reduced up to 38% and 42% respectively. Besides, a 4-layer CNN-based detection application is also fully mapped onto the proposed MacSim4. Working at 950MHz, MacSim4 reaches a throughput of 62.4 GOPS, which meets the requirement of real-time (720P HD, 30fps) detection. the energy consumption per PE per operation is very low, 4.7pJ/Op excluding SRAM (Static Random Access Memory) and 4.8pJ/Op including a 2k-entry SRAM bank. As a prototype, the proposed SIMD is mapped into an FPGA and can run all the kernels.

关键词： Registers computer architecture Kernel Parallel processing Energy consumption VLIW Pipelines

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Ensemble Fusion: Skin Cancer Detection using ResNet, EfficientNet, and VGG architectures

Ensemble Fusion: Skin Cancer Detection using ResNet, Efficie...

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International Conference on computing and Networking Technology (ICCNT)

作者： Saksham thakur Sangeeta Sharma Computer Science and Engineering National Institute of Technology Hamirpur Himachal Pradesh India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Skin cancer detection is crucial for timely intervention and improved patient outcomes. this study addresses the challenge of early detection accuracy through the utilization of advanced machine learning techniques. Leveraging the HAM1000 dataset, comprising high-resolution dermatoscopic images, rigorous preprocessing techniques were applied to enhance image quality and feature extraction. Our methodology involved training an ensemble model incorporating state-of-the-art architectures such as ResNet, EfficientNet, and VGG16. this ensemble approach harnesses the diverse capabilities of these models, leveraging their strengths in feature representation and *** results demonstrate outstanding performance, with the ensemble model achieving a remarkable accuracy of $99.1\%$ on test dataset in classifying skin lesions as malignant or benign. this achievement under-scores the effectiveness of ensemble modeling in skin cancer detection, particularly when integrating powerful architectures like ResNet, EfficientNet, and ***, our study highlights the importance of robust preprocessing techniques in optimizing model performance and ensuring reliable diagnostic outcomes. the findings of this research have significant implications for clinical practice, offering a promising avenue for improving early detection rates and ultimately enhancing patient *** research endeavors may explore the integration of additional datasets and validation on diverse populations to further validate the efficacy and generalizability of the proposed ensemble approach.

关键词： Training Image quality Accuracy computer architecture Feature extraction Skin Ensemble learning Reliability Lesions Skin cancer

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Towards Half-Precision Computation for Complex Matrices: A Case Study for Mixed Precision Solvers on GPUs

Towards Half-Precision Computation for Complex Matrices: A C...

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Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA)

作者： Ahmad Abdelfattah Stanimire Tomov Jack Dongarra Innovative Computing Laboratory University of Tennessee Knoxville USA

ISBN: (纸本)9781728159904

the use of low-precision computations is popular in accelerating machine learning and artificial intelligence (AI) applications. Hardware architectures, such as high-end graphics processing units (GPUs), now support native 16-bit floating-point arithmetic (i.e., half-precision). While half precision provides a natural 2×/4× speedup against the performance of single/double precisions, respectively, modern GPUs are equipped with hard- ware accelerators that further boost the FP16 performance. these accelerators, known as tensor cores (TCs), have a theoretical peak performance that is 8×/16× faster than FP32/FP64 performance, respectively. Such a high level of performance has encouraged researchers to harness the compute power of TCs outside AI applications. this paper presents a mixed-precision dense linear solver (Ax = b) for complex matrices using the GPU's TC units. Unlike similar efforts that have discussed accelerating Ax = b in real FP16 arithmetic, this paper focuses on complex FP16 precisions. the developed solution uses a “half-complex” pre- cision to accelerate the solution of Ax = b while maintaining complex FP32 precision accuracy. the proposed solver requires the development of a high-performance mixed-precision ma- trix multiplication (CGEMM-FP16) that accepts half-complex inputs, and uses the TCs' full-precision products and FP32 accumulations for the computation. We discuss two designs and their performance. Similar to the way fast GEMMs power the performance of LAPACK, the mixed-precision CGEMM- FP16 can enable the development of mixed-precision LAPACK algorithms. We illustrate this by integrating both CGEMM-FP16s into the development of mixed-precision LU factorizations of complex matrices. Finally, an iterative refinement solver is used to deliver complex FP32 accuracy using a preconditioned GMRES solver. Our experiments, conducted on V100 GPUs, show that the mixed-precision solver can be up to 2.5× faster than a full single-complex precision solver

关键词： Kernel Libraries Tensors Acceleration Graphics processing units computer architecture Standards

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Efficient and Low-Complexity Iterative Detectors for 5G Massive MIMO Systems

Efficient and Low-Complexity Iterative Detectors for 5G Mass...

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International Conference on Distributed computing in Sensor Systems (DCOSS)

作者： Robin Chataut Robert Akl Dept. of Computer Science and Engineering University of North Texas Denton Texas USA

ISBN: (数字)9781728143514

ISBN: (纸本)9781728198040

the global bandwidth shortage in the wireless communication sector has motivated the study and exploration of sub-6 GHz wireless access technology known as massive Multiple-Input Multiple-Output (MIMO). Massive MIMO groups together antennas at both transmitter and the receiver to provide high spectral and energy efficiency. Although massive MIMO provides enormous benefits, it has to overcome some fundamental implementation issues before it can be implemented for 5G networks. One of the fundamental issues in Massive MIMO systems is uplink signal detection, which becomes inefficient and computationally complex with a larger number of antennas. In this paper, we propose three iterative algorithms to address the issues of uplink signal detection in massive MIMO systems. the simulation results, compared to the traditional detection algorithms, show that the proposed iterative massive MIMO uplink signal detection algorithms are computationally efficient and can achieve near-optimal Bit Error Rate (BER) performance. Additionally, we propose novel hardware architectures for the proposed detection algorithms to identify the required physical components and their interrelationships.

关键词： MIMO communication Uplink Antennas Signal detection Detectors Base stations Iterative methods

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the block-based trace cache 99

The block-based trace cache

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Proceedings of the 26th annual international symposium on computer architecture

作者： Bryan Black Bohuslav Rychlik John Paul Shen Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA

ISBN: (纸本)9780769501703

the trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. this work presents a new block-based trace cache implementation that can achieve higher IPC performance with more efficient storage of traces. Instead of explicitly storing instructions of a trace, pointers to blocks constituting a trace are stored in a much smaller trace table. the block-based trace cache renames fetch addresses at the basic block level and stores aligned blocks in a block cache. Traces are constructed by accessing the replicated block cache using block pointers from the trace table. performance potential of the block-based trace cache is quantified and compared with perfect branch prediction and perfect fetch schemes. Comparing to the conventional trace cache, the block-based design can achieve higher IPC, with less impact on cycle ***: Using the SPECint95 benchmarks, a 16-wide realistic design of a block-based trace cache can improve performance 75% over a baseline design and to within 7% of a baseline design with perfect branch prediction. With idealized trace prediction, it is shown the block-based trace cache with an 1K-entry block cache achieves the same performance of the conventional trace cache with 32K entries.

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