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ASNet: Introducing Approximate Hardware to high-Level Synthesis of Neural Networks

ASNet: Introducing Approximate Hardware to High-Level Synthe...

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International symposium on Multiple-Valued Logic

作者： Saman Froehlich Lucas Klemmer Daniel Große Rolf Drechsler DFKI GmbH and Group of Computer Architecture University of Bremen Germany

ISBN: (数字)9781728154060

ISBN: (纸本)9781728154077

Approximate computing is a design paradigm which makes use of error tolerance inherent to many applications in order to trade off accuracy for performance. One classic example for such an application is machine learning with Neural Networks (NNs). Recently, LeFlow, a high-Level Synthesis (HLS) flow for mapping Tensorflow NNs into hardware has been proposed. the main steps of LeFlow are to compile the Tensorflow models into the LLVM Intermediate Representation (IR), perform several transformations and feed the result into a HLS tool. In this work we take HLS-based NN synthesis one step further by integrating hardware approximation. To achieve this goal, we upgrade LeFlow such that (a) the user can specify hardware approximations, and (b) the user can analyze the impact of hardware approximation already at the SW level. Based on the exploration results which satisfy the NN quality expectations, we import the chosen approx. HW components into an extended version of the HLS tool to finally synthesize the NN to Verilog. the experimental evaluation demonstrates the advantages of our proposed ASNet for several NNs. Significant area reductions as well as improvements in operation frequency are achieved.

关键词： Artificial neural networks Tools Hardware design languages Generators Libraries Hardware Complexity theory

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Cryogenic Alternative: CMOS Versus Dynamic-Based Logic

Cryogenic Alternative: CMOS Versus Dynamic-Based Logic

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Ali H. Hassan Puneet Gupta Sudhakar Pamarti Chih-Kong Ken Yang Department of Electrical and Computer Engineering University of California Los Angeles USA

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

Next-generation data-center computing requires high-performance energy-efficient servers. One counterintuitive approach to reduce energy is to lower the temperature of the processing elements even down to cryogenic temperatures of liquid nitrogen. If the processing load is reduced dramatically, the net energy cost is lower even considering the corresponding cooling cost. Operating at such temperatures will require one to utilize optimized devices and new circuit techniques. One technique is scaling down the threshold voltage of transistors which in turn allows the supply voltage to scale. Another technique is to leverage the reduced leakage and to use dynamic-based logic for processing. this paper utilizes a low-temperature low-threshold (LTLVT) model of a 14-nm FinFET device calibrated with measurements for cryogenic computing. A demonstration of a 16-bit NP-CMOS adder is presented for an energy-delay optimization up to 20X at 77K compared to 330K.

关键词： Costs Cooling Liquid nitrogen FinFETs threshold voltage Energy efficiency Logic

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Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only) 05

Accelerating mutual information-based 3D medical image regis...

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Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

作者： Jianchun Li Christos Papachristou Raj Shekhar Case Western Reserve University Cleveland OH University of Maryland Baltimore MD

ISBN: (纸本)9781595930293

Mutual information-based 3D image Registration algorithm is shown to be an accurate, robust and more general registration method for medical image processing. However, its potential application in clinic is jeopardized by its high computational costs. Like many other 3D imaging algorithms, 3D registration needs to process vast amount of image data. the intrinsic computing characteristics of the mutual information-based registration algorithm make it even more difficult to manage and cache the input data. In this paper, we introduce our FPGA-based computing platform and detail its application in accelerating the mutual information-based 3D image registration. this platform is designed to accelerate a series of 3D medical imaging algorithms dominated by local operations. It is a System-on-Chip (SoC) architecture with an intelligent data caching system for efficient data fetching and buffering. A reconfigurable multi-pipeline execution unit in the platform is designed to perform high-speed parallel computation. this unit can be customized according to different algorithm requirements to achieve high performance. the simulation results for accelerating the mutual information based registration with our platform show that a speed-up of about 30 can be achieved when compared to a single-CPU computer. Moreover, the platform can be easily reconfigured to accelerate other 3D medical imaging algorithms.

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A Hybrid Deep Transfer Learning Approach For the Detection Of Vector-Borne Diseases

A Hybrid Deep Transfer Learning Approach For The Detection O...

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International Conference on Contemporary computing and Informatics (IC3I)

作者： Inderpreet Kaur Amanpreet Kaur Sandhu Yogesh Kumar UIC Chandigarh University Gharuan Mohali India Department of CSE School of Technology Pandit Deendayal Energy University Gandhinagar Gujarat India

Vector-borne diseases considerably impact the worldwide population’s health and economic well-being. However, training deep-learning models requires significant time and training data. therefore, a unique hybrid transfer learning approach was proposed for detecting vector-borne diseases (VBD) to solve these issues while retaining high accuracy. In the first phase, malaria and Lyme benchmark datasets were obtained. then VGG16, VGG19, MobileNetV2, and DenseNet 169 were compared to the hybrid model results (MobileNetV2+DenseNet 169). the effectiveness of the hybrid transfer learning method was evaluated using several performance measures, namely precision, loss, accuracy, AUC and RMSE. On the malaria dataset, the proposed model (MobileNetV2+DenseNet 169) achieved the most excellent classification accuracy of 99.9%, and on the Lyme dataset, 99.3%.

关键词： Training Biological system modeling Computational modeling Transfer learning Training data computer architecture Predictive models

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Inter-Scanner Harmonization of high Angular Resolution DW-MRI Using Null Space Deep Learning

Inter-Scanner Harmonization of High Angular Resolution DW-MR...

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21st International Conference on Medical Image computing and computer-Assisted Intervention (MICCAI) / 8th Eurographics Workshop on Visual computing for Biology and Medicine (VCBM) / International Workshop on Computational Diffusion MRI (CDMRI)

作者： Nath, Vishwesh Parvathaneni, Prasanna Hansen, Colin B. Hainline, Allison E. Bermudez, Camilo Remedios, Samuel Blaber, Justin A. Schilling, Kurt G. Lyu, Ilwoo Janve, Vaibhav Gao, Yurui Stepniewska, Iwona Rogers, Baxter P. Newton, Allen T. Davis, L. Taylor Luci, Jeff Anderson, Adam W. Landman, Bennett A. Vanderbilt Univ EECS Nashville TN 37203 USA Vanderbilt Univ BME Nashville TN 37203 USA Vanderbilt Univ Biostat Nashville TN 37203 USA Middle Tennessee State Univ CS Murfreesboro TN 37132 USA Vanderbilt Univ Psychol Nashville TN 37203 USA Vanderbilt Univ VUIIS Nashville TN 37232 USA Vanderbilt Univ VUMC Nashville TN 37203 USA Univ Texas Austin BME Austin TX 78712 USA

ISBN: (纸本)9783030058319;9783030058302

Diffusion-weighted magnetic resonance imaging (DW-MRI) allows for non-invasive imaging of the local fiber architecture of the human brain at a millimetric scale. Multiple classical approaches have been proposed to detect both single (e.g., tensors) and multiple (e.g., constrained spherical deconvolution, CSD) fiber population orientations per voxel. However, existing techniques generally exhibit low reproducibility across MRI scanners. Herein, we propose a data-driven technique using a neural network design which exploits two categories of data. First, training data were acquired on three squirrel monkey brains using ex-vivo DW-MRI and histology of the brain. Second, repeated scans of human subjects were acquired on two different scanners to augment the learning of the network proposed. To use these data, we propose a new network architecture, the null space deep network (NSDN), to simultaneously learn on traditional observed/truth pairs (e.g., MRI-histology voxels) along with repeated observations without a known truth (e.g., scan-rescan MRI). the NSDN was tested on twenty percent of the histology voxels that were kept completely blind to the network. NSDN significantly improved absolute performance relative to histology by 3.87% over CSD and 1.42% over a recently proposed deep neural network approach. More-over, it improved reproducibility on the paired data by 21.19% over CSD and 10.09% over a recently proposed deep approach. Finally, NSDN improved generalizability of the model to a third in-vivo human scanner (which was not used in training) by 16.08% over CSD and 10.41% over a recently proposed deep learning approach. this work suggests that data-driven approaches for local fiber reconstruction are more reproducible, informative, precise and offer a novel, practical method for determining these models.

关键词： Diffusion HARDI DW-MRI Null space CSD Harmonization Inter-scanner Deep learning Histology

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Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: the LDPC Decoder Case

Shortening Design Time through Multiplatform Simulations wit...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： G. Falcao M. Owaida D. Novo M. Purnaprajna N. Bellas C.D. Antonopoulos G. Karakonstantis A. Burg P. Ienne Instituto de Telecomunicações Department of Electrical and Computer Engineering University of Coimbra Portugal Department of Computer and Communications Engineering University of Thessaly Greece École Polytechnique Fédérale de Lausanne Switzerland

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bit width and data representation. this is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on Open CL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. Open CL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpen CL (Silicon to Open CL), a tool that automatically converts Open CL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified Open CL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3× faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

关键词： Kernel Parity check codes Field programmable gate arrays Computational modeling Decoding Hardware Algorithm design and analysis

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An Optimal Wireless Transmission Strategy based on Coherent Beamforming and Successive Interference Cancellation for Edge computing

An Optimal Wireless Transmission Strategy based on Coherent ...

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International Conference on Mobile Ad-hoc and Sensor Networks, MSN

作者： Zhehao Li Lei Shi Yi Shi Yuqi Fan Zhenchun Wei Liaoyuan Wu School of Computer Science and Information Engineering HeFei University of Technology Hefei China Ministry of Education Engineering Research Center of Safety Critical Industrial Measurement and Control Technology Hefei China Intelligent Automation Inc. 15400 Calhoun Drive Rockville USA

ISBN: (数字)9781728199160

ISBN: (纸本)9781728192369

In general, edge devices and edge servers in edge computing environment communicate with each other by wireless network, which put forward a high requirement for end-to-end wireless communication performance. In this paper, we propose an optimal strategy by combining the coherent beamforming (CB) technique and the successive interference cancellation (SIC) technique for improving the performance of the edge device communications. CB technique can be used for expanding the transmitter's transmitting range, while SIC technique can be used for improving the receiver's receiving ability. However, when these two techniques are used jointly, interference will occur between transmitters and receivers, which makes the CB-SIC strategy hard to be designed. We first give the mathematical model based on CB-SIC and show it is difficult to solve directly. then, we design a heuristic algorithm called time slot loop allocation (TSLA) algorithm. TSLA is based on greedy strategy to obtain an approximate optimal solution. By using TSLA, the whole scheduling time will be divided into many time slots. In each time slot, we try to make as many edge devices as possible to transmit data to the server. these can increase the overall data throughput. In simulation, we compare CB-SIC wireless network with CB only, SIC only, and traditional multi-hop network. Simulation results show that the TSLA algorithm can improve the end-to-end communication performance in edge computing environment.

关键词： performance evaluation Silicon carbide Heuristic algorithms Wireless networks throughput Servers Edge computing

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Acacia-RDF: An X10-Based Scalable Distributed RDF Graph Database Engine

Acacia-RDF: An X10-Based Scalable Distributed RDF Graph Data...

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IEEE International Conference on Cloud computing, CLOUD

作者： Miyuru Dayarathna Isuru Herath Yasima Dewmini Gayan Mettananda Sameera Nandasiri Sanath Jayasena Toyotaro Suzumura WSO2 Inc. University of Moratuwa Dept of Computer Science & Engineering University of Moratuwa JST CREST The University of Tokyo

Linked data mining has become one of the key questions in high performance graph mining in recent years. However, the existing Resource Description Framework (RDF) database engines are not scalable and are less reliable in heterogeneous clouds. In this paper we describe the design and implementation of Acacia-RDF which is a scalable distributed RDF graph database engine developed with X10 programming language to solve this issue. Acacia-RDF partitions the RDF data sets into subgraphs following vertex cut paradigm. the partitioned data sets are persisted on secondary storage across X10 places. We developed a scalable SPARQL (an RDF query language) processor for Acacia-RDF which operates on top of partitioned RDF data. Furthermore, we designed and implemented a replication based fault tolerance mechanism for Acacia-RDF. We present performance results gathered from Acacia with different scales of LUBM (Lehigh University Benchmark) RDF benchmark data sets. We make a comparison of Acacia-RDF's performance against Neo4j graph database server. From the scalability experiments conducted upto 16 X10 places, we observed that Acacia-RDF scales well with LUBM data sets. Acacia-RDF reported less than ten seconds elapsed times on 16 places for running the first and the third queries of the LUBM benchmark on LUBM 160 universities data set with 3.6 million vertices and 28.5 million edges which was 1.7GB in size. through this work we describe and demonstrate the use of X10 language for development of scalable RDF graph data management systems.

关键词： Resource description framework Distributed databases Engines Fault tolerance Fault tolerant systems Servers computer architecture

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CCSF: Clustered Client Selection Framework for Federated Learning in non-IID Data 23

CCSF: Clustered Client Selection Framework for Federated Lea...

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Proceedings of the IEEE/ACM 16th International Conference on Utility and Cloud computing

作者： Aissa Hadj Mohamed Allan M de Souza Joahannes B D Da Costa Leandro A Villas Julio Cesar Dos Reis UNICAMP Campinas BR Institute of Computing UNICAMP Campinas BR

ISBN: (纸本)9798400702341

Federated Learning (FL) is a distributed approach where numerous devices train a shared global model for Machine Learning (ML) tasks. At every training round, the client devices must share their new local gradients with the central server to update the global model. Hence, FL requires high communication costs in terms of bandwidth and the number of messages exchanged between FL clients and the central server, leading to many issues, such as communication bottlenecks and scaling in the network. Consequently, having all devices participating in every training round is not practical. Moreover, the devices' local datasets are usually not Independent and Identically Distributed (IID), posing additional challenges for training the global model. In this sense, we introduce a Clustered Client Selection Framework (CCSF) to decrease the overall communication costs for training an ML model in the FL environment. CCSF clusters the client devices and employs a biased client selection strategy with two main objectives: (i) reducing the number of devices training at every round; and (ii) the number of rounds required to reach convergence. Our experimental evaluations, conducted on two well-known datasets, MNIST and MotionSense, show that CCSF is highly efficient, where the clients' local datasets can be grouped into homogeneous clusters. In MNIST, CCSF reaches an accuracy score above 60% in less than 50 rounds compared to FedAvg at 50% after 100 rounds. the performance gap is wider in the MotionSense data. CCSF reaches an accuracy score of 70% in a little more than 20 training rounds compared to FedAvg below 30% of accuracy in the first 100 FL rounds.

关键词： federated learning

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MacSim: A MAC-Enabled high-performance Low-Power SIMD architecture

MacSim: A MAC-Enabled High-Performance Low-Power SIMD Archit...

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Euromicro symposium on Digital System Design

作者： Tong Geng Luc Waeijen Maurice Peemen Henk Corporaal Yifan He Eindhoven University of Technology The Netherlands Xiamen University of Technology China

Single-Instruction-Multiple-Data (SIMD) architectures, which exploit data-level parallelism (DLP), are widely used to achieve high-performance and low-power computing. In most of streaming applications, such as CNN-based detection and recognition, color space conversion and various kinds of filters, multiply-accumulate is one of the most important and expensive operations to be executed. In this paper, we propose a high-performance low-power SIMD architecture with advanced multiply accumulator (MAC) support (MacSim) to improve the computational efficiency. In addition, a smart loop tiling scheme is proposed. To support this tiling even further, the MAC unit is equipped with multiple accumulator registers. According to the Design Space Exploration (DSE) of the proposed MAC unit, a MAC instance with four accumulator registers (MAC4reg) is selected as a good choice for target kernels. In this paper, a 64-PE 16-bit (processing element) SIMD instance without MAC support is taken as the baseline. For a head-to-head comparison, a 64-PE 16-bit SIMD with MAC4reg (MacSim4) and the baseline SIMD are all implemented in HDL and synthesized with a TSMC 40nm low-power library. Five streaming application kernels are mapped to both architectures. Our experimental results show with MAC4reg the runtime and energy consumption are reduced up to 38% and 42% respectively. Besides, a 4-layer CNN-based detection application is also fully mapped onto the proposed MacSim4. Working at 950MHz, MacSim4 reaches a throughput of 62.4 GOPS, which meets the requirement of real-time (720P HD, 30fps) detection. the energy consumption per PE per operation is very low, 4.7pJ/Op excluding SRAM (Static Random Access Memory) and 4.8pJ/Op including a 2k-entry SRAM bank. As a prototype, the proposed SIMD is mapped into an FPGA and can run all the kernels.

关键词： Registers computer architecture Kernel Parallel processing Energy consumption VLIW Pipelines

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