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high-Order QAM/APSK Receiver Design with Blind CFO Estimator of CORDIC-Based high-Order Power Pre-Processor for LEO Satellite Communications

High-Order QAM/APSK Receiver Design with Blind CFO Estimator...

引用

International Conference on Telecommunications and Signal Processing (TSP)

作者： Juinn-Horng Deng Pavan Vatal Shankar Prasad Yuan-Pei Wang Min-Sion Yang T. N. Vyas Kaushik P. R. Siva Prasanna Department of Electrical Engineering Yuan Ze University Taoyuan Taiwan R.O.C. School of Computing SASTRA University Thanjavur TamilNadu India

Low-Earth orbit (LEO) satellite communications are the research topics of 6G communication. high-order QAM/APSK communication transceiver design is the core research technology. Moreover, it pays more attention to overcoming the high-speed Doppler frequency offset problem of LEO. the blind frequency offset estimation technique is a popular solution. To achieve the blind estimator, the pre-processor of the high-order power operation is proposed to remove the coexisting high-order QAM/APSK signals. therefore, the pre-processed received signal reserves the pure frequency offset signals, which can be used for a phase-locked loop (PLL) to estimate the frequency offset. In this paper, we will propose the overall frequency/time/channel synchronization and demodulation schemes for the high-order QAM/APSK system. Besides, the pre-processing operation of high-order power, i.e., the 16th-order power operation used for 32QAM, is the key technology of hardware realization. the hybrid coordinate rotation digital computer (CORDIC) techniques are proposed to jointly complete the high-order power operations. Finally, the software-defined radio (SDR) platform confirms that the proposed transceiver with the hardware realization exhibits the excellent performance.

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Design & Verification of AMBA AHB-Lite Memory Controller

Design & Verification of AMBA AHB-Lite Memory Controller

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IEEE Annual computing and Communication Workshop and Conference (CCWC)

作者： Anila Kommineni Manoj Kumar Gundu Youngsoo Kim Shrikant Jadhav Dept. of Electrical Engineering San Jose State University San Jose USA Dept. of Electrical and Computer Engineering Bradley University Peoria USA

As technology advances, the on-chip communication bus architecture becomes increasingly prominent in interconnecting various components within the System-on-Chip (SoC). the standard ARM AMBA on-chip interconnect bus is designed as an SoC system's high-performance backbone bus, which supports faster communication with internal and external memories. this paper presented a memory controller design with an AMBA 3 AHB_Lite standard based on a single master and multiple slave model. We verified the design as per the specifications of ARM using a System Verilog verification environment and functional coverage. Various testbench verification environment components such as transaction and generator (which generates the input stimulus), Driver (which drives input data to the Design Under Test (DUT)), Monitor (which monitors the signals from the DUT), and the Scoreboard (which reports about the design working condition) are developed to test single burst, wrapping, and increment bursts of various sizes (4, 8, and 16 beats) with waited transfer responses of the AHB_Lite protocol. We also observed different corner cases during burst and wrap transfer.

关键词： Employee welfare Protocols Program processors Conferences Generators System-on-chip Hardware design languages

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Smart Waste Management: VGG16-Based Classification System for Organic and Recyclable Materials

Smart Waste Management: VGG16-Based Classification System fo...

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International Conference on Circuit, Power and computing Technologies (ICCPCT)

作者： Poonam Shourie Vatsala Anand Deepak Upadhyay Swati Devliyal Sheifali Gupta Chitkara University Institute of Engineering and Technology Chitkara University Punjab India Computer Science and Engineering Graphic Era Hill University Dehradun Uttarakhand India Computer Science & Engineering Graphic Era Deemed to Be University Dehradun Uttarakhand India

ISBN: (数字)9798350372816

ISBN: (纸本)9798350372823

In today’s world, waste management is a major concern, and efficient trash classification and sorting are becoming more and more necessary. this work uses the VGG16 deep learning architecture to offer a novel garbage classification method that focuses on organic and recyclable materials. Convolutional neural networks like VGG16 are well-known for their superior performance in image classification applications. the goal of this project is to create an accurate and effective automated garbage sorting system based on visual analysis of waste photos by utilising the VGG16 model. the process entails using a dataset of photos of different waste items to train the VGG16 model, with a focus on organic and recyclable material differentiation. the collection has been carefully selected to contain a variety of garbage products that are frequently seen in actual waste management situations. the VGG16 model is extensively trained and fine-tuned, enabling the system to identify important visual cues linked to the categories of organic and recyclable garbage. Evaluating the efficacy of the suggested trash classification system involves employing metrics like F1score, recall, accuracy, and precision. Furthermore, testing on unknown datasets and cross-validation are used to evaluate the model’s robustness and generalization abilities. the outcomes show how well the VGG16-based method works to precisely identify and classify recyclable and organic waste materials with high recall rates.

关键词： Waste management Training Visualization Waste materials Accuracy throughput Robustness

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Efficient reduction of HOL blocking in multistage networks

Efficient reduction of HOL blocking in multistage networks

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： T. Nachiondo J. Flich J. Duato Department of Computer Engineering Universidad Politécnica de Valencia Valencia Spain

Head-of-line blocking is one of the main problems arising in input-buffered switches. the best-known solution to this problem consists of using virtual output queues (VOQs). However this strategy is not scalable. Its implementation cost increases quadratically with the number of ports in the switch. Taking into account current trends, the demand for larger number of ports in high-performance switches is likely to increase very rapidly in the future. therefore, a scalable and cost-effective solution is required. In this paper we propose an efficient and cost-effective strategy (belonging to a family of strategies previously proposed, referred to as destination-based buffer management (DBBM)), to reduce HOL blocking in single-stage and multistage networks. the proposed strategy is based on allowing certain destinations to share the same queue. Its main purpose is to maximize network throughput whereas keeping HOL blocking to negligible values. In this paper, we apply the strategy at every switch included in a bidirectional multistage network (BMIN). We have evaluated DBBM, VOQ, and alternative strategies in different BMIN sizes and with different traffic conditions (synthetic traffic, IP traces, and I/O traces). Results show that DBBM with a reduced number of queues at each switch obtains roughly the same throughput as the VOQ mechanism. Moreover, VOQ at the switch level (as many queues as output ports at every switch) has also been analyzed. Results demonstrate that it does not scale. As the number of stages in the network increases, the VOQ solution at the switch level introduces more HOL blocking that leads to a severe degradation in network throughput. With the DBBM using 16 queues, maximum network throughput is sustained for all the traffic cases analyzed. Moreover, as the network size increases (up to a 2048 /spl times/ 2048 BMIN), DBBM keeps roughly the same performance with the same number of queues.

关键词： Intelligent networks Switches throughput Costs Telecommunication traffic Traffic control Queueing analysis Degradation Distributed computing Concurrent computing

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BrainSegNeT: A Lightweight Brain Tumor Segmentation Model Based on U-Net and Progressive Neuron Expansion 16th

BrainSegNeT: A Lightweight Brain Tumor Segmentation Model Ba...

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16th International Conference on Brain Informatics, BI 2023

作者： Ghose, Partho Biswas, Milon Gaur, Loveleen Jagannath University Dhaka1100 Bangladesh Department of Computer Science University of Alabama Birmingham United States School of Computer Science Taylor’s University Subang Jaya Malaysia

ISBN: (纸本)9783031430749

Brain tumor segmentation is a critical task in medical image analysis. In recent years, several deep learning-based models have been developed for brain tumor segmentation using magnetic resonance imaging (MRI) data. To address challenges such as high computational time and the requirement of huge storage and resources, we proposed BrainSegNet, which is a lightweight extension of U-Net with progressively expanded neurons that require fewer weights and less memory space. Unlike other DL models, our proposed model has the simplest architecture and is more accurate than other state-of-the-art methods for brain tumor segmentation. the proposed approach was extensively analyzed using the BraTS2020 benchmark dataset for segmenting brain tumors. the experimental findings demonstrate the effectiveness of the proposed system, producing a 96.01% Dice score and 95.89% mean IoU for brain tumor segmentation from brain MRI images. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Magnetic resonance imaging

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MIC-SVM: Designing a highly Efficient Support Vector Machine for Advanced Modern Multi-core and Many-Core architectures

MIC-SVM: Designing a Highly Efficient Support Vector Machine...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： Yang You Shuaiwen Leon Song Haohuan Fu Andres Marquez Maryam Mehri Dehnavi Kevin Barker Kirk W. Cameron Amanda Peters Randles Guangwen Yang Tsinghua National Laboratory for Information Science and Technology (TNList) Tsinghua University Beijing China Pacific Northwest National Lab Richland WA USA Ministry of Education Key Laboratory for Earth System Modeling Tsinghua University Beijing China MIT Computer Science and Artificial Intelligence Laboratory Cambridge MA USA Virignia Tech Blacksburg VA USA Lawrence Livermore National Lab Livermore CA USA

ISBN: (纸本)9781479938018

Support Vector Machine (SVM) has been widely used in data-mining and Big Data applications as modern commercial databases start to attach an increasing importance to the analytic capabilities. In recent years, SVM was adapted to the field of high performance computing for power/performance prediction, auto-tuning, and runtime scheduling. However, even at the risk of losing prediction accuracy due to insufficient runtime information, researchers can only afford to apply offline model training to avoid significant runtime training overhead. Advanced multi- and many-core architectures offer massive parallelism with complex memory hierarchies which can make runtime training possible, but form a barrier to efficient parallel SVM design. To address the challenges above, we designed and implemented MIC-SVM, a highly efficient parallel SVM for x86 based multi-core and many-core architectures, such as the Intel Ivy Bridge CPUs and Intel Xeon Phi co-processor (MIC). We propose various novel analysis methods and optimization techniques to fully utilize the multilevel parallelism provided by these architectures and serve as general optimization methods for other machine learning tools. MIC-SVM achieves 4.4-84x and 18-47x speedups against the popular LIBSVM, on MIC and Ivy Bridge CPUs respectively, for several real-world data-mining datasets. Even compared with GPUSVM, run on a top of the line NVIDIA k20x GPU, the performance of our MIC-SVM is competitive. We also conduct a cross-platform performance comparison analysis, focusing on Ivy Bridge CPUs, MIC and GPUs, and provide insights on how to select the most suitable advanced architectures for specific algorithms and input data patterns.

关键词： Support vector machines Training computer architecture Parallel processing Microwave integrated circuits Equations Bridges

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FPGA-accelerated Automatic Alignment for three-dimensional Tomography

FPGA-accelerated Automatic Alignment for Three-dimensional T...

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Annual IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Shuang Wen Guojie Luo School of Mathematical Sciences Peking University Department of Computer Science Peking University

ISBN: (数字)9781728158037

ISBN: (纸本)9781728158044

In the process of tomographic reconstruction, the attitude and center point of a specimen, from which the projection data are collected, suffer from misalignment due to mechanical imperfection and calibration error. Such misalignment leads to poor reconstruction quality. And effective automatic alignment approaches have been proposed. the alignment approaches are of good use for kinds of application scenarios such as X-CT and electron tomography. these scenarios demand not only high performance, but also that the component of automatic alignment can be integrated and upgraded in the whole solution. thus, we propose an FPGA accelerator for state-of-the-art tomographic alignment algorithm. We first introduce a multi-ray access approach that modifies the order of data access for easier on-chip data management. Making use of BRAMs on FPGAs and effective local data management strategy, data reuse is reinforced, and data transfer latency with DRAM is covered by computation. Also, we introduce an FPGA-customized processing engine at a low cost to improve data throughput. Moreover, a streaming structure with multiple paralleled PEs further improves the performance of our algorithm. Experiments demonstrate that our accelerator achieves a 44. 5x speed-up for the state-of-the-art alignment on Xilinx ZCU102 over a 16-thread multicore CPU implementation, and a 1. 60x speed-up with 7. 8x energy reduction over an OpenCL implementation on Nvidia Titan V.

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Black-Bus: a new data-transfer technique using local address on networks-on-chips

Black-Bus: a new data-transfer technique using local address...

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International symposium on Parallel and Distributed Processing (IPDPS)

作者： K. Anjo Y. Yamada M. Koibuchi A. Jouraku H. Amano Department of Information and Computer Science Keio University Yokohama Japan

Summary form only given. Network-on-a-chip (NoC) has received attention as a high-performance interconnect, because traditional buses, which can't transfer more than one data-stream simultaneously, are more likely to become a bottleneck. Since some concepts of NoC have been proposed by simply borrowing the networking structure of parallel computers or system area networks (SANs), it tends to require complicated network interface logic in all the nodes. We propose a novel data-transfer method called Black-Bus as a NoC. In Black-Bus, a local identifier (ID) is attached to each raw data as routing information. Unlike the traditional packet transfer, the local ID is transferred on dedicated wires attached to data lines to remove complicated packet generation procedure in a node. Only a small-sized local ID is required to specify routing tags to the destination, and intermediate routers change it to solve local ID conflicts between paths on a physical channel. the required local ID and routing table sizes for the Black-Bus router are evaluated with access trace data of NAS parallel benchmarks for on-chip multiprocessors, and JPEG codec as stream processing. Evaluation results show that most of the applications require only at most 3 bits for the local ID in a 16-node system. And the Black-Bus data-transfer reduces up to 75% of routing tags compared with global addressing scheme used in the traditional packet networks.

关键词： Network-on-a-chip Routing LAN interconnection computer interfaces computer networks Concurrent computing Network interfaces Logic Wires Codecs

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A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor 36

A systematic methodology to compute the architectural vulner...

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： S.S. Mukherjee C. Weaver J. Emer S.K. Reinhardt T. Austin VSSAD MMDC Intel Corporation Shrewsbury MA USA Advanced Computer Architecture Lab EECS Department University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780769520438

Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transients faults exist, but come at a cost. Designers clearly require accurate estimates of processor error rates to make appropriate cost/reliability tradeoffs. this paper describes a method for generating these estimates. A key aspect of this analysis is that some single-bit faults (such as those occurring in the branch predictor) do not produce an error in a program's output. We define a structure's architectural vulnerability factor (AVF) as the probability that a fault in that particular structure do not result in an error. A structure's error rate is the product of its raw error rate, as determined by process and circuit technology, and the AVF. Unfortunately, computing AVFs of complex structures, such as the instruction queue, can be quite involved. We identify numerous cases, such as prefetches, dynamically dead code, and wrong-path instructions, in which a fault do not affect, correct execution. We instrument a detailed 1A64 processor simulator to map bit-level microarchitectural state to these cases, generating per-structure AVF estimates. this analysis shows AVFs of 28% and 9% for the instruction queue and execution units, respectively, averaged across dynamic sections of the entire CPU2000 benchmark suite.

关键词： Microprocessors Circuit faults Error analysis Costs computer aided instruction Fault diagnosis Prefetching Instruments Computational modeling Circuit simulation

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Trinity: A General Purpose FHE Accelerator

Trinity: A General Purpose FHE Accelerator

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IEEE/ACM International symposium on Microarchitecture (MICRO)

作者： Xianglong Deng Shengyu Fan Zhicheng Hu Zhuoyu Tian Zihao Yang Jiangrui Yu Dingyuan Cao Dan Meng Rui Hou Meng Li Qian Lou Mingzhe Zhang Key Laboratory of Cyberspace Security Defense Institute of Information Engineering CAS Beijing China School of Cyber Security University of Chinese Academy of Sciences Beijing China University of Electronic Science and Technology of China Chengdu China Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China University of Illinois Urbana-Champaign IL USA University of Central Florida Orlando FL USA

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Fully Homomorphic Encryption (FHE) is crucial for privacy-preserving computing, which allows direct computation on encrypted data. While various FHE schemes have been proposed, none of them efficiently support both arithmetic FHE and logic FHE simultaneously. To address this issue, researchers explore the combination of different FHE schemes within a single application and propose algorithms for the conversion between them. Unfortunately, all prior ASIC-based FHE accelerators are designed to support a single FHE scheme, and none of them supports the acceleration for FHE scheme conversion. this necessitates FHE acceleration systems to integrate multiple accelerators for different schemes, leading to increased system complexity and hindering performance enhancement. In this paper, we present the first multi-modal FHE accelerator based on a unified architecture, which efficiently supports CKKS, TFHE, and their conversion scheme within a single accelerator. To achieve this goal, we first analyze the theoretical foundations of the aforementioned schemes and highlight their composition from a finite number of arithmetic kernels. then, we investigate the challenges for efficiently supporting these kernels within a unified architecture, which include 1) concurrent support for NTT and FFT, 2) maintaining high hardware utilization across various polynomial lengths, and 3) ensuring consistent performance across diverse arithmetic kernels. To tackle these challenges, we propose a novel FHE accelerator named Trinity, which in-corporates algorithm optimizations, hardware component reuse, and dynamic workload scheduling to enhance the acceleration of CKKS, TFHE, and their conversion scheme. By adaptive select the proper allocation of components for NTT and MAC, Trinity maintains high utilization across NTTs with various polynomial lengths and imbalanced arithmetic workloads. the experiment results show that, for the pure CKKS and TFHE workloads, the performance of our Trinity outp

关键词： Heuristic algorithms computer architecture Dynamic scheduling Hardware Polynomials Cryptography Kernel Homomorphic encryption Optimization Arithmetic

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